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`Global Foundaries US v. Godo Kaisha
`Global Ex. 1010
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`Page 1 of 15
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`U.S. Patent Mar. 26, 1985
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`Fig. 4
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`Sheetlof7
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`Fig.2(a)
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`Pt.
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`Fig.2(b)
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`LLYA[Pky 23
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`U.S. Patent Mar. 26, 1985
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`Sheet 2 of 7
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`4,506,434
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`Fig.2(c)
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`Fig.2(d)
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`llef
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`24
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`Fig.2(e)
`ON 24
`°
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`(?
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`Fig.2(f)
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`U.S. Patent Mar.26,1985§Sheet30f7 4,506,434
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`Fig.3
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`32
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`34
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`WL)
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`Mf
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`Fig.4(a)
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`TT
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`Page 4 of 15
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`U.S. Patent Mar.26,1985
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`Fig. 4(c)
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`rain
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`Fig.(d)
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`Fre
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`4
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`Fig(e)
`TTT i
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`U.S. Patent Mar. 26,1985
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`Fig.5(a)
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`NFae 96=ah
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`Page 6 of 15
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`U.S. Patent Mar.26,1985
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`G4
`Fig.“a)
`DTh
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`TDINpealLULL 16
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`FT
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`Fig.7(b)
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`Page 7 of 15
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`U.S. Patent Mar. 26, 1985
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`Sheet 7 of7
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`eeeiyBYEee}
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`Page 8 of 15
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`1
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`4,506,434
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`METHOD FOR PRODUCTION OF
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`SEMICONDUCTOR DEVICES
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`2
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`this
`Depending on the etching process employed,
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`improved prior art methodis classified into two inde-
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`pendent categories.
`The first is the case wherein a dry etching process is
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`BACKGROUND OF THE INVENTION
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`employed. Referring to FIG. 2(a), the first step is to
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`employ a chemical vapor deposition process for the
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`1. Field of the Invention
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`purpose of growing an insulating layer 22 onasilicon
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`The present invention relates to methods for produc-
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`(Si) substrate 21 which is provided with grooves 23
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`tion of semiconductor devices, and morespecifically to
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`surrounding mesa shaped portions 24 in which elements
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`an improvement applicable to methods for production
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`are to be fabricated, before a photoresist layer 25 is
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`of buried insulating layers each of which surrounds a
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`coated on the uneven surface of the insulating layer 22.
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`portion of a semiconductor substrate in which elements
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`As a result, the top surface of the photoresist layer 25
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`are fabricated, the buried insulating layers functioning
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`becomesflat. Referring to FIG. 2(6), the secondstepis
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`to isolate from one another, each element fabricated in
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`to employ a dry etching process which has a single
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`a chip.
`etching rate regardless of the quality of the material to
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`2. Description of the Prior Art
`be etched, to the substrate 21 covered bythe insulating
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`There is now a tendency inwhich the dimensions of
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`layer 22 and by the photoresist layer 25. As a result, the
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`insulating layer 22 remains only in the groove 23, and
`each element is decreased in order to satisfy require-
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`the top surface of the silicon (Si) substrate 21 becomies
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`ments for a larger quantity of elements fabricated in a
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`uncovered, During this process, however,
`the ion
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`chip and also for a larger quantity of elements fabri-
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`beams employed for the dry etching process readily
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`cated in the unit area of a chip. Such requirements are
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`produce damaged areas C along the top surface of the
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`included in the requirements effective to satisfy the
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`mesa shaped portion 24 of the silicon (Si) substrate 21 in
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`ultimate purposes for development of LSI’s and further
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`which elements are to be fabricated. These damaged
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`of VLSI’s. Insofar as the processes for isolating each
`areas can cause unsatisfactory characteristics for ele-
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`element fabricated in one chip from one another are
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`ments fabricated in the substrate 21. It is quite natural
`concerned, a process which is called local oxidation of
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`that the silicon (Si) substrate must be exposed to a plu-
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`silicon is available, and it is well knownthat this process
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`rality of high temperature processes such as oxidation
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`has various advantagesin the aspects of easy production
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`and annealing for repairing the damage caused by appli-
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`of durable wiring whichis free from potential discontin-
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`cation of ion implantation processes and the like, during
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`uation thereof and the potential employment ofself-
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`later processes for production of elements therein. Re-
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`alignment and the like. However, this local oxidation
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`ferring to FIG. 2(c), since the foregoing high tempera-
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`process has drawbacks. Thefirst is the problem ofbird’s
`ture processes are involved with non-uniform variation
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`beak. Referring to FIG. 1, local oxidation of the top
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`of density of the insulating layer 22, this variation causes
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`surface of a silicon (Si) substrate 11, having a limited
`strains E; and/or E2 to occur at the corners of the mesa
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`area covered bya silicon nitride (Sig3N4) layer mask 12,
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`shaped portion 24 of the substrate 21 surrounded by the
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`is accompanied by lateral growth ofa silicon dioxide
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`buried insulating layer 22. These strains are also param-
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`(SiO2) layer 13. This lateral growth producesa silicon
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`eters for causing unsatisfactory characteristics for ele-
`ments fabricated in the substrate 21.
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`dioxide (SiO2) layer having a bird’s beak shape which
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`40
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`extends underthe silicon nitride (SizN4) layer 12. The
`The secondis the case wherein a wet etching process
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`lateral length A of this bird’s beak causes a degradation
`is employed. Referring to FIG. 2(d), the first step is to -
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`of dimensional accuracy. The secondis the problem of
`employ a dry etching process to remove the photoresist
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`layer 25 from the areas on which elements are to be
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`strain which is producedin the portion B ofthesilicon
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`fabricated, leaving the photoresist layer 25 only along
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`substrate 11. The portion B directly contacts the layer
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`the grooves. Referring to FIG. 2(e), the second step is
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`13 of silicon dioxide (SiOz) which is converted from
`to employ a wet etching process to removethe insulat-
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`silicon (Si) during the oxidation process which inevita-
`ing layer 22 from the areas on which elements are to be
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`bly causes expansion in volume of the nitride. This
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`fabricated, leaving the insulating layer 22 only in the
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`strain, appearing in the silicon (Si) layer B, can cause
`grooves 23. Since the grooves 23 have sharp corners at
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`unsatisfactory characteristics in elements fabricated in
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`the bottom and top edges, the density of the insulating
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`the silicon (Si) layer. The third is the problem of white
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`layer 22 is not entirely uniform and the density thereof
`ribbon. Since it is not easy to completely remove the
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`is less along the broken lines shown in each of FIGS.
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`silicon nitride (Si3N«4) layer 12, numerous minute parti-
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`2(a), 2(6), 2(d) and 2(e) than in the other regions. Since
`cles of the nitride remain on the surface of the silicon
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`a material having a lower density has a larger etching
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`(Si) substrate 11 in the form of scattered stains. These
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`rate, recesses D are produced along the edges of the
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`residual nitride particles function as a type of mask
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`insulating layers 22 which are buried in the silicon (Si)
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`during oxidation processes carried outin later steps.
`substrate 21. As a result, the surface of a chipis not flat,
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`The above process results in a local oxidation process
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`causing the possibility of discontinuity and/or dimen-
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`whichis not necessarily satisfactory for the production
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`sional errors for wires which are placed along thesili-
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`of a semiconductor device having minute patterns. To
`con (Si) substrate 21.
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`overcome the foregoing drawbacks, a method wherein
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`To prevent occurrence of the foregoing recesses D
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`each element is isolated from one another by buried
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`along the edges of the insulating layer 22, an annealing
`insulating layers which are grownto fill grooves pro-
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`process is ordinarily employed after the completion of
`duced along the surface of a silicon (Si) substrate to
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`the insulating layer 22. Albeit this annealing process is
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`surround each element, has been developed andis pres-
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`effective to unify or make uniform the density of the
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`ently being used. Unfortunately, however,
`this im-
`insulating layer 22 even in the portions along the broken
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`proved method has other drawbacks described below,
`lines shown in FIG.2, differences in the amount of the
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`coefficient of expansion between the material of the
`with reference to the drawings.
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`Page 9 of 15
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`4,506,434
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`3
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`substrate and the material of the insulating layer causes
`stresses to occur along the interfaces of both materials,
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`since the stresses are concentrated along the edges. As a
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`result, strains E; and/or E2 occur along the edges of the
`elementfabrication areas of the substrate 21 surrounded
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`by the buried insulating layer 22 in FIG. 2(). These
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`strains are also parameters for causing unsatisfactory
`characteristics for elements fabricated in the substrate
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`21.
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`4
`duction of a semiconductor device in accordance with
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`the present invention. Since a thermal! strain absorbing
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`layer 32 is interleaved between the top surface of a
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`semiconductor substrate 31 and an insulator layer 33
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`ing layer, strains E; occur along the edges of the ther-
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`mal strain absorbing layer 32 rather than along the top
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`ductor substrate 31, during an annealing process which
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`ing layer 33. During a dry etching process which is
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`33, damaged areas G are producedin the thermal strain
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`absorbing layer 32 rather than in the semiconductor
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`substrate 31. As a result, the portions of the semicon-
`ductor substrate 31 in which elements are to be pro-
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`duced are protected from potential strains and damage,
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`thereby enabling the characteristics of the elements to
`be enhanced. Since the strains E, do not occur in the
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`semiconductor substrate 31 and since the magnitude of
`stress which may cause strains E2is limited, the amount
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`of strains Ez which occurs along the bottom edges of
`the element fabrication areas 34 of the semiconductor
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`substrate surrounded by the buried insulating layersis
`also decreased.
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`The requirements for the thermal strain absorbing
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`layer are (a) that the material will have to be chemically
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`stable under an annealing temperature of approximately
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`900° C. or higher and (b) that the material readily ab-
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`sorbs strains. Exemplary materials satisfying these re-
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`quirementsare polycrystallinesilicon (Si), molybdenum
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`silicide (MoSiz), tungsten silicide (WSi), titanium sili-
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`cide (TiSiz) and tantalum silicide (TaSiz).
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`Silicon dioxide (SiO2), silicon nitride (Si3N4) and
`aluminum oxide (Al203) can be selected as the material
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`of the buried insulating layer.
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`Notonly silicon (Si) but also any of the compound
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`semiconductors including galium-arsenic (GaAs), indi-
`um-phosphorus (InP) et al can be selected as the mate-
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`rial of the semiconductor substrate.
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`To achieve the foregoing second object, a method for
`production of a semiconductor device in accordance
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`with the other embodiment of the present invention
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`comprises, in addition to the steps specified above for
`the method for production of a semiconductor device in
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`accordance with the present invention, a step to pro-
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`duce a conductive layer on the thermal strain absorbing
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`layer and on the buried insulating layer and a step to
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`pattern the conductive layer to a shape corresponding
`to the gate electrode and someof the conductive wires.
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`Materials selected as a material for the conductive
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`layer are molybdenum silicide (MoSiz), tungsten silicide
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`(WSiy),
`titanium silicide
`(TiSiz),
`tantalum silicide
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`(TaSiz) and polycrystalline silicon (Si).
`BRIEF DESCRIPTION OF THE DRAWINGS
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`The present invention, together with its various fea-
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`tures and advantages, can be readily understood from
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`the following more detailed description presented in
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`conjunction with the following drawings.
`FIG.1 is a cross-sectional view of a silicon (Si) sub-
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`strate showing the position after the compietion of a
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`prior art local oxidation process.
`FIGS.2(a), 2(5), 2(c), 2(¢), 2(e) and 2(/) are cross-sec-
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`tional views of silicon (Si) substrates, each of which
`showsthe state after the completion of each of the
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`major steps of a method for production of a buried
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`SUMMARY OF THE INVENTION
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`An object of the present invention is to provide a
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`method for producing a semiconductor device having a
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`plurality of elements each of whichis isolated from one
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`another by buried insulating layers, wherein an im-
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`provementis made(a) to prevent strains E; which may
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`otherwise occur along the top edges of the element
`fabrication areas of the semiconductor substrate sur-
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`rounded by buried insulating layers which function to
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`isolate each element from one another, from occurring
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`during an annealing process which is carried out to
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`unify the density of the insulating layer, (b) to decrease
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`the amountof strains Ez which occur along the bottom
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`edges of the element fabrication areas of the semicon-
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`ductor substrate surrounded by buried insulating layers
`which function to isolate each element from one an-
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`other during the annealing process whichis carried. out
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`to unify the density of the insulating layer and (c) to
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`prevent damaged areas C which may otherwise be pro-
`duced along the element fabrication areas of a semicon-
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`ductor substrate surrounded by buried insulating layers,
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`from being produced during a dry etching process
`whichis carried out to remove a part of the insulating
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`layer which is grown on the semiconductor substrate
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`leaving the other part of the insulating layer in grooves
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`surrounding the element fabrication areas of the semi-
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`conductorsubstrate, the remaining part of the insulating
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`layer being the buried insulating layer which functions
`as an isolation region.
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`The other object of the present invention is to pro-
`vide a method for production of a semiconductor de-
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`vice having a plurality of elements each of which has
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`satisfactory quality due to lack of damagein the element
`fabrication areas of the semiconductor substrate sur-
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`rounded by buried insulating layers which function to
`isolate each element from one another, wherein an im-
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`provementis madeto simplify the steps for production
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`of wiring.
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`To achieve the foregoing first object, a method for
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`production of a semiconductor device in accordance
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`with the present invention comprises a step of growing
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`a thermal strain absorbing layer onat least a portion of
`the top surface of a semiconductor substrate, the por-
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`tion being an area which is not an area which becomes
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`an isolation area, a step of producingat least one groove
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`along said area which becomesan isolation area, a step
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`of inlaying an insulator in said at least one groove, and
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`a step of annealing said insulator.
`The concept of the present invention is to interleave
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`a thermal strain absorbing layer between the top surface
`of a semiconductor substrate and an insulating layer, of
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`whicha part is to becomea buried insulating layer, for
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`the purpose of allowing the thermal strain absorbing
`layer to absorb strains which may otherwise occur due
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`to an annealing process and to prevent damage which
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`may otherwise be produced byirradiation of ion beams.
`FIG. 3 shows the cross-sectional view of a semicon-
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`ductor device produced employing a method for pro-
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`45
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`Page 10 of 15
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`Page 10 of 15
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`6
`5
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`insulating layer which functions asisolation, according
`line silicon (Si) layer 43 is to absorb, strain and damage.
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`Therefore, this layer 43 can be replaced by a molybde-
`to the prior art.
`FIG.3 is a cross-sectional view of a semiconductor
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`num silicide (MoSi2) layer, a tungsten silicide (WSi2)
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`device produced employing a method for production of
`layer, a titanium silicide (TiSiz) layer, a tantalum silicide
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`(TaSig) layer or the like, insofar as the annealing tem-
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`a semiconductor device in accordance with the present
`invention.
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`perature range is 900° through 1,100° C. This is because
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`these materials are stable from the chemical viewpoint
`FIGS.4(a), 4(8), 4(c), 4(@) and 4(e) are cross-sectional
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`in the foregoing temperature range and readily absorb
`viewsofsilicon (Si) substrates, each of which showsthe
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`state after the completion of each of the major steps of
`strains. A photoresist layer 44 is produced on the sur-
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`face of polycrystalline silicon (Si) layer 43, before a
`a method for production of a semiconductor device in
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`patterning process is applied to the photoresist layer 44
`accordance with one embodimentof the present inven-
`tion.
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`for the purpose of producing grooves along the area
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`corresponding to the area in which a buried insulating
`FIGS. 5(a), 5(6) and 5(c) are cross-sectional views of
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`layer is produced. A thickness of the layer 43 is thicker
`silicon (Si) substrates, each of which shows thestate
`than 500 A for absorb.
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`after the completion of each of the major steps of a
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`the patterned photoresist
`Referring to FIG. 4(b),
`method for production of a semiconductor device in
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`layer 44 functions as a mask during a parallel plate type
`accordance with another embodiment of the present
`invention.
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`reactive ion etching process applied io the substrate for
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`the purpose of partly removing the polycrystalline sili-
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`FIG. 6 is a cross-sectional view of a complementary
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`con (Si) layer 43, the silicon (Si) substrate 41 for the
`MOS (C-MOS) semiconductor device produced em-
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`ultimate purpose to produce grooves 45 having the
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`ploying a method of production in accordance with a
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`third embodiment of the present invention.
`depth of 6,500 A in the silicon (Si) substrate 41. A car-
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`bon fluoride (CF4) gas containing oxygen (O2) by 5% is
`FIGS. 7(a) and 7() are cross-sectional views, of
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`employed as the reactive gas and an etching rate of 200
`which the former and the latter respectively show an
`A/min.is realized at a pressure of 5X 10—3 Torr. After
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`intermediate state of and the state after the completion
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`the photoresist layer 44 is entirely removed, a low pres-
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`of a process for production of a 1-transistor and 1-
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`capacitor type dynamic random access memorycellin
`sure chemical vapor deposition process is employed to
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`growasilicon dioxide (SiO) layer 47 having a thick-
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`accordance with a fourth embodiment of the present
`invention.
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`ness of 8,000 A whichentirely covers the top surface of
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`FIGS.
`8(a@) and 8(5) are cross-sectional views, of
`the substrate 41. Thereafter, the substrate is subjectedto .
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`an annealing process for 20 minutes in the nitrogen (N2)
`which the former and the latter respectively show an
`intermediate state of and a state after the completion of
`gas at a temperature of 1,000° C. for the purpose of
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`unifying or making uniform the density of the silicon
`a process for production of a bipolar type integrated
`circuit device in accordance with a fifth embodiment of
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`dioxide (SiO2) layer 47. Albeit strains may occurin the
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`35
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`polycrystalline silicon (Si) layer 43 during this process,
`the present invention.
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`the entire portion ofthe silicon (Si) substrate 41 is main-
`DETAILED DESCRIPTION OF THE
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`tained free from strains. In other words, potential strains
`PREFERRED EMBODIMENTS
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`which might otherwise occur along the edges of the
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`element fabrication area 46 of the silicon (Si) substrate
`In the following description, one of each embodiment
`40
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`41 surrounded by the buried insulating layer 47, are
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`in accordance with the present invention will be pres-
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`absorbed by the polycrystalline silicon (Si) layer 43.
`ented, on the assumption that FET’s are produced in a
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`The top surface ofthe silicon dioxide (SiO2) layer 47 is
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`silicon substrate, such FET’s being isolated from one
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`coated by a photoresist layer 48 of e.g. AZ1350J pro-
`another by buried insulating layers each of which sur-
`rounds each of the FET-s.
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`duced and marketed by Shipley Company Inc. of the
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`U.S.A. and the top surface of the photoresist layer 48
`Thefirst embodiment is a method for production of a
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`becomesflat.
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`semiconductor device having a plurality of FET’s, each
`of whichis fabricated in an element fabrication area of
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`Referring to FIG. 4(c), a dry etching process is ap-
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`plied to the substrate until the top surface of the poly-
`a silicon (Si) substrate surroundedby a buried insulating
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`crystalline silicon (Si) layer 43 is exposed. An argon
`layer, wherein an improvementis realized in which a
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`(An) gas at a pressure of 7x 10-4 Torr.is employed and
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`thermal strain absorbing layer of polycrystalline silicon
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`an etching rate of 500 A/min.
`is realized. Although
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`(Si) is interleaved between the substrate and the insulat-
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`damage may occur in the polycrystalline silicon (Si)
`ing layer such that the polycrystallinesilicon (Si) layer
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`layer 43, during this process, the entire silicon (Si) sub-
`absorbs potential strains and damage which may other-
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`strate 41 is protected from damage. This means that
`wise occur in the silicon (Si) substrate. This embodi-
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`potential damages which might be otherwise be pro-
`ment will be presented, referring to FIGS. 4(a), 4(d),
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`duced along the edges of the element fabrication area 46
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`4(c), 4(d) and 4(e).
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`of the silicon (Si) substrate 41 surrounded by the buried
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`Referring to FIG. 4(a), the top surface ofa silicon (Si)
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`insulating layer 47, are absorbed by the polycrystalline
`substrate 41 is oxidized to produce a silicon dioxide
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`silicon (Si) layer 43.
`(SiO2) layer 42 having a thickness of 500 A, before a
`60
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`Referring to FIG. 4(d), a dry etching process is ap-
`polycrystalline silicon (Si) layer 43 having a thickness of
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`plied to the substrate to remove only the upper portion
`1,000 A is grown onthesilicon dioxide (SiO) layer 42.
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`of the silicon dioxide (SiOz) layer 47 by a depth corre-
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`The function of the silicon dioxide (SiO2) layer 42 is to
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`sponding to the thickness of the polycrystalline silicon
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`make it easy to remove the polycrystalline silicon (Si)
`(Si) layer 43. A trifluoromethane (CHF3)gas at a pres-
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`layer 43 in a later step. In other words, it functions to
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`sure of 0.05 Torr. is employed and an etching rate of 800
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`solve the difficulty in removing the polycrystalline
`A/min.is realized.
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`silicon (Si) layer 43 whenit is produced directly on the
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`Referring to FIG. 4(e), a plasma etching process em-
`silicon (Si) substrate 41, which is, of course, a material
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`ploying a carbon fluoride (CF4) gas containing 5% of
`identical to the layer. The function of the polycrystal-
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`45
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`65
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`Page 11 of 15
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`Page 11 of 15
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`4,506,434
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`simultaneously pattern the gate electrodes and metal
`oxygen (O2) at a pressure of 1 (one) Torr. is applied to
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`wirings employing a single mask.
`the substrate to remove the polycrystalline silicon (Si)
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`layer 43 at an etching rate of 500 A/min. Thereafter, a
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`Referring to FIG. 5(c), a series of ordinary steps
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`available in the prior art are employed for production of
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`hydrogen fluoride (HF) solution is brought into contact
`with the surface of the substrate to removethesilicon
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`sources and drains 58, an inter-layer insulating layer 59
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`and an upperlayer wiring 60 for the ultimate purpose of
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`dioxide (SiO) layer 42 and the top portionofthe silicon
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`producing a MOS IC. Theright portion of FIG. 5(c)
`dioxide (SiOz) layer 47, thereby exposing the top sur-
`showsa cross-sectional view of a MOStransistor, the
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`face ofthesilicon (Si) substrate 41. As a result, a portion
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`cross-sectional view showing a cross-section which is
`of the silicon dioxide (SiOz) layer 47 remains buried
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`parallel to the direction in which the gate electrode
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`surrounding the element fabrication area 46 of the sili-
`extends. In other words,
`the source and drain (not
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`con (Si) substrate 41 and the buried silicon dioxide
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`shown) of the MOStransistor are located in the direc-
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`(SiO2) layer 47 functions as an isolation region.
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`tion perpendicular to the page.
`The foregoing description has described a method for
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`The foregoing description has described a method for
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`production of a semiconductor device having a plural-
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`production of a semiconductor device in accordance
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`ity of FET’s, each of which is fabricated in an element
`with the first embodiment which is expanded to a sec-
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`fabrication area of a silicon (Si) substrate surrounded by
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`ond embodiment, wherein the polycrystalline silicon
`a buried insulating layer which functionsas anisolation,
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`(Si) layer, which in the first embodiment functioned to
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`wherein improvements are realized which prevent
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`absorb thermal strains, is further employed for the pro-
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`strains from occurring at the corners of the element
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`duction of gate electrodes and/or some of the metal
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`fabrication area of the silicon (Si) substrate surrounded
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`wirings. As a result,
`in accordance with the present
`by the buried insulating layer and which prevent dam-
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`second embodiment, it is possible to simplify the pro-
`age on the surface of the element fabrication area of the
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`duction steps of a method for production of a semicon-
`silicon (Si) substrate surrounded by the buried insulat-
`ductor device.
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`ing layer when a high temperature process, which is
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`FIG.6 showsa cross-se