0
`
`United States Patent [19]
`Schuegraf et al.
`
`[54] SHALLOW TRENCH ISOLATION USING
`LOW DIELECTRIC CONSTANT INSULATOR
`
`[75] Inventors: Klaus F. Schuegmf; Aftab Ahmad,
`both of Boise, Id.
`
`['73] Assignee: Micron Technology, Inc., Boise. Id.
`
`[21] Appl. No.: 547,620
`[22] Filed:
`Oct. 24, 1995
`[51] Int. Cl.“
`[52] us. Cl.
`
`[58] Field of Search
`
`H01L 21/76
`437/67; 437/240; 437/238;
`143/])}(}_ 50
`437/64, 65, 67,
`437/233, 240; 148;DIG_ 50
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`US005702976A
`[11] Patent , Number:
`[45] Date of Patent:
`
`5,702,976
`Dec. 30, 1997
`
`437/67
`4/1989 Goth
`4,824,797
`.. 437/238
`5,429,995 7/1995 Nishiyama et al. .
`427/579
`5,492,736 7Jl996 laxman et a1. ..
`5,530,293
`6/1996 Cohen et a]. ......................... .. 257/752
`
`P?mary Examiner-“"118 Dang
`Attorney, Agent or Firm—Kn0bbe, Martens, Olson & Bear.
`LLP
`ABSTRACT
`[57]
`A shallow trench isolation is disclosed wherein the trench
`depth is reduced beyond that achieved in PH'OI an Processes
`The reduced Wench depth helps to eliminate the formation of
`voids during ?w mwh re?ll Process and provides for
`greater planarity in the ?nal isolation structure. Effective
`device isolation is achieved with a reduced trench depth by
`utilizing re?lling dielectric maten'als having low dielectric
`constant.
`
`4,5(2914 3/1985 Trumpp et a1.
`
`437/67
`
`22 Claims, 4 Drawing Sheets
`
`Global Foundaries US v. Godo Kaisha
`Global Ex. 1009
`
`Page 1 of 9
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`US. Patent
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`Dec. 30, 1997
`Dec. 30, 1997
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`Sheet 4 of 4
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`5,702,976
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`1
`SHALLOW TRENCH ISOLATION USING
`LOW DIELECTRIC CONSTANT INSULATOR
`
`FIELD OF THE lNVENTION
`The invention relates generally to silicon integrated cir
`cuit design and process technology. In particular, the inven
`tion pertains to trench isolation process technology.
`
`2
`wall pro?le as compared to LOCOS oxidation. The trenches
`are subsequently re?lled with a dielectric such as chemical
`vapor deposited (CVD) silicon dioxide (SiO2). They are then
`planatized by an etchback process so that the dielectric
`remains only in the trench, its top surface level with that of
`the silicon substrate. The etchback process is often per
`formed by etching photoresist and the deposited silicon
`dioxide at the same rate. The top surface of the resist layer
`is highly planarized prior to etchback through application of
`two layers of resist, and ?owing the ?rst of these layers.
`Active regions wherein devices are fabricated are those that
`were protected from etch when the trenches wm'e created.
`The resulting structure functions as a device isolator having
`excellent planarity and potentially high aspect ratio bene?
`cial for device isolation. Re?lled trench isolation can take a
`variety of forms depending upon the speci?c application;
`they are generally categorized in terms of the trench dimen
`sions: shallow trenches (<1 pm), moderate depth trenches
`(1-3 pm), and deep, narrow trenches (>3 um deep, Q inn
`wide). Shallow Trench Isolation (STI) is used primarily for
`isolating devices of the same type and is often considered an
`alternative to LOCOS isolation. Shallow trench isolation has
`the advantages of eliminating the birds beak of LOCOS and
`providing a high degree of swine planarity.
`The basic trench isolation process is, however, subject to
`drawbacks, one of these being void formation in the trench
`during dielectric re?ll. Such voids are formed when the
`re?lling dielectric material forms a constriction near the top
`of a trench, preventing ?ow of the material into the trench
`interior. Such voids compromise device isolation as well as
`the overall structural integrity. Unfortunately, preventing
`void formation during trench re?ll often places minimum
`size constraints on the trenches themselves, which may
`compromise device packing density or device isolation. For
`example, a key parameter measuring device isolation is the
`?eld threshold voltage between adjacent devices, that is. the
`voltage necessary to create a parasitic channel beneath a
`?eld oxide region linking adjacent devices. The ?eld thresh
`old voltage is in?uenced by a number of physical and
`matm'ial properties of the trench isolator such as insulator
`thickness, dielectric constant c, substrate doping, ?eld
`implant dose and substrate bias. Thus, a principal di?iculty
`in decreasing the trench depth is the compromise in device
`isolation. Clearly, it is highly desirably to develop a shallow
`trench isolation process which overcomes the problem of
`void formation while providing effective device isolation.
`SUMMARY OF THE INVENTION
`It is an object of the present invention to provide a trench
`isolation process which alleviates the problem of void
`formation during dielectric re?ll. It is another object of the
`present invention to provide a trench isolator having reduced
`dimensions, advantageous for device density and wafer
`planarity. It is a further object of the present invention to
`provide a shallow trench isolator having enhanced device
`isolation characteristics.
`In accordance with one aspect of the present invention. a
`process for isolating devices on a semiconductor substrate
`comprises ?rst removing portions of the semiconductor
`substrate, thereby forming recesses preferably having a
`trench pro?le. The trenches are then re?lled with a material
`having a dielectric constant lower than the dielectric con
`stant of silicon dioxide which is about 3.9. Using a low
`edielectric material allows the trench dimensions to be
`reduced while still providing elfective device isolation char
`acteristics. Preferably, the dielectric material comprises a
`halide-doped glass such as Fluorine-doped SiO2. To insure
`
`BACKGROUND OF THE INVENTION
`Implementing electronic circuits involves connecting iso
`lated devices through speci?c electronic paths. In silicon
`integrated circuit fabrication it is necessary to isolate devices
`from one another which are built into the same silicon
`matrix. They are subsequently interconnected to create the
`desired circuit con?guration. In the continuing trend toward
`higher device densities, parasitic interdevice currents
`become more problematic, thus isolation technology has
`become one of the most critical aspects of contemporary
`integrated circuit fabrication.
`Over the last few decades a variety of successful isolation
`technologies have been developed to address the require
`ments of different integrated circuit types such as NMOS,
`CMOS and bipolar. In general, the various isolation tech
`nologies exhibit dilferent attributes with respect to such
`characteristics as minimum isolation spacing, surface
`planarity, process complexity and defect density generated
`during isolation processing. Moreover, it is common to trade
`off some of these characteristics when developing an isola
`tion process for a particular integrated circuit application.
`In metal-oxide-semiconductor (MOS) technology it is
`necessary to provide an isolation structure that prevents
`parasitic channel formation between adjacent devices, such
`devices being primarily NMOS or PMOS transistors or
`CMOS circuits. The most widely used isolation technology
`for MOS circuits has been that of LOCOS isolation, an
`acronym for LOCal Oxidation of Silicon. LOCOS isolation
`essentially involves the growth of a recessed or semire
`cessed oxide in unmasked non-active or ?eld regions of the
`silicon substrate. This so-called ?eld oxide is generally
`grown thick enough to lower any parasitic capacitance
`occurring over these regions, but not so thick as to cause step
`coverage problems. The great success of LOCOS isolation
`technology is to a large extent attributed to its inherent
`simplicity in MOS process integration, cost e?’ectiveness
`and adaptability.
`In spite of its success, several limitations of LOCOS
`technology have driven the development of alternative iso
`lation structures. A well-known limitation in LOCOS isola
`tion is that of oxide undergrowth at the edge of the mask
`which de?nes the active regions of the substrate. This
`so-called bird’s beak (as it appears) poses a limitation to
`device density, since that portion of the oxide adversely
`in?uences device performance while not significantly con
`tributing to device isolation. Another problem associated
`with the LOCOS process is the resulting circuit planarity or
`lack thereof. For submicron devices, planarity becomes an
`important issue, often posing problems with subsequent
`layer conforrnality and photolithography.
`Trench isolation technology has been developed in part to
`overcome the aforementioned limitations of LOCOS isola
`tion for submicron devices. Re?lled trench structures essen
`tially comprise a recess formed in the silicon substrate which
`is re?lled with a dielectric material. Such structures are
`fabricated by ?rst forming submicron-sized trenches in the
`silicon substrate, usually by a dry anisotropic etching pro
`cess. The resulting trenches typically display a steep side
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`3
`against device contamination, the invention further com
`prises forrning a barrier Layer over the trenches prior to
`re?lling them with the low-edielectric material.
`In accordance with another aspect of the present
`invention, an isolation structure in a semiconductor substrate
`comprises a recessed trench formed in the semiconductor
`substrate and a material having a low dielectric constant
`?lling the trench. The trench structure preferably has a depth
`less than 250 nm, and furthermore comprises a barrier layer
`disposed between the interior trench surface and the dielec
`nic material. The dielectric material preferably has a dielec
`tric constant lower than about 3.9, and may comprise a
`Fluoride-doped silicon dioxide composition.
`In accordance with yet another aspect of the present
`invention, a method of reducing the formation of voids in a
`re?lled trench isolation process comprises forming trenches
`having an aspect ratio less than about 2:1, and then re?lling
`the trenches with a material having a dielectric constant less
`than the dielectric constant of silicon dioxide. The trenches
`preferably have a depth of less than 200 nm, and are re?lled
`with a material comprising a Fluorine-doped silicon dioxide
`composition.
`These and other aspect and attributes of the present
`invention will become more fully apparent with the follow
`ing detailed description and accompanying ?gures.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIGS. lA-lC are schematic sections illustrating an exem
`plary shallow trench isolation process.
`FIG. 2 is a schematic section of a trench re?ll having a
`void.
`FIG. 3 is a schematic section illustrating an embodiment
`of the present shallow trench isolation process.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`In accordance with the principles of the present invention,
`an improved shallow trench isolation technology utilizes a
`trench that is shallower than prior art trenches, and yet
`provides the same degree of device isolation. The shallower
`trench helps prevent the formation of voids dining dielectric
`re?ll. However, despite the smaller dimensions of the
`present inventive trench, equivalent device isolation is
`achieved through use of a dielectric re?ll having a lower
`dielectric constant e than in prior an isolation trenches. To
`better illustrate these inventive principles, a brief description
`of an exemplary STI process is provided ?rst hereinbelow.
`An exemplary STI process may comprise ?rst a masking,
`patterning and dry etch process, producing trenches in the
`silicon substrate as shown in FIG. 1A. The semiconductor
`substrate 10 is masked and patterned to expose the regions
`of the substrate to be etched. The mask 12 may for example
`comprise a resist layer which is resistant to the dry aniso
`tropic etch used to create the trenches. The mask 12 may be
`patterned by conventional photolithographic means to de?ne
`the regions of the substrate 10 to have trenches formed
`therein. The trenches 14 are formed by an anisotropic dry
`etch, such as a plasma or reactive ion etch. A preferred
`characteristic of the trenches 14 is the steep sidewall pro?le
`as compared to conventional LOCOS processes.
`After the trenches 14 are formed, the mask 12 is removed
`by selective etching or chemical mechanical polishing and
`the trenches are re?lled with a dielectric material 16, as
`shown in FIG. 1B. A preferred dielectric re?ll material for
`SP1 is chemical vapor deposited silicon dioxide (CV D-SiOZ)
`due to its high quality and excellent conformality. Confor
`mality is particularly important because the re?lled material
`must be supplied to ?ll trenches having relatively high
`aspect ratios (height:width>1).
`
`4
`Following the trench re?ll 16, the top surface of the
`substrate 10 is planarized by an etchback process, typically
`also performed using a chemical/mechanical polish. Prior to
`etchback. the substrate 10 may be coated with a layer of
`photoresist (not shown) in order to provide a planar surface
`with which to begin the etchback. The etchback itself
`provides a planarized substrate surface 18. having dielectric
`material 16 ?lling the trenches 14 up to and level with the
`top surface 18.
`As shown in FIG. 2, a common problem associated with
`trench re?ll isolation is the formation of voids in the
`trenches. During re?ll of the trench 14 with dielectric
`material 16, the trench l4 often becomes constricted near the
`top of the trench, thereby preventing complete re?ll of the
`trench, resulting in a void 20. The void 20 lowers the
`isolation characteristics of the re?lled trench in addition to
`introducing structural instabilities in subsequent processes.
`Increasing the trench width can alleviate void formation,
`however it also undesirably decreases device density.
`In accordance with the principles of the present invention,
`void formation is alleviated by dea'easing trench depth.
`Utilizing shallower trenches decreases the possibility of void
`formation and favorably increases surface planarity of the
`?nal re?lled trench structure. For example in a typical
`DRAM application, a trench in accordance with the present
`invention may have dimension of approximately 200 nm
`deep and 250 nm wide while prior art trenches typically have
`dimensions of approximately 275 nm deep and 350 nm
`wide. However, as is well known in the art, a key parameter
`measuring device isolation is the ?eld threshold voltage
`between adjacent devices, that is, the voltage necessary to
`create a parasitic channel beneath a ?eld oxide region
`linlcing adjacent devices. The ?eld threshold voltage is
`in?uenced by a number of physical and material properties
`of the trench isolator such as insulator thickness, dielectric
`constant e, substrate doping, ?eld implant dose and substrate
`bias. Thus, a principal difficulty in decreasing the trench
`depth is the compromise in device isolation.
`To circumvent this problem, the shallow trench isolation
`of the present invention maintains e?’ective device isolation
`in a shallower trench by utilizing dielectric materials having
`a lower dielectric constant than used in the prior art. For a
`given trench geometry, the ?eld threshold voltage is a
`decreasing function of the ?eld dielectric constant. ‘Thus, to
`compensate for smaller trench dimensions, the present
`invention utilizes dielectric materials having lower dielectric
`constant. A possible dielectric material is a low index glass
`such as a halide-doped silicon dioxide, deposited by intro
`ducing the halide during CVD of silicon dioxide. For
`example, F:Si02 possesses a dielectric constant of approxi
`mately 3.2, while typical CVlIt-SiO2 has a dielectric constant
`of about 3.9. Use of such materials allows arelative decrease
`in trench depth by about 20%.
`Fluorine or other elements comprising a reduced dielec
`tric constant material may however cause deleterious effects
`on neighboring devices if they di?’use into adjacent active
`areas. Therefore, a preferred embodiment of the present
`invention also incorporates a diifusion barrier layer lining
`the trench so as to prevent dopant migration into the silicon
`substrate. Use of a preferred barrier layer in the form of a
`grown oxide or nitride ?lm. or a deposited stoichiometric or
`non-stoichiometric oxide or nitride ?lm inhibits contamina
`tion of the isolation ?eld-e?’ect transistor, thereby preserving
`desirable characteristics such as a high threshold voltage.
`The integrated devices subject to isolation are also protected
`by the barrier layer from contamination.
`In accordance with the aforementioned principles, a pre
`ferred shallow trench isolation may for example comprise
`the following process steps illustrated in FIGS. 3A-3D. As
`shown in FIG. 3A, the silicon wafer 10 is ?rst owned by a
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`mask 12. such as a resist or silicon oxide/nitride bilayer, and
`then patterned and etched to de?ne the ?eld isolation
`regions. The wafer is then subject to a dry anisotropic etch
`such as a halide plasma complex, thereby forming the
`trenches 22 in the silicon substrate 10. As mentioned earlier,
`in comparison to the prior art trench isolation, the trenches
`of the present invention are about 200 nm deep, shallower
`than the prior art by about 20%.
`As mentioned previously, to avoid contamination of sub
`strate regions adjacent to the trenches 22, it is preferable to
`form a barrier layer 24 over the trenches 22 prior to
`dielectric re?ll as shown schematically in FIG. 3B. The
`barrier layer 24 may for example comprise a silicon oxide or
`nitride ?hn grown in an appropriate ambient or a chemical
`vapor deposited oxide or nitride ?lm at least 5 nm thick. The
`barrier layer 24 functions to prevent di?’usion of dopants
`deposited during the subsequent dielectric re?ll process.
`Although in general nitride forms a superior di?‘usion barrier
`to oxide, the higher dielectric constant of nitride should be
`considered in the overall isolation structure. It may be for
`example. that oxide performs adequately as a ditfusion
`barrier while having the advantage of a lower dielectric
`constant than nitride. Thus, barrier layer thickness and
`dielectric constant should be considered in the overall trench
`design.
`A shown in FIG. 3C, the trenches 22 are re?lled with a
`dielectric material 26 having a low dielectric constant e of
`about 3.3. As mentioned previously, the use of a low
`dielectric constant material lowers the gate capacitance of
`the isolation ?eld-e?‘ect transistor, thereby raising the
`threshold voltage. A CV D-SiO2 doped with a halide such as
`Fluorine is a presently preferred material.
`To complete the trench structure, a planarizing step is
`performed as shown in FIG. 3D. A planatizing process may
`for example comprise depositing and re?owing a resist layer
`to attain a planar top surface, followed by an etchback
`procedure to remove material down to the substrate surface.
`While the planarizing process may proceed in accordance
`with well-known processes, the present preferred isolation is
`advantageous because the shallower trench structures and
`consequent thinner re?lled layers allow for a greater degree
`of planarity.
`Thus. the present invention provides several advantages
`over the prior art by avoiding cavities in the trenches,
`providing more effective device isolation using low-e mate
`rials and having a greater degree of planarity in the ?nal
`trench strudure.
`Although described above with reference to the preferred
`embodiments, modi?cationswithin the scope of the inven
`tion may be apparent to those skilled in the art, all such
`modi?cations are intended to be within the scope of the
`appended claims.
`What is claimed is:
`l. A process for isolating devices on a semiconductor
`substrate comprising the steps of:
`removing predetermined portions of the semiconductor
`substrate forming recesses therein; and
`re?lling the portions of the semiconductor substrate with
`a material comprising an in situ doped silicon oxide
`complex, the material having a dielectric constant
`lower than the dielectric constant of undoped silicon
`dioxide.
`2. The process of claim 1, wherein the step of removing
`portions of the semiconductor wafer comprises forming
`trenches in the semiconductor wafer.
`3. The process of claim 2, wherein the trenches have a
`depth of less than 200 nm.
`
`45
`
`6
`4. The process of claim 3, wherein the trenches have an
`aspect ratio of less than 2:1.
`5. A process for isolating devices on a semiconductor
`substrate comprising the steps of:
`removing predetermined portions of the semiconductor
`substrate forming recesses therein; and
`re?lling the portions of the semiconductor substrate with
`a material having a dielectric constant lower than the
`dielectric constant of silicon dioxide,
`wherein the material having a dielectric constant lower than
`that of silicon dioxide comprises a halide-doped silicon
`dioxide composition.
`6. The process of claim 5, wherein the halide-doped
`silicon dioxide complex comprises a Fluorine-doped silicon
`dioxide complex.
`7. The process of claim 1, wherein the re?lling material
`has a dielectric constant less than about 3.9.
`8. The process of claim 1. further comprising forming a
`barrier layer over the semiconductor substrate prior to the
`step of re?lling portions of the semiconduaor substrate.
`9. The process of claim 8, wherein the barrie- layer
`comprises a silicon dioxide composition.
`10. The process of claim 8. wherein the barrier layer
`comprises a silicon nitride composition.
`11. A method of reducing the formation of voids in a
`re?lled trench isolation process comprising the steps of:
`forming trenches having an aspect ratio less than 2:1;
`re?lling the trenches with an insulating material; and
`halide-doping the material.
`12. The method of claim 11, wherein the trenches have a
`depth of less than 200 nm.
`13. A method of reducing the formation of voids in a
`re?lled trench isolation process comprising the steps of:
`forming trenches having an aspect ratio less than 2:1; and
`re?lling the trenches with a mata'ial having a dielectric
`constant less than the dielectric constant of silicon
`dioxide,
`wherein the re?lling material comprises a Fluorine-doped
`silicon dioxide composition.
`14. The method of claim 11, wherein the halide-doped
`material has a dielectric constant of less than about 3.9.
`15. The method of claim 1, wherein the material com
`prises a halide-doped oxide.
`16. The method of claim 1, wherein the material com
`prises a ?uoride-doped oxide.
`17. The method of claim 11, wherein re?lling ?re trenches
`comprises depositing silicon dioxide.
`18. The method of claim 17. wherein depositing silicon
`dioxide comprises a chemical vapor deposition.
`19. The method of claim 18, wherein halide-doping the
`matm'ial comprises in situ halide doping during chemical
`vapor deposition of the material.
`20. The method of claim 11, wherein doping the material
`comprises introducing a halide into the material while
`re?lling the trenches.
`21. The method of claim 11. wherein the halide comprises
`?uorine.
`22. A process for isolating devices on a semiconductor
`substrate comprising the steps of:
`forming trenches within the substrate;
`lining the trenches with a dilfusion barrier;
`re?lling the trenches with silicon dioxide; and
`halide-doping silicon dioxide.
`
`* * * * It‘
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`

`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`PATENTNO. : 5’702’976
`
`DATED
`
`; December 30, 1997
`
`'NVENT°"<S) = Klaus Schuegraf, A?ab Ahmad
`
`It is certified that error appears in the above-indenti?ed patent and that said Letters Patent is hereby
`corrected as shown below:
`
`On the title page item [57], In the Abstract,line3, delete “womb” and insert --trench--.
`
`Signed and Sealed this
`Twenty-third Day of June, 1998
`6%! W
`
`Attest:
`
`AIIESH-Hg O?CEi'
`
`Commissioner of Parents and Trademarks
`
`BRUCE LEHMAN
`
`Page 9 of 9
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