Philips tech. Rev. 34, 19-23, 1974, No.1
`
`19
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`LOCMOS,a new technology
`for complementary MOScircuits
`
`B.B.M.Brandt, W. Steinmaier and A.J. Strachan
`
`
`
`Although the good characteristics of complementary MOStransistors have been known
`for some time, they have been very little used in LSI (large-scale integration) circuits
`because of the complicatedprocesses and the low packing density. Now that the LOCOS
`technique is available CMOStransistors can be used io produce LSI circuits with high
`packing density and good electrical characteristics.
`
`1
`
`q
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`Io
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`Fig. 1. a) An inverter circuit (schematic) consisting of an MOS
`transistor with a P-type channel (above) and another with an
`N-type channel (below). The two gates are connected together,
`as are the two drains (‘complementary’ MOStransistors, CMOS
`for short). With a positive supply voltage Vaa and an input volt-
`age Vj (logic state ‘l’) the -channeltransistor conducts and the
`P-channeltransistor does not. The output voltage Vo is now zero
`(logic state ‘0’). If Vi =O (state ‘0°)
`the situation is reversed
`and the output voltage equals Vaa (‘1’). The two transistors
`function as switches and in both states the only current in the ~
`circuit is the leakage current of one transistor.
`6) Schematic circuit of an inverter circuit consisting of two P-
`channel MOStransistors, with the drain of one connected to the
`source of the other. With a negative supply voltage — Vaa and a
`negative input voltage —V; (‘1’) both transistors conduct. The
`output voltage is then determined by the ratio of the channel
`resistances of the two transistors. If the channel resistance of the
`lowertransistor, the ‘switching transistor’, is much smaller than
`that of the upper one, the ‘load transistor’, the output voltage is
`also very small (‘0’). A current determined by the value of the
`channel resistances now flows in the circuit. If Vi = 0 (state
`‘0’),
`the switching transistor does not conduct and the load
`transistor does. The output voltage is then equal to —Vaa + Vin
`(‘1’), where Viz is the threshold voltage of the load transistor.
`Only the leakage current of the switching transistor now flows
`in the circuit.
`
`, ©
`
`] MOStransistors and circuits have been discussed in detail in
`Philips tech. Rev. 31, No. 7/8/9, 1970 (the MOST issue).
`(2) Jn static logic the information content of a logic circuit is
`held for an unlimited time, while in dynamiclogicit is lost
`in a relatively short
`time. See also L. M. van der Steen,
`Digital integrated circuits with MOStransistors, Philips tech.
`Rev. 31, 277-285, 1970. The differences between static and
`dynamic shift registers are discussed in this article.
`(31 A more detailed treatmentofthis circuit is given in the article
`mentioned in note [2].
`
`A type of MOS-transistor circuit arrangement that
`has now been known for several years is the ‘comple-
`mentary MOSTcircuit’? (CMOS). The circuit has been
`given this name because it contains both N- and P-
`channel MOStransistors. Suchcircuits can have signif-
`icant advantages over conventional MOScircuits 2.
`The most important advantageis the low currentlevel
`in logic circuits, giving a low dissipation. This enables
`static logic to be produced that would encounter con-
`siderable problemsofheat dissipation if made entirely
`with N-channel or P-channel MOStransistors |].
`Weshall explain this with the example of an inverter
`circuit. Fig. Ja shows such a circuit, made from CMOS
`transistors. With a positive supply voltage Vaa, if a
`positive voltage Vi is applied to the input(logic state
`‘1’), then the V-channel transistor becomes conducting
`while the P-channel transistor does not conduct. The
`output voltageis then zero (logic state ‘0’). If the voltage
`is now removedfrom the input (‘0’), the P-channel tran-
`sistor becomes conducting and the N-channel transistor
`is switched off. The output voltage is now Vaa (‘1’).
`The two MOStransistors therefore behave as switches,
`and the currentin the circuit is determined by the very
`small leakage current of the switched-off MOStransis-
`tor. The current has a larger value only temporarily,
`during the switching, when there is some dissipation.
`By way of comparison fig. 15 shows an invertercir-
`cuit made up from P-channeltransistors !], The supply
`voltage here is —Vaq. If no voltage is applied to the
`input (‘0’) the lower MOStransistor, the ‘switching
`transistor’, does not conduct but the upper one, the
`‘load transistor’ does. The output voltage is then equal
`to the difference: between the supply voltage and
`the threshold “voltage Vin of the load transistor:
`—Vaa + Vin (‘1’). When a negative input voltage is
`
`Ir B. B. M. Brandt, Dr W. Steinmaier and Dr A. J. Strachan are
`with the Philips Electronic Components and Materials Division
`(Elcoma), at Nijmegen.
`
`Page 1 of 5
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`Global Foundaries US v. Godo Kaisha
`Global Ex. 1008
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`Page 1 of 5
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`applied the switching transistor conducts. The output
`voltage is now determined by the ratio of the channel
`resistances of the lower and uppertransistors. If this
`ratio has a small value, the output voltage is also small
`(‘0’). But in this state there is a difference from the
`CMOScircuit: a current mainly determined by the
`channel resistance of the load transistor now flows
`through the transistors, so that there is dissipation.
`While this current can indeed be made small by making
`the resistance of the channelhigh, this can only be done
`at the expense of switching speed. The advantage of a
`CMOScircuit is that the channel resistance values can
`be small, and hence the switching speeds high.
`Other advantages of CMOScircuits compared with
`ordinary MOScircuits are the immunityto fluctuations
`in the supply voltage or in the input voltage. Thesensi-
`tivity to input-voltage fluctuations is low because the
`input voltage at which the circuit changes over from
`one logic state to the other is equal to abouthalf the
`supply voltage, while the actual transition takes place
`over a very small range of input voltage. It is also easy
`to make a CMOScircuit compatible with other logic
`circuits such as DTL (diode-transistor logic) and TTL
`(transistor-transistor logic).
`All these advantages would make CMOStransistors
`very suitable for use in integrated circuits, were it not
`for the fact that with the same tolerances the packing
`density is smaller than for ordinary MOStransistors.
`This means that the CMOStechnique will give only a
`low yield when applied in large-scale integration (LSI
`circuits). Extra process steps are also required for a
`CMOScircuit, which has an adverse effect on the
`yield.
`It has now been found that marked reduction in sur-
`face area can be obtained by using the LOCOStech-
`nique [4] developed at Philips Research Laboratories,
`combined with a
`special
`technique for applying
`P-type regions. This processis controlled in such a way
`that LSI circuits can be made.
`In the LOCOStechniquea silicon substrate is coated
`with a layerof silicon nitride, which is used as a mask
`in a later oxidation of the silicon when a silicon-dioxide
`layer is formed at the places where the nitride has been
`removed. Most of this ‘LOCOS’ oxide sinks into the
`silicon and gives good separation between regions of
`different doping. It takes up far less space than the
`conventionalisolation diffusion. The dimensions of a
`circuit can be made even smaller since contact window
`and metallization masking do not have to be kept a
`certain minimum distance from theisolation diffusion,
`but can extend right up to the LOCOSoxide. In addi-
`tion, narrow uninterrupted metallized tracks can now
`be applied, since there are no large steps on the surface
`due to oxide layers. Another advantage of the LOCOS
`
`techniqueis the low capacitance between the metalliza-
`tion andthesilicon at the thick oxide layer; this enables
`fast switching speeds to be obtained.
`Weshall now describe the process used for making
`CMOScircuits by the LOCOStechnique — wecall the
`process the ‘LOCMOStechnique’ — with the aid of
`jig. 2. The starting material is a wafer of N-type silicon
`whose surface has the (100) orientation. A surface
`with this orientation generally has very few surface
`states, and little charge appears in the oxide grown
`upon it; this gives a low and reproducible threshold
`voltage. The wafer is coated with a thin layerof silicon
`nitride, which is next removed at the places where the
`isolation oxide is to be formed, and thesilicon is then
`oxidized until the oxide layer is 1.8 wm thick (fig. 2a).
`The next step is to remove the nitride at the places
`where the P-islands for the N-channel transistors have
`to appear; this is done by standard photo-etching tech-
`niques. After this P-type regions are produced at these
`places by a special technique(fig. 2b). In this technique
`the silicon is doped with boron in such a waythat the
`boron concentration at the surface has the value neces-
`sary for good operation of the MOStransistor, while
`the maximum of the concentration profile is located
`about 1.5 um beneath the surface. This approach pre-
`vents parasitic N-type channels from forming along the
`LOCOS oxide. With this method there is no need to
`use ‘channel stoppers’ — these are strongly doped
`regions included to counteract the formation of para-
`sitic channels, and they take up a lot of space. After
`the P-diffusion the rest of the nitride is removed, and
`a thin oxide layer is formed thermally. A polycrystal-
`line layer of silicon is then applied. Next the poly-
`crystalline layer is doped with phosphorus to makeit
`an N-type conductor, and a pattern is etched in it for
`the electrodes and a part of the interconnection pattern
`(fig. 2c); the doping is necessary to give a low series
`resistance of the conductors and hence a high switching
`speed. This treatmentalso gives a stable threshold volt-
`age, since the phosphorous oxide produced binds so-
`dium atomsandthusprotects the silicon dioxide from
`atomsthat are knownto introduce mobile charge in the
`oxide. The next step in the process is to produce P-type
`sources and drains by boron diffusion at previously
`etched openings in the oxide layer (fig. 2d). The gates
`
`4] ‘LOCOS’is an acronym from Local Oxidation of Silicon. A
`description is given in:
`J. A. Appels, H. Kalter and E. Kooi, Some problems of
`MOStechnology, Philips tech. Rev. 31, 225-236, 1970;
`J. A. Appels and M. M. Paffen, Local oxidation ofsilicon,
`new technological aspects, Philips Res. Repts. 26, 157-165,
`1971;
`E. Kooi, J. G. van Lierop, W. H. C. G. Verkuijlen and R. de
`Werdt, LOCOS devices, Philips Res. Repts. 26, 166-180,
`1971.
`See also Philips tech. Rev. 31, 276, 1970.
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`Fig. 2. The steps in the LOCMOStechnique. a) The application
`of the LOCOS oxide. The N-type silicon is coated withsilicon
`nitride in which openings are etched. The LOCOS oxide forms
`here as a result of an oxidation treatment. b) P-type regions for
`the N-channel transistors are made by diffusing boron through
`windowsin the silicon-nitride layer. c) After removing the nitride,
`and forming a thin oxide layer on thesilicon surface, a layer of
`polycrystalline silicon is applied. A pattern for the gates andtheir
`interconnections is etched in this layer. d) The sources anddrains
`(P*) for the P-channeltransistors (right) are nowformed by boron
`diffusion in the N-type regions, with the gates and the LOCOS
`oxide serving as a mask. e) The sources and drains (N*) for the
`N-channel transistors (right) are now formed in a similar way
`by phosphorus diffusion in the P-type regions. f) An SiOz layer
`is next deposited pyrolitically, and openings are etched in the
`SiOz at the places where contact with the electrodes is required.
`g) An aluminium layer is then deposited by evaporation and the
`interconnection pattern for the circuit is etched in it.
`
`
`
`BAUOGBEU
`
`oxide
`nitride
`polycrystalline Si
`P-Si
`P*-Si
`N-Si
`N?t-Si
`Al
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`
`
`
`
` |
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`|
`
`g |
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`Page 3 of 5
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`and the LOCOSoxide serve as masks. Since these elec-
`trodes are small the stray capacitances are small, which
`also helps to give a high switching speed. After the
`boron diffusion a thin oxide is again formed on these
`regions. The N-type sources and drains are next pro-
`duced in a similar treatment, with a phosphorus dif-
`fusion (fig. 2e). A silicon-dioxide layer is then deposited
`pyrolitically, and openings are etched in this to allow
`contact between the electrodes and the interconnection
`pattern (fig. 2/). Finally, a layer of aluminium is ap-
`plied by vacuum evaporation and the interconnection
`pattern is formed in this by etching(fig. 2g).
`The great
`saving in
`space obtained with the
`LOCMOStechnique is demonstrated in fig. 3, which
`shows an inverter circuit made with this technique com-
`pared with the samecircuit made with the conventional
`technique.
`The LOCMOSprocess described here has been suc-
`cessfully applied in the manufacture of a number of
`integrated circuits. These includean inverter circuit, an
`8-bit shift register and a static 256-bit random-access
`memory.
`The invertercircuit has a delay time of 3 to 5 ns with
`a supply voltage of 5 V and anidentical inverter circuit
`as
`load. Under similar conditions a conventional
`CMOScircuit has a delay time of at least 12 ns.
`The 8-bit shift register has one series input and eight
`parallel outputs, which are all capable of driving one
`TTL input. This circuit operates up to a frequency of
`10 MHz at a supply voltage of 5 V. The area occupied
`by this circuit
`is 2.5 mm?; a conventional CMOS
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`LZ a(iL//)— rr
`_— Laan
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`ZZ
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`Fig. 3. Comparison of the dimensions of an inverter circuit made by the conventional pro-
`cess (a) and by the LOCMOS process (b). The structure is explained in fig. 2.
`
`peer
`
` Eacgeenn
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`Fig. 4. A 256-bit static random-access memory made by the LOCMOSprocess. Thecircuit
`occupies an area of 5 mm?.
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`circuit would occupy at least 5 mm?2.
`The memory shown in fig. 4, occupies an area of
`5 mm2. The access time is 200 ns at a supply voltage of
`5 V andis less than 100 ns if the supply voltage is
`increased to 10 V. The dissipation is extremely small.
`A similar circuit made without using the LOCOS
`
`technique would occupy more than 10 mm2 and with
`a 5 V supply would have an access time of 600 ns.
`These examples, particularly the last one, show that
`the use of the LOCOS technique has considerably
`increased the possibility of applying CMOScircuits in
`LSI.
`
`Summary. Circuits with CMOStransistors have several good
`features, one of the most important being the low dissipation.
`It is however particularly difficult to apply them in LSI when
`conventional methods are used, partly because only low packing
`densities are obtainable. When the LOCOStechnique is used,
`in whichthesilicon is locally oxidized by meansofsilicon-nitride
`masking, circuits can be made that have high packing densities
`and high switching speeds. Noteworthy features of this new
`LOCMOStechniquearea special P-diffusion to produce a boron-
`concentration profile with a maximum belowthesilicon surface
`
`(to prevent parasitic N-channels from forming along the ‘LOCOS
`oxide’), and the use of the LOCOSoxide and the interconnection
`pattern for the gates as masking for the formation of the sources
`and drains.
`The article gives three examples of circuits made by the
`LOCMOStechnique: an inverter circuit with a delay time of
`3 to 5 ns, an 8-bit shift register occupying an area of 2.5 mm?
`and operating up to a frequency of 10 MHz, and a 256-bitstatic
`random-access memory with a surface area of 5 mm? and an
`access time of 100 to 200 ns.
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