Inter Partes review
`United States Patent 7,126,174
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`GlobalFoundries U.S. Inc.
`Petitioner
`
`v.
`
`Godo Kaisha IP Bridge 1
`Patent Owner
`
`
`
`Patent No. 7,126,174
`Filing Date: November 24, 2004
`Issue Date: October 24, 2006
`
`Title: SEMICONDUCTOR DEVICE AND
`METHOD OF MANUFACTURING THE SAME
`__________________________________________________________________
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.100 ET SEQ.
`
`
`
`
`
`
`1
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`Table of Contents
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`
`
` I.
`
`Preliminary Statement .................................................................................. 1
`
`
`
` Technological Background ........................................................................... 2 II.
`
`A.
`
`B.
`
`Integrated Circuits ................................................................................. 2
`
`Isolation Structures ................................................................................ 4
`
`
`
` 1.
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` 2.
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`LOCOS ....................................................................................... 4
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`Shallow Trench Isolation ........................................................... 5
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`C.
`
`Insulating Sidewalls .............................................................................. 7
`
`
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` The ’174 Patent ............................................................................................ 10 III.
`
`A. Admitted Prior Art............................................................................... 10
`
`B.
`
`C.
`
`D.
`
`Challenged Claims .............................................................................. 12
`
`Representative Embodiment ............................................................... 12
`
`The ’174 Patent Is Not Entitled to the Benefit of Foreign Priority
`Before December 19, 1995 .................................................................. 14
`
`
`
` Statement of Precise Relief Requested for Each Claim Challenged ....... 16 IV.
`
`A.
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`B.
`
`C.
`
`D.
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`Claims for Which Review is Requested .............................................. 16
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`Statutory Grounds of Challenge .......................................................... 16
`
`Level of Ordinary Skill ....................................................................... 16
`
`Claim Construction.............................................................................. 16
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`
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` Claims 1–3, 5–7, 9–12, and 14–18 of the ’174 Patent Are Unpatentable 17 V.
`
`A. Disclosures of the Prior Art ................................................................. 18
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` 1.
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` 2.
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` 3.
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`Lee (U.S. Patent No. 5,153,145) .............................................. 18
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`Noble (U.S. Patent No. 5,539,229) .......................................... 19
`
`Ogawa (U.S. Patent No. 4,506,434) ........................................ 20
`
`B.
`
`The Lee-Noble combination renders claims 1–3, 5–7, 9–12, and 14–
`18 obvious ........................................................................................... 22
`
`
`
` 1.
`
`A POSITA would have found it obvious, and even desirable,
`to have combined the teachings of Lee and Noble .................. 23
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`2.
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` 3.
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` 4.
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` 5.
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` 6.
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` 7.
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` 8.
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`9.
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`Claim 1 is obvious over the Lee-Noble combination ............... 32
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`Claim 2 is obvious over the Lee-Noble combination ............... 47
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`Claim 3 is obvious over the Lee-Noble combination ............... 48
`
`Claim 5 is obvious over the Lee-Noble combination ............... 50
`
`Claim 6 is obvious over the Lee-Noble combination ............... 52
`
`Claim 7 is obvious over the Lee-Noble combination ............... 53
`
`Claim 9 is obvious over the Lee-Noble combination ............... 54
`
`Claim 10 is obvious over the Lee-Noble combination ............. 57
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`
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` Claim 11 is obvious over the Lee-Noble combination ............. 60 10.
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`
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` Claim 12 is obvious over the Lee-Noble combination ............. 61 11.
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` Claim 14 is obvious over the Lee-Noble combination ............. 63 12.
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` Claim 15 is obvious over the Lee-Noble combination ............. 64 13.
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` Claim 16 is obvious over the Lee-Noble combination ............. 66 14.
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`
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` Claim 17 is obvious over the Lee-Noble combination ............. 70 15.
`
`16.
` Claim 18 is obvious over the Lee-Noble combination ............. 71
`
`C.
`
`The Lee-Ogawa combination renders claims 1–3, 5–7, 9–12, and
`14–18 obvious ..................................................................................... 73
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`
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` 1.
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` 2.
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` 3.
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` 4.
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` 5.
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` 6.
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` 7.
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` 8.
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` 9.
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`A POSITA would have combined the teachings of Lee and
`Ogawa ...................................................................................... 73
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`Claim 1 is obvious over the Lee-Ogawa combination ............. 79
`
`Claim 2 is obvious over the Lee-Ogawa combination ............. 82
`
`Claim 3 is obvious over the Lee-Ogawa combination ............. 82
`
`Claim 5 is obvious over the Lee-Ogawa combination ............. 83
`
`Claim 6 is obvious over the Lee-Ogawa combination ............. 83
`
`Claim 7 is obvious over the Lee-Ogawa combination ............. 83
`
`Claim 9 is obvious over the Lee-Ogawa combination ............. 84
`
`Claim 10 is obvious over the Lee-Ogawa combination........... 85
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`
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` Claim 11 is obvious over the Lee-Ogawa combination........... 86 10.
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`
`ii
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` Claim 12 is obvious over the Lee-Ogawa combination........... 86
`11.
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` Claim 14 is obvious over the Lee-Ogawa combination........... 86 12.
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`
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` Claim 15 is obvious over the Lee-Ogawa combination........... 86 13.
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` Claim 16 is obvious over the Lee-Ogawa combination........... 87 14.
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` Claim 17 is obvious over the Lee-Ogawa combination........... 87 15.
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`
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` Claim 18 is obvious over the Lee-Ogawa combination........... 87 16.
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`
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` Trial Should Be Instituted on Both Grounds ............................................ 88 VI.
`
` Mandatory Notices Under 37 C.F.R. §42.8 ............................................... 88
`VII.
`
`A.
`
`B.
`
`C.
`
`D.
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`Real Parties-In-Interest ........................................................................ 88
`
`Related Matters .................................................................................... 88
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`Lead and Back-Up Counsel ................................................................. 90
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`Service Information ............................................................................. 90
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`
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` Certification Under 37 C.F.R. §42.24(d) ................................................... 91 VIII.
`
`
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` Payment of Fees ........................................................................................... 91 IX.
`
`
`X.
`
`Time for Filing Petition ............................................................................... 91
`
`
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` Grounds for Standing .................................................................................. 91 XI.
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`
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` Conclusion .................................................................................................... 91 XII.
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`TABLE OF AUTHORITIES
`
`CASES
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`Page(s)
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`Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc) ......................... 16
`
`Liberty Mutual Inc. Co. v. Progressive Casualty Ins. Co., ..................................... 88
`CMB2012-00003, Paper 7, at 2 (Oct. 25, 2012)
`
`STATUTES AND RULES
`
`35 U.S.C. § 103 ........................................................................................................ 16
`
`35 U.S.C. § 311 ........................................................................................................ 16
`
`35 U.S.C. §§311–319 ........................................................................................... 1, 93
`
`MISCELLANEOUS
`
`37 C.F.R. § 42.1(b) .................................................................................................. 88
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`37 C.F.R. § 42.8 ................................................................................................. 88, 91
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`37 C.F.R. § 42.15(a) ................................................................................................. 91
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`37 C.F.R. § 42.24 ..................................................................................................... 91
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`37 C.F.R. § 42.24(d) ................................................................................................ 91
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`37 C.F.R. § 42.100(b) .............................................................................................. 17
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`37 C.F.R. § 42.100 et seq. .................................................................................... 1, 93
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`37 C.F.R. §§ 42.103(a) ............................................................................................. 91
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`37 C.F.R. § 42.104(a) ............................................................................................... 91
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`37C.F.R. § 42.122(b) ............................................................................................... 91
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`iv
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`
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`LIST OF EXHIBITS
`
`Global Ex. 1001:
`
`U.S. Patent No. 7,126,174 to Segawa et al.
`
`Global Ex. 1002:
`
`U.S. Patent No. 5,153,145 to Lee et al.
`
`Global Ex. 1003:
`
`U.S. Patent No. 3,617,824 to Shinoda et al.
`
`Global Ex. 1004:
`
`Expert Declaration of Dr. Sanjay Banerjee, Ph.D.
`
`Global Ex. 1005:
`
`J.A. Appels et al., “Some Problems of MOS
`Technology,” Philips Tech. Rev. vol. 31 nos. 7–9, pp.
`225–36, 276 (1970).
`
`Global Ex. 1006
`
`U.S. Patent No. 4,110,899 to Nagasawa et al.
`
`Global Ex. 1007:
`
`U.S. Patent No. 3,787,251 to Brand et al.
`
`Global Ex. 1008:
`
`B.B.M. Brandt et al., “LOCMOS, a New Technology for
`Complementary MOS Circuits,” Philips Tech. Rev. vol.
`34 no. 1, pp. 19–23 (1974).
`
`Global Ex. 1009:
`
`U.S. Patent No. 5,702,976 to Schuegraf et al.
`
`Global Ex. 1010
`
`U.S. Patent No. 4,506,434 to Ogawa et al.
`
`Global Ex. 1011:
`
`U.S. Patent No. 4,957,590 to Douglas
`
`Global Ex. 1012:
`
`U.S. Patent No. 5,976,939 to Thompson et al.
`
`Global Ex. 1013:
`
`U.S. Patent No. 6,165,826 to Chau et al.
`
`Global Ex. 1014:
`
`U.S. Patent No. 5,733,812 to Ueda et al.
`
`Global Ex. 1015:
`
`U.S. Patent No. 5,539,229 to Noble, Jr. et al.
`
`Global Ex. 1016:
`
`U.S. Patent No. 5,521,422 to Mandelman et al.
`
`Global Ex. 1017:
`
`U.S. Patent No. 5,021,353 to Lowrey et al.
`
`Global Ex. 1018:
`
`U.S. Patent No. 4,638,347 to Iyer
`
`Global Ex. 1019:
`
`Global Ex. 1020:
`
`Japanese Patent Application No. 7-192181 to Segawa et
`al.
`
`Certified Translation of Japanese Patent Application No.
`7-192181 to Segawa et al.
`
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`v
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`Global Ex. 1021:
`
`Global Ex. 1022:
`
`Global Ex. 1023:
`
`File History of U.S. Patent No. 7,126,174 to Segawa et
`al.
`
`File History of Japanese Patent Application No. 7-
`330112 to Segawa et al.
`
`Certified Translation of Portions of the File History of
`Japanese Patent Application No. 7-330112 to Segawa et
`al.
`
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`vi
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`
`
`I.
`
`Preliminary Statement
`
`U.S. Patent No. 7,126,174 to Segawa et al. (Ex. 1001) is directed to
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`structures for metal-oxide-semiconductor field-effect transistors (“MOSFETs”)
`
`and their interconnections. MOSFETs, which can act as switches in integrated
`
`circuits, are linked by interconnections, which connect parts of an integrated circuit
`
`to one another.
`
`MOSFET integrated circuits debuted as early as 1965 (see Ex. 1003). By
`
`the mid-1990s, MOSFET/interconnection structures were ubiquitous. Virtually all
`
`of the limitations in the challenged claims were known and constitute admitted
`
`prior art. (See Ex. 1001, 1:52–5:51, Figs. 17, 20(e).) The only feature of the sole
`
`independent claim in the ’174 patent, claim 1, that is not admitted prior art is the
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`feature of “L-shaped” sidewalls over the MOSFET and interconnection. But this
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`feature had been known for over a decade before the ’174 patent was filed.
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`This Petition, supported by the Expert Declaration of Sanjay Banerjee,
`
`Ph.D., (Ex. 1004), establishes that the challenged claims are unpatentable over the
`
`prior art. GlobalFoundries, Inc. (“Global”) respectfully requests inter partes
`
`review under 35 U.S.C. §§311–319 and 37 C.F.R. §42.100 et seq. and cancellation
`
`of all challenged claims.
`
`
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`
`1
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`

`

`
`
` Technological Background
`II.
`
`A.
`
`Integrated Circuits
`
`A MOSFET includes a “source,” an inlet to receive current, and a “drain” as
`
`an outlet to output current. (Ex. 1004, ¶44.) Electrodes on the source and drain
`
`allow current to flow into and out of the transistor. (Id.) Another basic MOSFET
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`element is a “gate,” which controls current flow between the source and drain
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`through a “channel” beneath the gate. (Id.) The gate includes a gate insulator
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`(“gate oxide” or “gate dielectric”) and a gate electrode (“gate”). (Id., ¶45.) The
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`gate electrode can receive a control voltage to switch the MOSFET on and off, and
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`the gate insulator generates an associated electric field that controls the channel.
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`(Id.) “ON” and “OFF” states of a MOSFET are depicted below. (Id.; Ex. 1003,
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`Fig. 5 (below with color annotation).)
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`
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`
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`ON
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`OFF
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`To form circuits, MOSFETs are connected by interconnections, which are
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`electrical conductors that provide pathways for electrical signals. (Ex. 1004, ¶46.)
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`2
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`They can be made from a variety of conducting materials, including metals, metal
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`alloys, metal compounds, polycrystalline silicon (polysilicon), and combinations of
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`these (e.g., metal-silicon compounds, called “silicides”). (Id.)
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`Integrated circuits having multiple MOSFETs and interconnections have
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`existed for over 50 years. For example, a patent filed in 1965 discloses multilevel
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`interconnections formed between MOSFETs in an integrated circuit. (U.S. Patent
`
`No. 3,617,824 to Shinoda et al., Ex. 1003, 4:30–73, Figs. 6–7 (below with color
`
`and annotation).)
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`3
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`B.
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`Isolation Structures
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`The semiconductor industry has steadily moved towards packing more
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`MOSFETs onto each chip. (Ex. 1004, ¶48.) As device densities increase, the
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`distance between devices shrinks, and by the early 1970s, decreasing inter-device
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`distances started to cause undesirable interactions between circuit elements. (See
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`Ex. 1005, 10–12; Ex. 1006, 1:40–2:26; Ex. 1007, 1:6–2:32; Ex. 1004, ¶49.) The
`
`industry’s solution to this problem was to include insulating “isolation” regions
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`between the devices to shield them from one another. (Ex. 1005, 10–12; Ex. 1006,
`
`1:7–2:66; Ex. 1007, 1:6–2:32; Ex. 1008, 2–5; Ex. 1004, ¶49.) Use of such
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`isolation regions has continued through the present time. (Ex. 1004, ¶49.)
`
`
`1.
`
`LOCOS
`
`Reported as early as 1970, LOCOS (LOCal Oxidation of Silicon) was one of
`
`the first isolation techniques. (Ex. 1005, 2, 13; Ex. 1008, 2 & n.4; Ex. 1006, 1:8–
`
`14, 1:63–68; Ex. 1004, ¶50.) In LOCOS, selected regions of a silicon substrate are
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`exposed to oxygen at a high temperature to convert the silicon in those regions into
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`4
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`silicon dioxide. (Ex. 1005, 4, 6, 10; Ex. 1006, 3:18–20, 4:18–34; Ex. 1008, 2–3;
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`Ex. 1004, ¶50.)
`
`LOCOS has drawbacks. Silicon dioxide grows laterally as the substrate is
`
`oxidized, resulting in unintentional silicon dioxide projections into MOSFET
`
`regions, called “overhang” or “bird’s beaks.” (Ex. 1006, 6:1:10; Ex. 1009, 1:47–
`
`59; Ex. 1004, ¶51; Ex. 1008, Fig. 2a; Ex. 1010, 1:33–42, Fig. 1 (below with color
`
`and annotation).) By the mid-1990s, this bird’s beak “pose[d] a limitation to
`
`device density” that could be addressed by new isolation techniques. (Ex. 1009,
`
`1:47–59; see also Ex. 1001, 1:29–43 (admitted prior art); Ex. 1004, ¶51.) The
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`bird’s beak (see annotated Fig. 1 below from U.S. Patent No. 4,506,434 to Ogawa
`
`et al.) also causes undesirable strain. (Ex. 1010, Fig. 1, 1:42–50).
`
`
`2.
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`Shallow Trench Isolation
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`
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`Shallow trench isolation (STI) was developed to replace LOCOS for small-
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`device processes. (Ex. 1001, 1:29–43; Ex. 1009, 2:20–24; Ex. 1004, ¶52.) In STI,
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`trenches are etched into the substrate and filled with insulating material. (Ex.
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`5
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`1004, ¶52.) Although more expensive and complex than LOCOS, STI resolves the
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`problems of LOCOS. (Ex. 1009, 2:20–24; Ex. 1010, 1:60–68; Ex. 1004, ¶52.)
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`Because they are so similar otherwise, STI and LOCOS are interchangeable and
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`functionally equivalent. (See Ex. 1009, 1:31–2:24; Ex. 1011, 4:8–16; Ex. 1012,
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`3:1–10; Ex. 1013, 5:56–67; Ex. 1014, 22:49–52; Ex. 1004, ¶¶53, 82, 198.) D espite
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`the added expense and complexity, the industry adopted STI to increase device
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`density. (Ex. 1004, ¶53; see also Ex. 1002, 1:10–14.)
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`In some STI processes, the top of the isolation structure is level with the
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`substrate surface. The industry recognized, however, that such an arrangement can
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`interfere with MOSFET operation if the transistors are packed too closely, as sharp
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`corners of the STI structure enhance local electric fields that degrade device
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`performance. (Ex. 1016, 1:16–37, Abstract, 1:6–35, Figs. 6a, 6b; Ex. 1004, ¶54.)
`
`These problems become worse if the isolation trench recesses below the substrate
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`surface during subsequent etches because the gate can then “wrap around” the
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`trench corner. (Ex. 1016, 1:30–37, 3:27–48, 4:58–62, Fig. 2; Ex. 1004, ¶54.)
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`To mitigate the wrap-around problem, a raised STI structure can extend
`
`above the substrate surface. (See Ex. 1015, 5:49–55, 6:32–50, Fig. 12; Ex. 1016,
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`Abstract, 3:33–34, Fig. 5; Ex. 1004, ¶55.) Raised STI also helps localize
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`source/drain regions by providing a barrier during the ion implantation or diffusion
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`processes used to make them. (Ex. 1015, Abstract, 4:62–65, 5:5–8; Ex. 1004, ¶55.)
`
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`6
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`Raised STI structures from the prior art appear below in red. (Ex. 1010, Fig. 5(b);
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`Ex. 1015, Fig. 11; Ex. 1016, Fig. 5.)
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`C.
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`Insulating Sidewalls
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`The ’174 patent acknowledges that a “conventional semiconductor device”
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`
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`had MOSFETs, interconnections, and STI regions with sidewalls. (Ex. 1001,
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`1:52–2:21, Figs. 17 (below with color annotation), 20(e); Ex. 1004, ¶56.).
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`Sidewalls 7a and 7b of features 4a and 4b, respectively, appear below.
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`7
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`Sidewalls can (1) prevent damage during etching, (2) insulate electrodes and
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`interconnections to eliminate short-circuits, (3) control the shape of the
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`source/drain regions by creating a barrier against the migration of impurities, and
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`(4) reduce parasitic leakage current. (Ex. 1015, 5:5–9, 6:6–8, 6:32–50; Ex. 1002,
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`1:44–54, 1:64–2:20, 3:22–30, 5:51–6:4, 6:62–7:7, 7:44–8:5, Fig. 15; Ex. 1016,
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`1:6–10, 3:49–53, 4:5–17, 4:30–32, 4:58–5:2, Fig. 5; Ex. 1017, 8:58–9:2; Ex. 1004,
`
`¶57.)
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`One of the prior-art references relied on in this petition, U.S. Patent
`
`No. 5,153,145 to Lee et al. (Ex. 1002), provides sidewalls on gates and gate
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`runners (interconnections) to avoid short-circuits. (Id., 1:47–54.) In response to
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`“increasingly complex interconnection schemes” (Ex. 1002, 1:44–47), Lee
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`provided insulating sidewalls on the gates and gate runners (Id., 6:62–7:7, Figs. 13,
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`15). These “prevent[] electrical contact between patterned layer 170 and the
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`conductive polysilicon heart 117′ of runner 203” and “facilitate[] the formation of
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`a sub-gate level interconnection between junction regions of different transistors . .
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`. without the possibility of shorting to a gate runner.” (Id., 7:44–8:5.) Figure 15 of
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`Lee appears below with color.
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`8
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`The process for creating a silicon-metal “silicide” may damage the gate (id.,
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`1:40–43), so Lee discloses insulating gate sidewall spacers between the gate and
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`source/drain to address this. (Id., 4:41–5:4, 5:51–60, 7:16–25, Fig. 9 (shown below
`
`with color).) Lee explains that sidewalls “prevent the migration of other types or
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`particles into the gate stack” to avoid “shorting of the gate to the source/drain.”
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`(Id., 5:61–6:30; Ex. 1004, ¶59.)
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`
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`As Lee and other references show, L-shaped sidewalls were known in the
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`semiconductor processing art. (Ex. 1004, ¶60; Ex. 1002, 3:8–21, Figs. 9, 15;
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`Ex. 1018, 3:61–68, Fig. 5 (shown below on left with color); Ex. 1012, 3:1–10, 4:1–
`
`10, Fig. 7 (shown below on right with color).)
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`9
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` The ’174 Patent III.
`
`A.
`
`Admitted Prior Art
`
`The ’174 patent describes a semiconductor device “with high integration and
`
`a decreased area.” (Ex. 1001, 1:13–16.) The ’174 patent explains that “there
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`[we]re increasing demands for more refinement of the semiconductor device.”
`
`(Id., 1:17–20.) Although “the LOCOS isolation method [had been] conventionally
`
`adopted in view of its simpleness [sic] and low cost,” the ’174 patent admits that
`
`others already recognized that trench isolation was “more advantageous for
`
`manufacturing a refined semiconductor device.” (Id., 1:17–28.) This was because
`
`the bird’s beak of LOCOS “invades a transistor region against the actually
`
`designed mask dimension,” which was “unallowable” for scaling beyond 0.5 µm.
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`(Id., 1:29–36.) The ’174 patent further admits, “even in the mass-production
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`techniques, the isolation forming method ha[d] started to be changed to the trench
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`isolation method.” (Id., 1:36–43.) The ’174 patent also describes “conventional
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`semiconductor device[s]” with “the conventional trench isolation,” shown below in
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`color-annotated Figures 17 and 20(e). (Id., 1:44–2:22, 3:53–5:11.) The ’174 patent
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`further shows that trench isolation with a top surface higher than the surface of the
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`semiconductor substrate is part of a “conventional trench isolation and a
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`MOSFET.” (Id., 3:53–55, 3:64–4:8, 4:45–58, 4:16–19, Figs. 19, 20(a)–20(e)
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`(Fig. 20(e) shown below with color annotations).)
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`B.
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`Challenged Claims1
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`The only independent claim of the ’174 patent recites:
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`1. A semiconductor device, comprising:
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`a trench isolation surrounding an active area of a semiconductor
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`substrate;
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`a gate insulating film formed over the active area;
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`a gate electrode formed over the gate insulating film;
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`first L-shaped sidewalls formed over the side surfaces of the
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`gate electrode;
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`first silicide layers formed on regions located on the sides of the
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`first L-shaped sidewalls within the active area;
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`an interconnection formed on the trench isolation; and
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`second L-shaped sidewalls formed over the side surfaces of the
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`interconnection.
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`(Ex. 1001, 29:39–50.) Claims 2, 3, 5–7, 9–12, and 14–18 depend, directly or
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`indirectly, from claim 1.
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`C.
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`Representative Embodiment
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`As shown below in color-annotated Figure 15(f) of the ’174 patent, one
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`embodiment of the claimed structure has a trench isolation region (2b), a gate
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`electrode (4a), an interconnection (4b), a gate electrode sidewall (32a), and an
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`interconnection sidewall (32b). (Ex. 1001, 21:39–65, 26:40–54, 27:4–8, Figs.
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`15(a)–15(f).) Isolation region 2b may have a top surface higher in a stepwise
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`1 The challenged claims are claims 1–3, 5–7, 9–12, and 14–18.
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`12
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`manner than the surface of an active area. (Ex. 1001, 13:49–64, 15:34–36.)
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`Further, the gate and interconnection sidewalls (32a and 32b) are “L-shaped.” (Id.,
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`27:4–8.)
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`For comparison, “a semiconductor device including the conventional trench
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`isolation and a MOSFET having the salicide structure,” as the ’174 patent
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`characterizes it, is shown below. (Ex. 1001, 3:53–5:11, Fig. 20(e) (below with
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`color annotations).) The only difference relevant to the claim limitations is the “L-
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`shaped” sidewall feature.
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`D.
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`The ’174 Patent Is Not Entitled to the Benefit of Foreign Priority
`Before December 19, 1995
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`The ’174 patent, filed on November 24, 2004,2 claims priority to Japanese
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`Patent Application No. 7-192181 (“the ’181 application”) (Ex. 1019; Ex. 1020),
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`filed on July 27, 1995, and Japanese Patent Application No. 7-330112 (“the ’112
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`application”) (Ex. 1022; Ex. 1023), filed on December 19, 1995.3 The challenged
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`claims are not entitled to the July 1995 priority date.
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`The ’181 application does not disclose the claimed “first silicide layers” or
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`even mention silicide. The local interconnection (13) is polysilicon, as is the
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`2 The ’174 patent claims priority through a line of intervening applications to
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`parent U.S. Application No. 08/685,726, filed on Jul. 24, 1996. (Ex. 1021, 137.)
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`3 The Japanese Patent Office rejected these applications over the prior art and
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`never issued a patent. (Ex. 1023, 187–93.)
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`interconnection (4b). (Ex. 1020, ¶¶0004, 0009, 0057, 0066, 0072, 0078–0081,
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`0086, 0094, p. 28.)
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`The ’181 application also does not provide support for the required “first
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`L-shaped sidewalls formed over the side surfaces of the gate electrode” or “second
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`L-shaped sidewalls formed over the side surfaces of the interconnection.” The
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`term “L-shaped” does not appear in the ’181 application, and the structures shown
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`in the ’181 application lack the claimed “L” shape. (See Ex. 1019, 38–45;
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`Ex. 1004, ¶¶66–69.) The “sidewalls” in the ’181 application, labeled 7a and 7b, are
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`not even remotely L-shaped. (See Ex. 1020, Fig. 4(a) (below with color
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`annotations).)
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`The “insulating film” of the ’181 application, labeled 12, does not constitute
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`L-shaped sidewalls either. A POSITA (“person of ordinary skill in the art”) would
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`not have considered a unitary layer that extends over the entire gate or
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`interconnection to be a “sidewall” or to have “sidewalls.” (Ex. 1004,¶¶67–69.)
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`Due to these deficiencies, the ’174 patent is not entitled to the July 27, 1995,
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`priority date of the ’181 application. Because the ’174 patent does not claim the
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`benefit of foreign priority to any other document other that the ’112 application
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`filed December 19, 1995, the ’174 patent is not entitled to a benefit of foreign
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`priority earlier than December 19, 1995.
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` Statement of Precise Relief Requested for Each Claim Challenged IV.
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`A.
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`Claims for Which Review is Requested
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`Global requests review under 35 U.S.C. §311 of claims 1–3, 5–7, 9–12, and
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`14–18, and the cancellation of those claims as unpatentable.
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`B.
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`Statutory Grounds of Challenge
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`Claims 1–3, 5–7, 9–12, and 14–18 are unpatentable under 35 U.S.C. §103.
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`C.
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`Level of Ordinary Skill
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`A POSITA would possess (1) the equivalent of a Master of Science degree
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`from an accredited institution in electrical engineering, materials science, physics,
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`or the equivalent; (2) a working knowledge of semiconductor processing
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`technologies for integrated circuits; and (3) at least two years of experience in
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`related semiconductor processing analysis, design, and development. Additional
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`graduate education could substitute for professional experience, and significant
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`work experience could substitute for formal education. (Ex. 1004, ¶72.)
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`D.
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`Claim Construction
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`Claim terms are given their ordinary and accustomed meaning as understood
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`by a POSITA. Phillips v. AWH Corp., 415 F.3d 1303, 1312–13 (Fed. Cir. 2005)
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`(en banc). Although a claim in an unexpired patent in inter partes review receives
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`the “broadest reasonable construction in light of the specification of the patent in
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`which it appears” (37 C.F.R. §42.100(b)), the ’174 patent will expire on July 24,
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`2016, so the Phillips standard for claim construction should govern this petition,
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`see id. The plain and ordinary meaning as understood by a POSITA should be
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`applied to all claim terms of the ’174 patent.
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` Claims 1–3, 5–7, 9–12, and 14–18 of the ’174 Patent Are Unpatentable
`V.
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`Lee (Ex. 1002) teaches every limitation of the challenged claims except
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`trench isolation. It uses LOCOS isolation instead. Noble (Ex. 1015) and Ogawa
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`(Ex. 1010) each disclose devices very similar to Lee, but which use trench
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`isolation. Therefore, the Lee-Noble and Lee-Ogawa combinations disclose every
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`limitation of the challenged claims.
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`A POSITA would have found it obvious to make the Lee-Noble and Lee-
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`Ogawa combinations for many reasons. The admitted prior art of the ’174 patent,
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`and other contemporary references, describe the transition in the 1990s away from
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`LOCOS toward trench isolation. Moreover, a POSITA would have understood
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`that replacing Lee’s LOCOS with Noble’s STI or Ogawa’s trench isolation would
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`have been a simple substitution of one element for a known equivalent according
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`to known methods to achieve predictable results. A POSITA would have further
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`understood that making such combinations would have provided numerous
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`benefits.
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`A.
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`Disclosures of the Prior Art
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`1.
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`Lee (U.S. Patent No. 5,153,145)
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`Lee (Ex. 1002) teaches every element of the challenged claims except trench
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`isolation.
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`Lee was filed on October 17, 1989, and issued on October 6, 1992. It
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`therefore qualifies as prior art under §102(b). Lee was neither considered nor cited
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`during prosecution of the ’174 patent.
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`Lee discloses a MOSFET/interconnection structure. Referring to the
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`illustration of the Lee structure below (colored and annotated Fig. 15 of Lee), Lee
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`discloses a silicon substrate (111) (Ex. 1002, 6:49–50, Fig. 15), a LOCOS region
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`(113) (id., 6:50–51, Fig. 15), source/drain regions (300, 301, 302) (id., 7:16–28,
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`Fig. 15), a gate insulator (115) (id., 6:51–52, Fig. 15), a gate electrode (117) (id.,
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`6:52–53, 6:62–7:4, Fig. 15), sidewall spacers (119, 121, 123) (id., 7:13–15, Fig.
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`15), optional source/drain silicide regions (51, 53) (id., 4:41–52, 7:16–25, Fig. 9),
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`and a “gate runner” (i.e., interconnection) (117) (id., 6:67–7:4, Fig. 15). A
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`representative illustration of Lee’s Figure 15 with optional source/drain silicide,
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`appended to the figure by Petitioner, appears below with color and annotations.
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`2.
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`Noble (U.S. Patent No. 5,539,229)
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`Noble (Ex. 1015) teaches trench isolation. Noble was filed on December 28,
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`1994, and issued on July 23, 1996. It therefore qualifies as prior art under §102(e).
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`Noble “relates to shallow trench isolation (STI) in which the insulating
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`material is raised above the surface of the semiconductor.” (Ex. 1015, 1:7–10,
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`Fig. 13 (below).) Noble discloses a silicon substrate (10) (Id., 3:59–62), a raised
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`STI region (30) (id., 4:14–19, 4:40–45, 4:63–65), substrate source/drain regions
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`(138, 156) (id., 6:13–31), a gate dielectric (14) (id., 3:64–4:1, 4:11–14), a gate
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`conductor (116) (id., 5:67–6:6), dielectric spacers (152) (id., 6:6–8), silicide
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`regions (158) (id., 6:24–26), and conductive wiring level (140) (id., 5:53–61,
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`5:67–6:6). (Ex. 1004, ¶78.) Noble’s Figure 13, with color and annotations,
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`appears below.
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`3.
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`Ogawa (U.S. Patent No. 4,506,434)
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`Ogawa (Ex. 1010) also teaches trench isolation. Ogawa was filed on
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`September 3, 1982, and issued on March 26, 1985. It therefore qualifies as prior
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`art under §102(b). Ogawa was neither considered nor cited during prosecution of
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`the ’174 patent.
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`Ogawa teaches “a method wherein each element is isolated from one another
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`by buried insulating layers which are grown to fill grooves produced along the
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`surface of a silicon (Si) substrate to surround each element.” (Ex. 1010, 1:61–66;
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`see also 1:8–15, Fig. 5(c) (below).) Referring to the colored and annotated Fig.
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`5(c) below, Ogawa discloses a silicon substrate (51) (id., 7:43–47), a buried
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`silicon dioxide layer (52) that extends above the active region of the substrate (id.,
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`7:43–47, Fig. 5(c)), a silicon dioxide layer (54) as a gate oxide (id.), a
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`polycrystalline silicon layer (55) and molybdenum silicide layer (56) double-
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`layer gate electrode (id., 7:51–56, 8:35–38, Fig. 5(c)), a molybdenum silicide
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`layer (57[sic])4 as a wiring/interconnect level (id., 7:51–56, 8:67–9:5, Fig. 5 (c)),
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`and sources and drains (58) (id., 8:3–7, Fig. 5(c)). (Ex. 1004, ¶80.) Ogawa’s
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`Figure 5(c), a representative illustration, appears below with color and annotations.
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`4 The label 57 is erroneous in Figure 5(c). (Ex. 1004, ¶81 n.1.) It should read
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`“56.” (Id.) Layer 57 is a photoresist layer not shown in Figure 5(c). Element 57
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`in Figure 5(c) corresponds to layer 56 of Figures 5(a) and 5(b). (Ex. 1010, 7:53–
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`56, Figs. 5(a)–5(c).)
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`B.
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`The Lee-Noble combination renders claims 1–3, 5–7, 9–12,