CERTIFICATE OF TRANSLATION
`
`I Roger P. Lewis, whose address is 42 Bird Street North,
`Martinsburg WV 25401, declare and state the following:
`
`I am well acquainted with the English and Japanese languages
`and have in the past translated numerous English/Japanese
`documents of legal and/or technical content.
`
`I hereby certify that the Japanese translation of the
`attached document identified as:
`
`JP7-192181
`
`is true, and that all statements of information and belief
`are believed to be true, and that these and similar
`statements are punishable by fines or imprisonment, or both,
`under Section 1001 of Title 18 of the United States Code.
`
`SINCERELY,
`
`ROGER P. LEWIS
`
`Date: June 10, 2016
`
`1
`
`Global Foundaries US v. Godo Kaisha
`Global Ex. 1020
`
`Page 1 of 30
`
`

`

`Patent Application
`[Document Name]
`2020270178
`[Control Number]
`[Date of Submission] July 27, 1995
`[Addressee]
`
`Japan Patent Office Director
`[International Patent Classification] H01L 27/118
`
`
`
`
`
`H01L 21/82
`[Title of Invention] Semiconductor device and method of manufacturing the same
`[Number of Claims] 17
`
`[Inventor]
`Matsushita Electric Industrial Co., Ltd.
`
`[Home/Office Address]
`1006 Kadoma, Kadoma City, Osaka
`
`
`
`
`
`
`[Name]
`Mizuki Segawa
`
`[Inventor]
`Matsushita Electric Industrial Co., Ltd.
`
`[Home/Office Address]
`1006 Kadoma, Kadoma City, Osaka
`
`
`
`
`
`
`[Name]
`Isao Miyanaga
`
` [Inventor]
`
`[Home/Office Address]
`
`
`
`
`
`
`[Name]
`Toshiki Yabu
`
` [Inventor]
`Matsushita Electric Industrial Co., Ltd.
`
`[Home/Office Address]
`1006 Kadoma, Kadoma City, Osaka
`
`
`
`
`
`
`[Name]
`Takashi Nakabayashi
`
` [Inventor]
`Matsushita Electric Industrial Co., Ltd.
`
`[Home/Office Address]
`1006 Kadoma, Kadoma City, Osaka
`
`
`
`
`
`
`[Name]
`Takashi Uehara
`
` [Patent Applicant]
`000005821
`
`[Identification Number]
`
`[Name]
`Matsushita Electric Industrial Co., Ltd
`
`[Representative]
`Yoichi Morishita
`
`[Agent]
`
`[Identification Number]
`
`[Benrishi]
`
`[Name]
`
`[Agent]
`
`[Identification Number]
`
`Matsushita Electric Industrial Co., Ltd.
`1006 Kadoma, Kadoma City, Osaka
`
`100094134
`
`100077931
`
`Hiroshi Maeda
`
`Page 2 of 30
`
`

`

`
`
`
` [Agent]
`
`[Identification Number]
`
`[Benrishi]
`
`[Name]
`
` [Disclosure of Commission]
`
`[Method of Payment] Prepayment
`
`[Prepayment Ledger Number]
`
`[Payment Amount]
`21,000 yen
`
`[List of Items Submitted]
`
`[Item Name] Specification 1
`
`[Item Name] Drawings
`1
`
`[Item Name] Abstract
`1
`
`[Letter of Attorney Number] 9006026
`
`[Letter of Attorney Number] 9110638
`
`[Necessity of Proof] Necessary
`
`014409
`
`
`
`
`
`[Benrishi]
`[Name]
`
`Hiroki Oyama
`
`100100262
`
`Tsutomu Matsunaga
`
`Page 3 of 30
`
`

`

`Specification
`[Document Name]
`[Title of Invention] Semiconductor device and method of manufacturing the same
`[Scope of Claims]
`[Claim 1]
`
`A semiconductor device comprising:
`
`a semiconductor substrate;
`
`an isolation formed such that the top surface is higher in a stepwise manner than the
`surface of the semiconductor substrate;
`
`a plurality of active areas formed by introducing impurities in the semiconductor
`substrate surrounded by the isolation;
`
`an insulating film formed so as to stretch over the active areas and the isolation;
`
`contact holes formed so as to expose a part of the insulating film, at least a portion of the
`contact holes reaching to the surface of the active areas; and
`
`an upper interconnection formed above the insulating film and in the contact hole, the
`upper interconnection connecting to the active areas.
`
`[Claim 2]
`
`The semiconductor device according to Claim 1, wherein through dispersion in
`manufacturing procedures of the semiconductor device, at least some of the contact holes out of
`the plurality of contact holes are formed so as to stretch from the surface of the active areas to
`the isolation.
`
`[Claim 3]
`
`The semiconductor device according to Claim 1, further comprising:
`
`an interconnection member formed such that at least a portion thereof is positioned on the
`isolation;
`
`wherein the contact holes are formed so as to stretch from the surface of the active areas
`to the interconnection member near the active areas; and
`
`the upper interconnection is also connected to an interconnection member on the isolation.
`
`[Claim 4]
`
`The semiconductor device according to any one of Claims 1 to 3, further comprising:
`
`an isolation sidewall made of an insulating material and formed on a side surface of a
`step portion from the surface of the active areas reaching to the top surface of the isolation;
`
`wherein the contact holes are formed so as to stretch over the isolation sidewall.
`
`[Claim 5]
`The semiconductor device according to Claim 1, wherein the dimensions and materials of
`the respective components can be determined so as to satisfy the inequality:
`OE × a × (ER2/ER1) ≥ b + D × (2/10),
`wherein "a" denotes the thickness of the insulating film; "b" denotes the level difference
`between the surface of the field oxide film and the surface of the active area; "ER1" denotes the
`etching rate of the insulating film; "ER2" denotes the etching rate of the field oxide film; "D"
`denotes the depth of an impurity diffused layer in the active area; and "OE" denotes the over-etch
`ratio of the insulating film in the formation of the contact hole.
`
`
`Page 4 of 30
`
`

`

`[Claim 6]
`
`The semiconductor device according to Claim 1, further comprising:
`
`a FET having a gate electrode formed on top of the active area, a source/drain region
`formed in the active area positioned on both side surfaces of the gate electrode, and a gate
`protection film formed on top of the gate electrode;
`
`wherein the contact holes are formed so as to stretch from the source/drain region to at
`least a portion of the gate protection film.
`
`[Claim 7]
`
`The semiconductor device according to Claim 4, further comprising:
`
`a FET having a gate electrode formed on the active area, a source/drain region formed in
`the semiconductor substrate positioned to the side of the gate electrode, a gate protection film
`formed on top of the gate electrode, and an electrode sidewall formed on both side surfaces of
`the gate electrode;
`
`wherein the isolation sidewall is formed at the same time as the electrode sidewall.
`
`[Claim 8]
`
`The semiconductor device according to Claim 6 or Claim 7, wherein the dimensions and
`materials of the respective components are determined so as to satisfy the inequality:
`OE × a × (ER3/ER1) < c,
`wherein "a" denotes the thickness of the insulating film; "c" denotes the thickness of the
`gate protection film; "ER1" denotes the etching rate of the insulating film; "ER3" denotes the
`etching rate of the gate protection film; and "OE" denotes the over-etch ratio of the insulating
`film in the formation of the contact hole.
`
`[Claim 9]
`
`The semiconductor device according to Claim 1, wherein the angle of inclination of the
`side surface of the step portion from the surface of the active area to the surface of the isolation
`to the semiconductor substrate surface is at least 70 degrees.
`
`[Claim 10]
`
`A manufacturing method for a semiconductor device, the method including:
`
`a procedure for forming, on a semiconductor substrate, an isolation having a top surface
`that is higher in a stepwise manner than the surface of the semiconductor substrate;
`
`a procedure for introducing impurities in a plurality of active areas surrounded by the
`isolation in the semiconductor substrate;
`
`a procedure for depositing an insulating film on the active areas and the isolation;
`
`a procedure for forming a mask member having an exposing area for forming contact
`holes to the active areas, on the insulating film;
`
`a procedure for removing the insulating film in the exposing area of the mask member
`through etching, and furthermore accomplished a prescribed over-etch, thereby forming a contact
`hole; and
`
`a procedure for forming an upper interconnection connecting to the active areas above the
`insulating film and in the contact hole;
`
`wherein in the procedure for forming the mask member, a margin is not provided for
`ensuring that the exposing area of the mask member does not include the isolation when a mask
`
`Page 5 of 30
`
`

`

`alignment shift occurs in the photolithography.
`
`[Claim 11]
`The manufacturing method for a semiconductor device according to Claim 10,
`accomplished so as to satisfy the inequality:
`OE × a × (ER2/ER1) ≥ b + D × (2/10),
`wherein "a" denotes the thickness of the insulating film; "b" denotes the level difference
`between the surface of the field oxide film and the surface of the active area; "ER1" denotes the
`etching rate of the insulating film; "ER2" denotes the etching rate of the field oxide film; "D"
`denotes the depth of an impurity diffused layer in the active area; and "OE" denotes the over-etch
`ratio of the insulating film in the formation of the contact hole.
`
`[Claim 12]
`
`The manufacturing method for a semiconductor device according to Claim 10, wherein in
`the procedure for forming the mask member, the mask member is formed with the position
`thereof determined so that the exposing area of the mask member includes at least a portion of
`the isolation when a mask alignment shift does not occur in the photolithography.
`
`[Claim 13]
`
` The manufacturing method for a semiconductor device according to Claim 10, further
`including:
`
`a procedure for forming an interconnection member on the isolation;
`
`wherein in the procedure for forming the mask member, the mask member is formed so
`that the exposing area of the mask member includes at least a portion of the active areas and the
`interconnection member.
`
`[Claim 14]
`
`The manufacturing method for a semiconductor device according to Claim 10, further
`including:
`
`a procedure for forming a MISFET gate insulating film and a gate electrode on the active
`areas, after the procedure for forming the isolation; and
`
`a procedure for depositing an insulating film for forming sidewalls on the gate electrode,
`the active area and the isolation, then doing anisotropic etching to form an electrode sidewall on
`both side surfaces of the gate electrode, and forming an isolation sidewall on the side surface of
`the step portion between the isolation and the active area.
`
`[Claim 15]
`
`The manufacturing method for a semiconductor device according to Claim 10, further
`including:
`
`a procedure for depositing and forming a MISFET gate insulating film, a gate electrode
`and a gate protection film made of insulating materials on the active areas, after the procedure
`for forming the isolation;
`
`wherein in the procedure for forming the mask member, the mask member is formed with
`the position thereof determined without providing a margin for ensuring that the exposing area of
`the mask member does not include a portion of the gate protection film even if a mask alignment
`shift occurs in the photolithography.
`
`Page 6 of 30
`
`

`

`
`[Claim 16]
`
`The manufacturing method for a semiconductor device according to Claim 15, wherein in
`the procedure for forming the mask member, the mask member is formed with the position
`thereof determined such that the exposing area of the mask member includes a portion of the gate
`protection film even when a mask alignment shift does not occur in the photolithography.
`
`[Claim 17]
`
`The manufacturing method for a semiconductor device according to Claim 15 or Claim
`16, wherein the following inequality is satisfied in the procedure for forming the contact hole:
`OE × a × (ER3/ER1) < c,
`wherein "a" denotes the thickness of the insulating film; "c" denotes the thickness of the
`gate protection film; "ER1" denotes the etching rate of the insulating film; "ER3" denotes the
`etching rate of the gate protection film; and "OE" denotes the over-etch ratio of the insulating
`film in the formation of the contact hole.
`
`[Detailed Description of the Invention]
`[0001]
`[Field of the Invention]
`
`The present invention relates to a semiconductor device including transistors and
`connection between the transistors for constituting an LSI with high integration and a decreased
`area.
`
`[0002]
`[Background of Related Art]
`
`In a semiconductor device mounting elements such as a MOSFET in an active area
`surrounded with an isolation, an insulating film is deposited on the active area, the isolation and
`a gate electrode, and a contact hole is formed by partly exposing the insulating film for
`connection between the active area and an interconnection member on a layer above the
`insulating film. This structure is known as a very common structure for the semiconductor
`device.
`
`[0003]
`FIG. 8 is a sectional view for showing the structure of a conventional semiconductor
`
`device. In particular, in semiconductor devices mounting elements such as a MOSFET that is
`highly integrated and has extremely minute measurements, much development is being pursued
`of a semiconductor device that utilizes a trench isolation structure as the isolation to avoid
`problems such as a so-called bird's beak and/or the like that occur in the isolation formed by the
`LOCOS method. FIG. 8 shows on example of the structure of a semiconductor device utilizing
`such a trench isolation structure.
`
`[0004]
`In this drawing, a reference numeral 1 denotes a silicon substrate, a reference numeral 2b
`
`denotes a field oxide film which is made of a silicon oxide film with a trench isolation structure
`and whose top surface is flattened so as to be at the same level as the top surface of the silicon
`substrate, a reference numeral 3 denotes a gate oxide film made of a silicon oxide film, a
`
`Page 7 of 30
`
`

`

`reference numeral 4a denotes a polysilicon electrode working as a gate electrode, a reference
`numeral 4b denotes a polysilicon interconnection formed simultaneously with the polysilicon
`electrode on top of the field oxide film 2b, a reference numeral 6 denotes a low-concentration
`source/drain region formed by doping the silicon substrate with an n-type impurity at a low
`concentration, a reference numeral 7a denotes an electrode sidewall, a reference numeral 7b
`denotes an interconnection sidewall, a reference numeral 8 denotes a high-concentration
`source/drain region formed by doping the silicon substrate with an n-type impurity at a high
`concentration, a reference numeral 12 denotes an insulating film made of a silicon oxide film,
`and a reference numeral 13 denotes a local interconnection made of a polysilicon film formed on
`the insulating film 12.
`
`[0005]
`
`The local interconnection 13 is also filled within a contact hole 14 formed in a part of the
`insulating film 12, so as to be contacted with the source/drain region in the active area through
`the contact hole 14. In this case, the contact hole 14 is formed apart from the field oxide film 2b
`by a predetermined distance. In other words, in the conventional layout rule for such a
`semiconductor device, there is a rule that the edge of a contact hole is previously located away
`from the boundary between the active area and the isolation region so as to prevent a part of the
`contact hole 14 from stretching over the field oxide film 2b even when a mask alignment shift is
`caused in photolithography (this distance between the contact hole and the isolation is designated
`as an alignment margin).
`
`[0006]
`[Problems Overcome by this Invention]
`
`However, in the structure of the conventional semiconductor device, the problem of
`damage occurring in the attempts to further improve the integration occurs for the following
`reason.
`
`[0007]
`A distance La between the polysilicon electrode 4a and the field oxide film 2b is
`
`estimated as an index of the integration. In order to prevent the contact hole 14 from interfering
`with the field oxide film 2b as described above, the distance La is required to be 1.2 µm, namely,
`the sum of the diameter of the contact hole 14, that is, 0.5 µm, the width of the electrode sidewall
`7a, that is, 0.1 µm, the alignment margin from the polysilicon electrode 4a, that is, 0.3 µm, and
`the alignment margin from the field oxide film 2b, that is, 0.3 µm. A contact hole has attained a
`more and more refined diameter with the development of processing techniques, and also a gate
`length has been decreased to as small as 0.3 µm or less. Still, the alignment margin in
`consideration of the mask alignment shift in the photolithography is required to be approximately
`0.3 µm. Accordingly, as the gate length and the contact hole diameter become more refined, the
`proportion of the alignment margin is increased. This alignment margin has become an obstacle
`to the high integration.
`
`[0008]
`Therefore, attempts have been made to form the contact hole 14 without considering the
`
`alignment margin in view of the alignment shift in the photolithography. Manufacturing
`procedures adopted in such a case will now be described by exemplifying an n-channel
`
`Page 8 of 30
`
`

`

`MOSFET referring to FIGS. 9(a) through 9(c).
`
`[0009]
`First, as is shown in FIG. 9(a), after forming a field oxide film 2b having the trench
`
`structure in a silicon substrate 1 doped with a p-type impurity (or p-type well), etch back or the
`like is conducted for flattening so as to place the surfaces of the field oxide film 2b and the
`silicon substrate 1 at the same level. In an active area surrounded with the field oxide film 2b, a
`gate oxide film 3, a polysilicon electrode 4a serving as a gate electrode, an electrode sidewall 7a,
`a low-concentration source/drain region 6 and a high-concentration source/drain region 8 are
`formed. On the field oxide film 2b are disposed a polysilicon interconnection 4b formed
`simultaneously with the polysilicon electrode 4a and an interconnection sidewall 7b. At this
`point, the top surface of the high-concentration source/drain region 8 in the active area is placed
`at the same level as the top surface of the field oxide film 2b. Then, an insulating film 12 of a
`silicon oxide film is formed on the entire top surface of the substrate.
`
`[0010]
`Next, as is shown in FIG. 9(b), a resist film 30 used as a mask for forming a contact hole
`
`is formed on the insulating film 12, and the contact hole 14 is formed by, for example, dry
`etching.
`
`[0011]
`Then, as is shown in FIG. 9(c), the resist film 30 is removed, and a polysilicon film is
`
`deposited on the insulating film 12 and within the contact hole 14. The polysilicon film is then
`made into a desired pattern, thereby forming a local interconnection 13.
`
`[0012]
`At this point, in the case where the alignment margin in view of the mask alignment shift
`
`in the formation of the contact hole 14 is not considered in estimating the distance La between
`the polysilicon electrode 4a and the field oxide film 2b, a part of the field oxide film 2b is
`included in the contact hole 14 when the exposing area of the resist film 30 is shifted toward the
`field oxide film 2b due to the mask alignment shift in the photolithography. Through over-etch
`in conducting the dry etching of the insulating film 12, although the high-concentration
`source/drain region 8 made of the silicon substrate is not largely etched because of its small
`etching rate, the part of the field oxide film 2b included in the contact hole 14 is selectively
`removed, resulting in forming a recess 40 in part of the contact hole 14. When the recess 40 in
`the contact hole 14 has a depth exceeding a given proportion to the depth of the high-
`concentration source/drain region 8, junction voltage resistance can be decreased and a junction
`leakage current can be increased because the concentration of the impurity in the high-
`concentration source/drain region 8 is low at that depth.
`
`[0013]
`In order to prevent these phenomena, it is necessary to provide a predetermined
`
`alignment margin as is shown in the structure of FIG. 8 so as to prevent the contact hole 14 from
`interfering with the field oxide film 2b even when the alignment shift is caused in the lithography.
`In this manner, in the conventional layout rule for a semiconductor device, an alignment margin
`in view of the mask alignment shift in the photolithography is unavoidably provided.
`
`Page 9 of 30
`
`

`

`
`[0014]
`Furthermore, a distance between the polysilicon electrode 4a and the contact hole 14 is
`
`also required to be provided with an alignment margin. Otherwise, the contact hole 14 can
`interfere with the polysilicon electrode 4a due to fluctuations caused in the manufacturing
`procedures, resulting in causing an electric short-circuit between an upper layer interconnection
`buried in the contact hole and the gate electrode.
`
`[0015]
`As described above, it is necessary to provide the contact hole 14 with margins for
`
`preventing the interference with other elements around the contact hole, which has become a
`large obstacle to the high integration of an LSI.
`
`[0016]
`In consideration of the foregoing, an object of the present invention is providing a
`
`semiconductor device with high integration and a decreased area, and a method of manufacturing
`the same, by devising a means of reducing the aliment shift when forming the contact hole for
`connecting the interconnection member on the top layer and the active area, while preventing
`decrease of the junction voltage resistance and increase in the junction leakage at the boundary
`between the active area and the isolation region.
`
`[0017]
`[Problem Resolution Means]
`
`In order to achieve this object, the resolution means devised by the present invention
`provides an isolation having a top surface which is higher in a stepwise manner than an active
`area surface.
`
`[0018]
`As noted in Claim 1, a basic configuration of the semiconductor device according to the
`
`present invention includes: a semiconductor substrate; an isolation formed such that the top
`surface is higher in a stepwise manner than the surface of the semiconductor substrate; a plurality
`of active areas formed by introducing impurities in the semiconductor substrate surrounded by
`the isolation; an insulating film formed so as to stretch over the active areas and the isolation; a
`contact hole formed so as to expose a part of the insulating film, at least a portion of the contact
`hole reaching to the surface of the active areas; and an upper interconnection formed above the
`insulating film and in the contact hole, the upper interconnection connecting to the active areas.
`
`[0019]
`As noted in Claim 2, in the basic configuration, through dispersion in manufacturing
`
`procedures of the semiconductor device, at least some of the contact holes out of the plurality of
`contact holes are formed so as to stretch from the surface of the active areas to the isolation.
`
`[0020]
`Owing to the configuration of Claim 1 or Claim 2, in the case where a part of or all the
`
`holes are formed so as to stretch from the active areas to the isolation due to mask alignment
`shift in photolithography, a part of the isolation is removed by over-etch for ensuring the
`
`Page 10 of 30
`
`

`

`formation of the holes. In such a case, the depth of the holes formed in the isolation is small in
`the boundary between a portion of the contact hole and the active area because of the level
`difference between the top surface of the isolation and the surface of the active area.
`Accordingly, degradation of the junction voltage resistance and increase of the junction leakage
`current can be suppressed. Therefore, there is no need to provide a portion of the active area
`where each contact hole is formed with an alignment margin for avoiding the interference with
`the isolation caused by the mask alignment shift. Thus, the area of the active area can be
`decreased, resulting in improving the integration of the semiconductor device.
`
`[0021]
`As noted in Claim 3, in the basic configuration, an interconnection member can also be
`
`provided, the interconnection member formed such that at least a portion thereof is positioned on
`the isolation; wherein the contact holes are formed so as to stretch from the surface of the active
`areas to the interconnection member near the active areas; and the upper interconnection is also
`connected to an interconnection member on the isolation.
`
`[0022]
`Owing to this configuration, in the case where the upper interconnection works as a local
`
`interconnection for connecting the interconnection member on the isolation with the active area,
`there is no need to separately form contact holes in the insulating film on the interconnection
`member and the insulating film on the active area. In addition, there is no need to separately
`provide alignment margins from the boundary between the active area and the isolation.
`Accordingly, the area of the isolation can also be decreased, resulting in greatly improving the
`integration of the semiconductor device.
`
`[0023]
`As noted in Claim 4, in the configuration of each of the Claims, an isolation sidewall
`
`made of an insulating material and formed on a side surface of a step portion from the surface of
`the active areas reaching to the top surface of the isolation can also be provided, wherein the
`contact holes are formed so as to stretch over the isolation sidewall.
`
`[0024]
`Owing to this structure, in addition to the effects of the above Claims, the abrupt level
`
`difference between the surfaces of the isolation and the active area can be released by the
`presence of the isolation sidewall. Therefore, a residue is scarcely generated in patterning the
`interconnection members, and an upper interconnection is prevented from being disconnected
`and increasing in its resistance.
`
`[0025]
`
`As noted in Claim 5, in the basic configuration, the dimensions and materials of
`
`the respective components are preferably determined so as to satisfy the inequality:
`OE × a × (ER2/ER1) ≥ b + D × (2/10),
`wherein "a" denotes the thickness of the insulating film; "b" denotes the level difference
`between the surface of the field oxide film and the surface of the active area; "ER1" denotes the
`etching rate of the insulating film; "ER2" denotes the etching rate of the field oxide film; "D"
`
`Page 11 of 30
`
`

`

`denotes the depth of an impurity diffused layer in the active area; and "OE" denotes the over-etch
`ratio of the insulating film in the formation of the contact hole.
`
`[0026]
`Owing to this structure, even if a part of the isolation included in the hole because of the
`
`mask alignment shift is removed, the bottom of the removed region is not next to the area of the
`active area with low impurity concentration. Accordingly, degradation of the junction voltage
`resistance and increase of the junction leakage current can be definitely prevented.
`
`[0027]
`As noted in Claim 6, in the basic configuration, a FET can be further provided, the FET
`
`having a gate electrode formed on top of the active area, a source/drain region formed in the
`active area positioned on both side surfaces of the gate electrode, and a gate protection film
`formed on top of the gate electrode; and the contact holes can be formed so as to stretch from the
`source/drain region to at least a portion of the gate protection film.
`
`[0028]
`Owing to this structure, a part of the gate protection film included in the contact hole is
`
`removed by the over-etch in the formation of the holes. However, the gate electrode is protected
`by the gate protection film, and hence, electrical short circuit between the gate electrode and the
`interconnection member can be prevented. Accordingly, there is no need to provide an
`alignment margin from the gate electrode in the area where each contact hole is formed, resulting
`in further improving the integration.
`
`[0029]
`As noted in Claim 7, in the configuration according to Claim 4, the configuration can be
`
`such that a FET is further provided, the FET having a gate electrode formed on the active area, a
`source/drain region formed in the semiconductor substrate positioned to the side of the gate
`electrode, a gate protection film formed on top of the gate electrode, and an electrode sidewall
`formed on both side surfaces of the gate electrode; wherein the isolation sidewall is formed at the
`same time as the electrode sidewall.
`
`[0030]
`Owing to this structure, a FET having the LDD structure suitable for refinement can be
`
`integrated with high density in the semiconductor device.
`
`As noted in Claim 8, in the configuration of Claim 6 or Claim 7, the dimensions and
`materials of the respective components are preferably determined so as to satisfy the inequality:
`OE × a × (ER3/ER1) < c,
`wherein "a" denotes the thickness of the insulating film; "c" denotes the thickness of the
`gate protection film; "ER1" denotes the etching rate of the insulating film; "ER3" denotes the
`etching rate of the gate protection film; and "OE" denotes the over-etch ratio of the insulating
`film in the formation of the contact hole.
`
`[0031]
`Owing to this structure, even when the contact hole is formed stretching to a position
`
`interfering with the gate electrode, by over-etch in the formation of the contact hole, the contact
`
`Page 12 of 30
`
`

`

`hole is definitely prevented from reaching the gate electrode, and an electric short-circuit
`between the active area and the gate electrode is definitely prevented.
`
`[0032]
`As noted in Claim 9, in the basic configuration, the angle of inclination of the side
`
`surface of the step portion from the surface of the active area to the surface of the isolation to the
`semiconductor substrate surface is preferably at least 70 degrees.
`
`[0033]
`Owing to this structure, when the contact hole interferences with the isolation, by over-
`
`etch in the formation of the contact holes, removal of part of the isolation included in the contact
`hole up to the part of the active area with low concentration of impurities can be definitely
`prevented.
`
`[0034]
`In addition, as noted in Claim 10, a manufacturing method for the basic semiconductor
`
`device of the present invention includes: a procedure for forming, on a semiconductor substrate,
`an isolation having a top surface that is higher in a stepwise manner than the surface of the
`semiconductor substrate; a procedure for introducing impurities in a plurality of active areas
`surrounded by the isolation in the semiconductor substrate; a procedure for depositing an
`insulating film on the active areas and the isolation; a procedure for forming a mask member
`having an exposing area for forming contact holes to the active areas, on the insulating film; a
`procedure for removing the insulating film in the exposing area of the mask member through
`etching, and furthermore accomplished a prescribed over-etch, thereby forming a contact hole;
`and a procedure for forming an upper interconnection connecting to the active areas above the
`insulating film and in the contact hole; wherein in the procedure for forming the mask member, a
`margin is not provided for ensuring that the exposing area of the mask member does not include
`the isolation when a mask alignment shift occurs in the photolithography.
`
`[0035]
`In adopting this method, even when a part of the isolation is removed by over-etch in the
`
`formation of the holes, the depth to which a portion of the contact hole penetrates inside the
`isolation is reduced because of the level difference between the isolation and the active area.
`Accordingly, the degradation of the junction voltage resistance and the increase of the junction
`leakage current can be suppressed in the manufactured semiconductor device. On the other hand,
`the area of the active area can be reduced because an alignment margin for the isolation is not
`provided, so integration can be increased in the manufactured semiconductor device.
`
`[0036]
`
`As noted in Claim 11, in the manufacturing method of the basic semiconductor device,
`preferably the inequality:
`OE × a × (ER2/ER1) ≥ b + D × (2/10),
`is satisfied, wherein "a" denotes the thickness of the insulating film; "b" denotes the level
`difference between the surface of the field oxide film and the surface of the active area; "ER1"
`denotes the etching rate of the insulating film; "ER2" denotes the etching rate of the field oxide
`
`Page 13 of 30
`
`

`

`film; "D" denotes the depth of an impurity diffused layer in the active area; and "OE" denotes the
`over-etch ratio of the insulating film in the formation of the contact hole.
`
`[0037]
`In adopting this method, even when a part of the isolation included in the contact hole is
`
`removed by over-etch in the formatio