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`Global Foundaries US v. Godo Kaisha
`Global Ex. 1012
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`5,976,939
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`5,976,939
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`N0v.2, 1999
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`5,976,939
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`41
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`Mlfhi
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`Page 4 of 8
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`U.S. Patent
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`Nov. 2, 1999
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`Sheet 4 of 4
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`5,976,939
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`@
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`Page 5 of 8
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`5,976,939
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`1
`LOW DAMAGE DOPING TECHNIQUE FOR
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`SELF-ALIGNED SOURCE AND DRAIN
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`REGIONS
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
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`The invention relates to the field of forming self-aligned
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`source and drain regions for field-effect transistors.
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`2. Prior Art
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`Typically during the formation of a field-effect transistor,
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`ion implantation is used to align a source and drain region
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`with a gate (and/or with gate spacers in some processes). The
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`ion implantation damages the crystalline structure of the
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`silicon substrate necessitating thermal annealing. During the
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`annealing the implanted dopant diffuses thereby deepening
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`the source and drain regions. These deeper regions make it
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`diflicult to control the adverse effects of short channels.
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`Ideally, to control the short channel effects where effective
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`channel lengths are in the order of 0.1 um or less, the source
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`and drain regions should be extremely shallow and heavily
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`doped (e.g., 0.05 to 0.1 um versus 0.2 to 0.4 um for ion
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`implanted regions).
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`Scaling implanted p+ junctions is particularly difficult
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`since the light boron (B11) ions channel during implantation
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`causing point defects. These point defects significantly
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`increase the diffusion of the boron atoms (up to 1000 times)
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`during subsequent thermal annealing. Thus, even for light
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`ions, such as B11, and low energy implants, the implant
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`damage results in enhanced diffusion.
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`One solution to this problem is to make amorphous the
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`silicon substrate before the B11 implant since this reduces
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`channeling. However, the net result is not a significantly
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`shallow profile since the damage to the silicon lattice leads
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`to enhance diffusion of the implanted B11.
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`Another technique for solving this problem is to diffuse
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`the portion of the source and drain regions adjacent to the
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`gate (tip or tip region) from doped spacers and to form the
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`more heavily doped main portions of the source and drain
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`regions by ion implantation. This provides some advantage
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`over the ion implantation of both the tip region and main
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`portion of the source and drain regions but implant damage
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`from the source/drain implant still affects the depth of the
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`diffused tip region resulting in degraded short channel
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`effects. Short channel effects are discussed in numerous
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`publications such as Silicon Processing for the VLSI Era,
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`Vol. 2, by S. Wolf, published by Lattice press, see Section
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`5.5, beginning at page 338.
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`As will be seen, the present invention permits the simul-
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`taneous doping of an ultra shallow lightly doped source and
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`drain tip regions, main portions of the source and drain
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`regions and doping of the polysilicon gate without
`ion
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`implantation.
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`SUMMARY OF THE INVENTION
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`A method is described for fabricating field-effect transis-
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`tors on a substrate where the source and drain regions are
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`formed in alignment with a gate. A source of dopant is used
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`a more lightly doped region which is formed
`having
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`directly adjacent to the gate and (ii) a more heavily doped
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`region spaced apart from the gate. This dopant source is
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`formed on the surface of the substrate. The dopant is diffused
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`from the source of dopant in a heating step simultaneously
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`forming both the lightly doped source and drain tip region
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`and the main portion of the source and drain regions.
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`Page 6 of 8
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`2
`In one embodiment boron is diffused from two different
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`layers of borosilicate glass (BSG). Spacers are formed
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`adjacent to the gate by anisotropically etching a silicon
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`nitride layer which overlies a 2% BSG layer. Then a 6%
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`BSG layer is formed over the spacers and 2% BSG layer to
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`supply the dopant for the more heavily doped main portion
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`of the source and drain regions. Rapid thermal processing is
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`used to diffuse the dopant into the substrate from both BSG
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`layers.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIG. 1 is a cross sectional elevation View of a section of
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`a substrate showing an n-well isolated from a p-well. Poly-
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`silicon gates and a first glass layer are also shown.
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`FIG. 2 illustrates the substrate of FIG. 1 after a first
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`photoresist layer has been masked and etching, and during
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`an ion implantation step used to form the tip regions for the
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`n-channel transistor.
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`FIG. 3 illustrates the substrate of FIG. 2 after the forma-
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`tion of a TEOS layer and a silicon nitride layer.
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`FIG. 4 illustrates the substrate of FIG. 3 after the silicon
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`nitride layer has been anisotropically etched to form spacers
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`and after the substrate has been covered with a second glass
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`layer.
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`FIG. 5 illustrates the substrate of FIG. 4 after the masking
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`and etching of a photoresist layer and during an ion implan-
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`tation step used to form the main portion of the source and
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`drain regions for the n-channel transistor.
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`FIG. 6 illustrates the substrate of FIG. 5 after diffusion of
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`the boron dopant from the glass layers to form the source
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`and drain regions for the p-channel transistor.
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`FIG. 7 illustrates the substrate of FIG. 4 for an alternate
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`embodiment where the n-type dopant is diffused from a glass
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`layer.
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`DETAILED DESCRIPTION OF THE
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`INVENTION
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`A method and structure for forming low damage, shallow
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`source and drain regions in alignment with a gate for a
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`field-effect
`transistor
`is described.
`In the following
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`description, numerous well-known steps such as masking
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`and etching steps are not discussed in detail in order not to
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`obscure the present invention. In other instances, specific
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`details are set forth such as specific boron dopant concen-
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`trations in order to provide a thorough understanding of the
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`present invention.
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`The various layers of materials shown in the drawings are
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`not shown to scale. Rather,
`the layers have been made
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`clearly visible so that the present invention can be better
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`understood from the drawings. Additionally, only a portion
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`of a substrate showing a single p-channel and n-channel
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`transistor is illustrated. It will be appreciated that in practice
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`the invention is used to fabricate an entire integrated circuit.
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`While the present invention is not limited to any particular
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`geometry in one embodiment, it is used for the fabrication
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`of transistors having a channel length of approximately 0.1
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`um with transistors that operate from a 1.8 volt supply.
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`Referring now to FIG. 1, a section of a monocrystalline
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`silicon substrate 15 is illustrated having a well doped within
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`an n-type conductivity dopant (n well 21) and a region or
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`well doped with a p-type conductivity dopant (p well). As
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`will be seen, it is not important to the present invention
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`whether both n and p wells are used. For instance, an n well
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`may be used for p-channel transistors with the n-channel
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`transistors being formed directly in a p-type substrate.
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`5,976,939
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`3
`The n and p well of FIG. 1 are isolated from one another
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`by a recessed isolation region specifically,
`trench 10.
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`Additionally, within the n well 21 there are other isolation
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`trenches 12 for isolating from one another p-channel tran-
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`sistors formed within the n well. Likewise, there are isola-
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`tion trenches 13 formed within the p well
`to isolate
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`n-channel transistors formed in the p well from one another.
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`The isolation trenches may be formed using well-known
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`technology. Other isolation technologies such as local oxi-
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`dation of silicon (LOCOS) may be used instead of trenches
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`A gate insulative layer (such as a high quality, thermally
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`grown oxide to insulate the gate from the substrate) is
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`formed over the substrate. Following this, a polycrystalline
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`silicon (polysilicon) layer is deposited and the gates for the
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`field-effect transistors are fabricated using ordinary photo-
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`lithographic and etching techniques. Two such gates insu-
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`lated from the substrate are shown in FIG. 1. Gate 11,
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`formed above the n well, as will be seen, is used for a
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`p-channel transistor; the other gate 14, formed above the p
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`well, is used for an n-channel transistor, Numerous steps
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`typically used before the fabrication of the gates are not
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`illustrated, such as cleaning steps, ion implantation steps to
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`adjust threshold voltage, etc.
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`Following the formation of the gates 11 and 14 a confor-
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`mal layer 16 of borosilicate glass (BSG) is deposited over
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`the entire substrate. This layer may be 100 A-300 A thick.
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`The layer in one embodiment has a 2% functional descrip-
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`tion concentration of a p-type conductivity dopant (boron).
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`This layer is referred to hereinafter as 2% BSG layer. TEOS
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`or silane based chemistry is used to deposit the 2% BSG
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`layer. This layer is formed in one embodiment at a tempera-
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`ture of 400—600° C.
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`In the embodiment of the present invention described in
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`this application, the p-channel transistor is formed using the
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`present invention while the n-channel transistor is formed
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`using well-known ion implantation. The formation of the
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`n-channel transistor is described nonetheless since the mask-
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`ing steps for the n-type implants are used to diffuse the
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`p-type dopant sources.
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`FIG. 2 illustrates the first of two ion implantation step
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`used in the formation of the n-channel transistor. First, a
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`photoresist layer 17 is formed over the substrate 15. This
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`layer is masked exposed and developed by well-known
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`techniques to reveal the substrate regions where the source
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`and drains are formed for the n-channel transistors and
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`additionally, regions where an n-type dopant is used for well
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`tap 20. This is shown in FIG. 2 where the photoresist
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`members 17 protect predetermined areas of the substrate
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`while leaving exposed other areas. Next, the exposed por-
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`tions of glass layer 16 are etched in alignment with the
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`photoresist members 17. This etching step uses a hydrogen
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`based solution. The substrate is then subjected
`fluoride
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`to ion implantation of an arsenic dopant as shown by the
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`arrows 18. This forms the regions 19 in alignment with the
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`gate 14 and a region 20 between the trenches 12. This
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`arsenic doping implant is relatively light and is used for
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`forming the tip regions of the source and drain regions for
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`the n-channel transistor. The main portions of the source and
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`drain regions for this n-channel transistor are subsequently
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`formed with the second ion implantation step.
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`Next, as shown in FIG. 3, a conformal layer of undoped
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`silicon dioxide is formed from tetraethyl orthosilicate
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`(TEOS) by low pressure chemical vapor deposition layer 30
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`or other undoped LPCVD oxide film is formed over the
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`substrate using well-known processing. This layer provides
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`an etchant stop for the spacers formed for the n-channel
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`transistor. The TEOS layer may be 50 A-300 A thick.
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`Page 7 of 8
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`4
`Now, as shown in FIG. 3 a conformal layer 31 of silicon
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`nitride is formed over the TEOS layer 30. (An oxide layer
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`may be used instead of the silicon nitride layer.) This silicon
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`nitride layer is approximately 800 A thick in one embodi-
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`ment. Well-known anisotropic etching is used to etch the
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`silicon nitride layer to form spacers 31 shown on opposite
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`sides of gates 11 and 14 of FIG. 4. The TEOS layer acts as
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`an etchant step to protect the silicon. The TEOS and BSG
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`regions not covered by the nitride spacers are also etched
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`away. A wet etchant may be used for this purpose.
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`Following this, a second layer 35 of BSG is formed over
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`the substrate. This time, however,
`the layer has a 6%
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`concentration of boron (6% BSG). This layer in one embodi-
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`ment is approximately 200 A-600 A thick and is deposited
`using a TEOS or silane based chemistries at a temperature
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`of 400-600° C. in one embodiment.
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`Better results may be achieved for some processes if a
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`relatively thin cap layer (e.g., 100
`of undoped glass or
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`silicon nitride (not shown) is formed over the 6% BSG layer.
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`This undoped layer protects the 6% BSG from a subsequent
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`photoresist layer formed over the glass and assures that
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`dopant will not diffuse upward. This layer also prevents
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`water from the photoresist
`layer from reacting with the
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`boron dopant.
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`As shown in FIG. 5, following the formation of the 6%
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`BSG layer 35, a photoresist layer 40 is masked, exposed and
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`developed to expose generally the same areas that were
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`exposed in FIG. 2. Specifically, gate 12, the areas adjacent
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`to gate 12 (source and drain regions) and region 20; the
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`remainder of the substrate shown in FIG. 5 is protected by
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`the photoresist members 40.
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`The cap layer over the glass layer 35 (if used) and the 6%
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`BSG layer 35 are then etched in alignment with the photo-
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`resist members 40. This is done by HF based chemistry.
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`The second n-type ion implantation step is now used to
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`implant the arsenic dopant into the regions of the substrate
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`not protected by the photoresist layer 40, spacers 31, or gate
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`12. The arrows 41 illustrate the implantation of this arsenic
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`dopant. This dopant is used to form the main portions N+ of
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`the 45 source and drain regions for the n-channel transistors.
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`Note that since the spacers 31 are in place, the dopant is
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`implanted in alignment with the spacers and not in align-
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`ment with the gate.
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`is used. The
`Following this, a driving (heating) step,
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`p-type dopant from the 2% BSG and 6% BSG layers is
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`simultaneously diffused into the substrate to form both the
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`tip regions, main source and drain regions, and doping of the
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`gate 11 for the p-channel transistor. The tip region has a
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`depth of 300-700 A which the main portion of the p-type
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`region has depth of 1000-2500
`Additionally, the p-type
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`dopant from the BSG layers forms a well tap between the
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`isolation trenches 13. In one embodiment, this drive step
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`employs rapid thermal processing. Specifically, driving at
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`1000° C. to 1040° C. for 10-20 seconds with ramping up to
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`and down from this temperature at 70° C. per second. A
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`standard Halogen lamp based rapid thermal reactor is used.
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`Well-known processing may be used to complete the
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`fabrication of the integrated circuit shown in FIG. 6. The
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`glass layers 16 and 35 to the extent remaining as shown in
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`FIG. 6 may remain in place for the remainder of the
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`processing and may stay in the completed integrated circuit.
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`Glass layer 35 may be removed to facilitate a subsequent
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`selective TiSi or CoSi2 layer on gates 11 and 12 and regions
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`41 and 45.
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`The result of the processing described above is a source
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`and drain region for the p-type transistor having a tip region
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`Page 7 of 8
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`

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`6
`FIG. 7 illustrates alternate processing where a single glass
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`layer doped with an n-type dopant is used to form the
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`source/drain for the n-channel transistor. For this processing,
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`following the etching of the glass layer 35, an additional
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`glass layer 50 doped with the n-type dopant (e.g., 6% PSG)
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`is formed as shown in FIG. 7. (The glass layer 50 is formed
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`over the structure shown in FIG. 5 without the photoresist
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`layer 40). During the driving step used to dope the source/
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`drain and gate of the p-channel transistor the n-channel
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`transistor is simultaneously formed. Dopant from layer 50
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`forms the main source/drain regions of the n-channel tran-
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`sistor. Note the dopant from layer 50 does not diffuse into the
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`layer 35. This n-type dopant also diffused under the spacers
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`of gate 12 to form more lightly doped tip regions for the
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`n-channel transistor. At the same time, the gate 12 is doped
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`with the n-type dopant from layer 50.
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`With similar processing note that the glass layer 16 need
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`not be used to form the p-channel transistor. That is, as in the
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`case for the n-channel transistor described in conjunction
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`with FIG. 7, the p-type dopant may be driving under the
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`spacer of gate 11 from the 6% glass layer to form the tip
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`source/drain regions for the p-channel transistor. This per-
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`mits the doping of source/drain for both n-channel and
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`p-channel transistors with a single masking step.
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`Thus, an improved process and structure for providing
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`doping for a source and drain region has been described
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`which employs two layers with different doping concentra-
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`tions to permit simultaneously doping of a lightly doped tip
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`regions and more heavily doped main portions of source and
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`drain regions. Ultra shallow source and drain regions are
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`obtained with improved short channel properties.
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`We claim:
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`1. A method for forming a field-effect transistor on a
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`substrate region doped with a first conductivity type dopant
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`comprising the steps of:
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`forming a gate insulated from the substrate;
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`forming a glass layer containing a second conductivity
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`type dopant over the substrate including over the gate;
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`forming a silicon dioxide layer over the first glass layer;
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`forming a silicon nitride layer over the layer of silicon
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`dioxide;
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`forming spacers on opposite sides of the gate from the
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`silicon nitride layer, silicon dioxide layer and glass
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`layer.
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`2. The method defined by claim 1 including forming the
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`silicon dioxide layer from tetraethyl orthosilicate.
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`3. The method defined by claim 1 wherein the glass layer
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`is borosilicate.
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`4. In the fabrication of a field-effect transistor where
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`spacers are formed in part from a doped glass and an
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`overlying silicon nitride layer and where dopant from the
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`glass doped is diffused into the substrate to form extension
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`source and drain regions, an improvement wherein a layer of
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`silicon dioxide is formed from tetraethyl orthosilicate
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`between the doped glass layer and the silicon nitride layer.
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`*
`*
`*
`*
`*
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`5,976,939
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`5
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`40 adjacent to the gate (from the dopant diffused into the
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`substrate from the 2% BSG layer 16) and a more highly
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`doped main portion of the source and drain regions 41
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`spaced apart from the gate (from the dopant diffused from
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`the 6% BSG layer 35). For the described embodiment the
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`p-type tip region has a dopant concentration of 1—5><1019
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`cm‘3 while the main portion of the source and drain region
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`has a dopant concentration of 2—5><102O cm‘3. This results
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`directly from the 2% and 6% BSG. Other concentrations of
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`dopants in the glass may be used. For example, layer 16 may
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`have a dopant concentration between 1 to 4% and layer 35
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`may have a dopant concentration between 6 to 12%.
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`The ultra-shallow p+ regions formed with the described
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`invention, as illustrated in the figures has shown to provide
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`substantial improvement over prior art fabrication where the
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`p-channel source and drain regions are formed with a tip
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`implant in alignment with the gate followed by implantation
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`of the main portion of source and drain regions in alignment
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`with a spacer. Transistors made with the low damage doped
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`source and drain regions of the present
`invention have
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`shown in one benchmark to have a 25% improved gate delay
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`when operated at 1.8V even when compared to a prior art
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`transistor operated at 2.5V.
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`With the present invention as described above, two mask-
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`ing steps are saved when compared to the prior art technique
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`of forming the p-channel device through two implantation
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`steps, one for the tip implant and the other for the main
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`portion of the source and drain regions. Note that with the
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`present invention, the two masking steps used to expose
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`those areas of the substrate which are doped with the n-type
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`dopant for the n-channel transistor source and drain region
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`are also used to etch the BSG layers 16 and 35. In the prior
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`art, two additional masking steps are needed to protect the
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`n-channel device when the p-channel device are implanted.
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`As shown in FIG. 5,
`the glass layer 35 is etched in
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`alignment with the photoresist members 40 prior to the
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`implantation illustrated by lines 41. It may be desirable in
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`some processes to leave the 6% BSG layer in place. The
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`second ion implantation step used to form the N+ source and
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`drain regions for the n-channel
`transistor is then done
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`through this glass layer. The counter doping effect of the
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`boron dopant in the n-type source and drain regions in
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`general will not present a problem. The arsenic dopant level
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`of the source and drain region for the n-channel transistor is
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`high and consequently, not significantly affected by the
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`introduction of the boron atoms. Leaving layer 35 in place
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`saves the step used to remove this layer from the areas not
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`protected by the photoresist members.
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`While in the above description, the p-channel transistor is
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`shown fabricated with the present
`invention and the
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`n-channel
`transistor is fabricated using conventional ion
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`implantation, the n-channel transistor may likewise be fab-
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`ricated using one or two layers of glass phosphorous or
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`arsenic doped glass.
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`While in the above-described process the dopant for the
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`p-channel transistor was obtained from a glass, specifically
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`BSG, other materials may be used as a source of the dopant
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`such as polysilicon or germanium-silicon.
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`Page 8 of 8
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`Page 8 of 8
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