US005920790A
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`5,920,790
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`Jul. 6, 1999
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`[11] Patent Number:
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`[45] Date of Patent:
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`OTHER PUBLICATIONS
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`B. Luther et al., “Planar Copper—Polyimide Back End of the
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`Line Interconnections for ULSI Devices", Jun. 8-9, 1993
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`VMIC Conference, Catalog No. 93ISMIC—l02, pp. 15—21.
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`P"i”7””y E"7‘1’77":’l“V—J0hH F Niebllng
`Assistant Examiner—DaVid A. Zarneke
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`[57]
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`ABSTRACT
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`that
`forming semiconductor device (1)
`A method for
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`inelndee Pnwiding a substrate (10) having a inetn1inteie0n-
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`nect (12), depositing a Via interlevel dielectric (ILD) layer
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`(20).0VCI l.l'lC .SLlbSl.I"‘cll.C
`‘clfld lhti 1HCl.‘cll lHl.CICOHHt3Cl
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`etching the Via ILD layer (20) to form a Via (30) over the
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`to form a trench (40), the trench (40)
`trench ILD. layer
`being contiguous with the Via (12), and depositing a metal
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`(44) so as to fill the Via (30) and the trench (40), and provide
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`electrical connection with the metal interconnect (12).
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`26 Claims, 4 Drawing Sheets
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`References Cited
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`U.S. PATENT DOCUMENTS
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`10/1987 Chow et a1.
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`12/1988 Chow et al.
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`7/1990 Beyer et al.
`................. ..
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`4’702;792
`4,789,648
`4,944,836
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`..
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`Z.MM
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`Vk\j; M.
`EOE?/fl/A5 ”
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`‘j 16
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`United States Patent
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`Wetzel et al.
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`[19]
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`[54 METHOD OF FORMINGA
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`SEMICONDUCTOR DEVICE HAVING DUAL
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`INLAID STRUCTURE
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`[75
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`Inventors: Jeifrey T- Wetzel; John J- Stankus,
`both of Austin, Tex.
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`[73 Assignee: Motorola, Inc., Schaumburg, Ill.
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`Appl. No.2 08/921,293
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`Film:
`Aug‘ 29’ 1997
`Int. c1.e
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`U_S_ CL
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`H01L 21/4763
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`438/618; 438/622; 438/623;
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`438/618’ 622,
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`Field of Search
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`TSMC Exhibit 1019
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`Page 1 of 9
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`U.S. Patent
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`Jul. 6, 1999
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`Sheet 1 of4
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`FIG.J
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`U.S. Patent
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`Jul. 6, 1999
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`Sheet 2 of4
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`U.S. Patent
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`Jul. 6, 1999
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`Sheet 3 of4
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`U.S. Patent
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`‘Aif
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`__k —
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`Page 5 of 9
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`5,920,790
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`1
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`METHOD OF FORMING A
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`SEMICONDUCTOR DEVICE HAVING DUAL
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`INLAID STRUCTURE
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`TECHNICAL FIELD OF THE INVENTION
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`This invention relates in general to a method for forming
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`semiconductor devices, and more particularly, to a method
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`for forming multilevel metal (MLM) interconnects in semi-
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`conductor devices.
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`BACKGROUND OF THE INVENTION
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`The present invention is directed to a method of forming
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`a dual
`inlaid interconnect structure in semiconductor
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`devices, including microprocessors, DSPs, microcontrollers,
`FSRAMS, etc. Dual inlaid interconnect techniques are gen-
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`erally known in the art, and have been found to be advan-
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`tageous by permitting simultaneous formation of
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`interconnected, metal-filled trenches and vias. However,
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`numerous problems exist with current dual
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`technology, particularly with respect to use of such technol-
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`ogy with so-called low-k dielectrics, materials having a
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`dielectric constant below 3.5, more preferably, below 3.0. In
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`connection with prior art techniques of forming dual inlaid
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`structures, reference is made to FIG. 9.
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`FIG. 9 depicts a stage in the method of forming a dual
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`inlaid structure at a step where via opening 400a is formed
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`in trench interlevel dielectric (ILD)
`layer 320. More
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`particularly, FIG. 9 depicts a structure having substrate 100,
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`formed of a low-k material or a conventional oxide material,
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`in which metallic interconnects 120 are formed. As known
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`in the art, metallic interconnects can be formed of copper,
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`aluminum, gold, silver, etc. Metal interconnects 120 are
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`provided for lower level electrical connection to active
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`devices formed along the active region of the semiconductor
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`substrate (not shown). An etch stop layer 160 is deposited
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`over substrate 100, including metal interconnects 120. Etch
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`stop layer 160 is generally formed of a nitride material, such
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`as silicon nitride, silicon oxynitride, or a composite thereof.
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`Conventionally, the etch stop layer is formed by a plasma
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`enhanced chemical vapor deposition process. Then, a via
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`ILD layer 200 is deposited on the etch stop layer 160. Via
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`ILD layer 200 is generally formed of an oxide, such as
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`silicon dioxide formed by PECVD. Further, etch stop layer
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`220 is formed on via level dielectric 200, in a similar fashion
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`to etch stop layer 160 formed on substrate 100. Trench level
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`dielectric 320 is then formed on etch stop layer 220, in a
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`similar fashion to the via ILD layer 200.
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`After completing the dual dielectric layer structure includ-
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`ing dielectric layers 200 and 320, etching is executed to form
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`a lower via 400 and a trench 500, both of which are
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`subsequently filled with a conductive metal. Particularly, a
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`hard mask 340 is formed on trench level dielectric 320. The
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`hard mask 340 is be formed in a similar fashion to the etch
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`stop layers 160 and 220. Aphotoresist 360 is then formed on
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`hard mask 340. The materials of photoresist 360 are par-
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`ticularly chosen depending upon the particular wavelength
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`utilized for exposure, such as I-line or DUV (deep ultra-
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`violet) processing. Such photoresist materials are generally
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`spun-on and are readily commercially available.
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`FIG. 9 particularly shows a first step for forming what is
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`known in the art as the conventional via first-trench last
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`(VFTL) process, wherein via 400 is formed in the via ILD
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`layer 200 prior to trench 500 within trench ILD layer 320.
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`Here, after exposure and developing of photoresist 360, hard
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`mask 340 is etched, followed by subsequent etching of via
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`opening 400a in the trench ILD layer 320. Thereafter,
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`additional etching steps are carried out to form via 400 and
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`trench 500. Via 400 and trench 500 are formed by any one
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`of several conventional techniques. For example, etch stop
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`layer 220 is etched, followed by partial etching, such as to
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`level 400b, to leave a dielectric material over etch stop layer
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`160. At this point, photoresist 360 is removed by the etching
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`process, and a new photoresist layer (not shown) is formed
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`to define trench 500. During etching to define trench 500, the
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`remaining portion of dielectric material below level 400b is
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`simultaneously removed.
`A final etching step is be executed to remove a portion of
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`etch stop layer 160 superposed on metal interconnect 120,
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`followed by metal fill to fill via 400 and trench 500 and
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`provide electrical connection to metal
`interconnect 120.
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`While not shown in the plane of FIG. 9, trench 500, after
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`metal fill, forms a line that extends into and out of the plane
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`to provide electrical contact to the other in trenches and vias.
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`The vias, on the other hand, only provide electrical connec-
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`tion vertically through the structure, to the contacts 120.
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`Accordingly, the vias generally extend perpendicularly with
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`respect to the plane of FIG. 9 only a short distance. For
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`example, via 400 may be round or square, the width of the
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`via 400 shown in FIG. 9 defining the diameter or side
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`respectively.
`The process as described above in connection with FIG.
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`9 is known in the art, particularly with respect to via and
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`trench ILD layers formed of an oxide dielectric material.
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`However,
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`inventors have recognized several
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`problems with this process when applied to low-k dielectrics
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`for the via and trench ILD layers. Particularly, it has been
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`observed that the materials used for forming the photoresist
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`360, as well as the developer for such materials, interact with
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`the exposed outer walls within via opening 400a, along zone
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`320a. In particular,
`it has been observed that the low-k
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`dielectric material tends to swell due to absorption of solvent
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`used in connection with the photoresist and/or the developer
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`used for forming trench 500. Additionally, unwanted chemi-
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`cal reactions take place between the low-k dielectric mate-
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`rial along zone 320a and the photoresist, the solvent used
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`with the photoresist, and/or the developer used for devel-
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`oping the photoresist. As is evident,
`the swelling of the
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`low-k dielectric material along via opening 400a can be
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`deleterious, causing problems with control of critical dimen-
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`sions (CD) and ILD stack integrity, resulting in cracking of
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`the hardmask 340,
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`the unwanted
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`chemical reactions may adversely affect the photo-active
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`properties of the photoresist layer for forming trench 500, or
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`the dielectric properties along zone 320a.
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`Further, multilevel metal (MLM) interconnects may also
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`be made by other techniques, such as utilizing a single inlaid
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`process. In this known process, a single inlaid of metal trace
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`is deposited in the via ILD layer, prior to formation of the
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`trench ILD layer thereon. Accordingly, the metal deposited
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`in the via requires CMP (chemical mechanical polishing)
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`prior to formation of subsequent layers thereon, including
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`appropriate etch stop layers and the trench ILD layer. Not
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`only does this process require multiple steps of depositing
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`metal to fill the vias and trenches, but also multiple CMP
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`steps, which are difficult to regulate and clean-up after.
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`In view of the foregoing problems with application of the
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`dual inlaid process to low-k dielectric materials, and the
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`disadvantages with single inlaid process, the present inven-
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`tion has been developed.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`The present invention is illustrated by way of example
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`and not limitation in the accompanying figures, in which like
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`references indicate similar elements, and in which:
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`3
`FIG. 1 depicts a step of providing a substrate having metal
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`interconnects therein;
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`FIG. 2 depicts a step of forming a via interlevel dielectric
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`(ILD) layer on the substrate;
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`FIG. 3 depicts formation of a mask, including a hard mask
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`and photoresist, on the via ILD layer;
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`FIG. 4 depicts the structure after etching the via ILD layer
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`to form vias;
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`FIG. 5 depicts a step of forming a trench ILD layer, over
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`the via ILD layer;
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`FIG. 6 depicts a step of forming a second mask, including
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`a second hard mask and second photoresist layer, on the
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`trench ILD layer;
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`FIG. 7 depicts a step of etching trenches in the trench level
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`ILD, the trenches being contiguous with the vias;
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`FIG. 8 depicts a step of filling metal to form a multilevel
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`metal (MLM) interconnect structure; and
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`FIG. 9 depicts a prior art method of forming a dual in-laid
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`multilevel metal interconnect structure.
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`Skilled artisans appreciate that elements in the figures are
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`illustrated for simplicity and clarity and have not necessarily
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`been drawn to scale. For example, the dimensions of some
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`of the elements in the figures are exaggerated relative to
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`other elements to help to improve understanding of
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`embodiment(s) of the present invention.
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`DETAILED DESCRIPTION OF THE DRAWINGS
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`In reference to FIGS. 1-8,
`the present
`invention is
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`described herein. FIG. 1 depicts a step of providing a
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`substrate 10 having metal interconnects 12 of semiconductor
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`device 1. The substrate 10 and metal interconnects 12 may
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`be formed of conventional materials. For example, substrate
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`10 may be formed of an oxide such as SiO2. However,
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`substrate 10 is preferably formed of a low-k dielectric
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`polymer material. The metal interconnects 12 are preferably
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`formed of copper, but may also be formed of aluminum,
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`gold, and silver, for example.
`In the case of a low-k
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`dielectric material for substrate 10, preferably a polish stop
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`layer 14 is incorporated, which provides an indication to
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`stop polishing the metal interconnects 12 after a metal fill
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`step. The polish stop layer may or may not be consumed
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`during polishing. It is noted that a polish stop layer need not
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`be incorporated in the structure in the case of an oxide
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`substrate, particularly SiO2. Further, a passivation layer 16
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`is provided so as to cover substrate 10, which includes metal
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`interconnects 12. Passivation layer 16 functions to protect
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`metal interconnects 12 from damage during later processing
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`steps, and also provides an etch stop function during later
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`processing steps. The passivation layer 16 may be formed of
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`silicon nitride, silicon oxynitride, or composites thereof.
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`However, it is noted that a passivation layer need not be
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`incorporated when certain metals are used for metal
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`interconnects, such as aluminum. Particularly, aluminum
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`forms a self-passivating layer formed of aluminum oxide. In
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`contrast, copper does not form an effective passivating layer.
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`The substrate is on the order of 5,000—12,000 angstroms
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`in thickness, and the passivating layer is generally on the
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`order of 300—1,100 angstroms in thickness. However,
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`preferably, the passivating layer is made as thin as possible
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`to minimize intra-line capacitance, and may be as thin as 10
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`angstroms. The substrate and passivating layer can be made
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`by conventional techniques, as well known in the art. For
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`example, the passivating layer can be made by chemical
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`vapor deposition or plasma-enhanced chemical vapor depo-
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`sition.
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`Page 7 of 9
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`4
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`FIG. 2 illustrates a next step of forming a via ILD layer
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`20. The via ILD layer 20 is preferably formed of low-k
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`organic materials, such as thermoplastics or thermosetting
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`plastics, having a dielectric constant lower than 3.5, prefer-
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`ably lower than 3.0. Examples of thermoplastics include
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`polyimides, polyarylethers, PTFEs, polyquinolines,
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`polyphenylquinoxalines, parylenes, and polynaphthalenes.
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`thermosetting plastics include
`Examples of
`benzocyclobutenes,
`fiuorinated amorphous carbons, and
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`polyimides. While particular materials for the via ILD layer
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`20 are set forth herein, it is understood that other low-k
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`materials may be utilized. The via ILD layer 20 is preferably
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`on the order 1,000 to 20,000 angstoms in thickness, more
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`preferably on the order of 5,000—12,000 angstroms in thick-
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`ness.
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`Thereafter, as shown in FIG. 3, a first hard mask 22 is
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`formed along with a first photoresist layer 24. The first hard
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`mask 22 is formed by an inorganic layer comprised of
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`various materials, such as silicon nitride, silicon oxynitride,
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`silicon dioxide, phosphorous-doped silicon dioxide, or com-
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`posites thereof, similar to the passivating layer 16. While the
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`drawings depict formation of first hard mask 22, this com-
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`ponent is not necessarily incorporated for inorganic dielec-
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`tric materials. However, in the case of an organic low-k
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`dielectrics such as those preferably used for via ILD layer
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`20, a hard mask is preferably incorporated.
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`FIG. 4 represents the structure after exposure and devel-
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`opment of the photoresist layer 24, followed by etching of
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`first hard mask 22 and via ILD layer 20, to form vias 30. The
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`photoresist
`layer 24 is not shown in FIG. 4, since the
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`photoresist
`is consumed during etching. Unlike single
`in-laid processes, no metal fill is incorporated at this stage,
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`rather,
`further processing steps are carried out.
`but
`In
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`particular, turning to FIG. 5, a second dielectric layer, trench
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`ILD layer 32 is deposited on the via ILD layer 20, after
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`etching thereof. As shown in FIG. 5, vias 30 are partially
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`filled by partial fill portions 32a of trench interlevel dielec-
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`tric (ILD)
`layer 32. While partial fill portions 32a are
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`depicted in FIG. 5, the extent of such portions is preferably
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`minimized, to simplify material removal during later stages.
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`Like the via ILD layer 20,
`the trench ILD layer 32 is
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`preferably on the order 1,000 to 20,000 angstoms in
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`thickness, more preferably on the order of 5,000—12,000
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`angstroms in thickness, and is formed of similar materials.
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`In FIG. 6, a second hard mask 34 and a second photoresist
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`layer 36 are deposited on trench ILD layer 32, in a similar
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`fashion to first hard mask 22 and first photoresist layer 24.
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`Thereafter, photoresist layer 36 is exposed and developed,
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`and several etching steps are carried out to form trenches 40.
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`Particularly, after exposure and development of second
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`photoresist layer 36, a first etching step is carried out to
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`remove desired portions of second hard mask 34, followed
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`by a second etching step to remove desired portions of
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`trench ILD layer 32, including partial fill portions 32a. Then,
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`portions of passivating layer 16 are etched to expose metal
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`interconnects 12. While three separate etching steps are
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`described herein, it is well recognized in the art that the
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`etching steps can be combined in a single process by
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`switching between appropriate etchant gases.
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`fill
`Finally, a metal
`is deposited simultaneously in
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`trenches 40 and vias 30, so as to make electrical contact with
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`metal interconnects 12. As is known in the art, chemical
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`mechanical polishing (CMP) is carried out to planarize the
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`in trenches 40, and optionally remove those
`metal
`fill
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`remaining portions of second hard mask 34.
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`Preferably, the metal fill 44 is formed of copper, which is
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`deposited by an electroplating technique. However, other
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`Page 7 of 9
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`

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`5,920,790
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`5
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`materials may be utilized, such as aluminum, gold, silver,
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`and alloys thereof (including alloys containing copper). In
`the case of copper, preferably relatively thin barrier and
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`metal seed layers are deposited along the topography of the
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`structure. Particularly, a thin barrier layer formed of TaN,
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`TiSiN, TaSiN, or other appropriate materials is deposited by
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`IMP or CVD techniques, followed by a metal seed layer
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`formed of copper, which may also be formed by IMP, CVD,
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`or electroless plating techniques. The barrier layer prevents
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`the copper from diffusing into the via ILD layer 20 and/or
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`the trench ILD layer 32. The seed layer provides good
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`electrical conduction for subsequent electroplating of the
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`copper fill material.
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`As can be understood in reference to the foregoing
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`explanation and the present drawings, a new process for
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`forming a dual in-laid structure is provided that overcomes
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`the deficiencies associated with prior art techniques. Accord-
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`ing to the present invention, materials such as low-k dielec-
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`trics that are reactive with photoresists and/or developers are
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`not exposed during deposition of the photoresist or appli-
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`cation of the developer. Accordingly, the present invention
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`overcomes disadvantages associated with interaction
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`between the photoresist and/or developer and the low-k
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`dielectric material as discussed in connection with the
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`conventional dual in-laid techniques.
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`Further, the present invention overcomes the disadvan-
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`tages with the single in-laid techniques described above.
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`Particularly, the present invention eliminates not only the
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`requirement to deposit individually within the via and trench
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`to form the multilevel metal interconnect, but also, elimi-
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`nates the intermediate CMP processing step by requiring
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`only one CMP processing step after depositing metal fill 44.
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`Accordingly, throughput and yield are increased, while cycle
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`time is decreased.
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`the invention has been
`In the foregoing specification,
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`described with reference to specific embodiments. However,
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`one of ordinary skill in the art appreciates that various
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`modifications and changes can be made without departing
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`from the scope of the present invention as set forth in the
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`claims below. Accordingly, the specification and figures are
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`to be regarded in an illustrative rather than a restrictive
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`sense, and all such modifications are intended to be included
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`within the scope of present invention. In the claims, means-
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`plus-function clause(s), if any, cover the structures described
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`herein that perform the recited function(s). The mean-plus-
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`function clause(s) also cover structural equivalents and
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`equivalent structures that perform the recited function(s).
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`What is claimed is:
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`1. A method for forming a semiconductor device com-
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`prising the steps of:
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`providing a substrate having a metal interconnect;
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`depositing a via interlevel dielectric layer over the sub-
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`strate and the metal interconnect;
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`etching the via interlevel dielectric layer to form a via
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`over the metal interconnect;
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`depositing a trench interlevel dielectric layer over the via
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`interlevel dielectric layer and the via;
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`etching the trench interlevel dielectric layer to form a
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`trench, the trench being contiguous with the via; and
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`depositing a metal so as to fill the via and the trench, and
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`provide electrical connection with the metal intercon-
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`nect
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`2. The method of claim 1, wherein the via interlevel
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`dielectric layer and the trench interlevel dielectric layer
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`comprise a dielectric material having a dielectric constant
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`less than 3.5.
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`10
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`Page 8 of 9
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`6
`3. The method of claim 2, wherein the dielectric material
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`is selected from a group consisting of thermoplastics and
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`thermosetting plastics.
`4. The method of claim 3, wherein the dielectric material
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`is a thermoplastic selected from a group consisting of
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`polyimides, polyarylethers, PTFEs, polyquinolines,
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`polyphenylquinoxalines, parylenes, and polynaphthalenes.
`5. The method of claim 3, wherein the dielectric material
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`is a thermosetting plastic selected from a group consisting of
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`benzocyclobutenes,
`fiuorinated amorphous carbons, and
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`polyimides.
`6. The method of claim 1, wherein the metal comprises a
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`material selected from a group consisting of copper,
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`aluminum, gold, and silver.
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`7. The method of claim 1, further comprising a step of
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`depositing a first mask on the via interlevel dielectric layer
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`prior to etching the via interlevel dielectric layer.
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`8. The method of claim 7, wherein the step of depositing
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`the first mask comprises the steps of:
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`depositing an inorganic layer over the via interlevel
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`dielectric layer; and
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`depositing a photoresist layer over the inorganic layer,
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`wherein the photoresist layer is patterned to form the
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`via.
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`9. The method of claim 8, wherein the inorganic layer
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`comprises a material selected from a group consisting of
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`silicon nitride, silicon oxynitride, silicon dioxide, phospho-
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`rous doped silicon dioxide, and composites thereof.
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`10. The method of claim 1, further comprising a step of
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`depositing a second mask on the trench interlevel dielectric
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`layer prior to the trench interlevel dielectric layer.
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`11. The method of claim 10, wherein the step of depos-
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`iting the second mask comprises the steps of:
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`depositing an inorganic layer over the trench interlevel
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`dielectric layer; and
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`depositing a photoresist layer over the inorganic layer,
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`wherein the photoresist layer is patterned to form the
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`trench.
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`12. The method of claim 11, wherein the inorganic layer
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`comprises a material selected from a group consisting of
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`silicon nitride, silicon oxynitride, silicon dioxide,
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`phosphorous-doped silicon dioxide, composites thereof.
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`13. The method of claim 1, further comprising the step of
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`depositing a passivation layer over the substrate before the
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`step of depositing the via interlevel dielectric layer.
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`14. The method of claim 13, wherein the passivation layer
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`comprises a material selected from a group consisting of
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`silicon nitride, silicon oxynitride, and composites thereof.
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`15. A method for forming a semiconductor device com-
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`prising the steps of:
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`providing a substrate having a metal interconnect;
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`depositing a via interlevel dielectric layer comprising a
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`dielectric material having a dielectric constant of less
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`than 3.5 over the substrate and the metal interconnect;
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`depositing a first inorganic layer over the via interlevel
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`dielectric layer;
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`depositing a first photoresist layer over the first inorganic
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`layer;
`patterning the first photoresist layer;
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`etching the first inorganic layer and the via interlevel
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`dielectric layer using the first photoresist layer to form
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`a via over the metal interconnect;
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`depositing a trench interlevel dielectric layer comprising
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`a dielectric material having a dielectric constant of less
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`than 3.5 over the via interlevel dielectric layer and the
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`via;
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`Page 8 of 9
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`5,920,790
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`10
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`15
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`20
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`25
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`7
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`depositing a second inorganic layer over the trench inter-
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`level dielectric layer;
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`depositing a second photoresist layer over the second
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`inorganic layer;
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`patterning the second photoresist layer;
`etching the second inorganic layer and the trench inter-
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`level dielectric layer using the second photoresist layer
`to form a trench, the trench being contiguous with the
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`Via; and
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`depositing a metal so as to fill the Via and the trench, and
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`provide electrical connection with the metal intercon-
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`nect
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`16. The method of claim 15, wherein the dielectric
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`material is selected from a group consisting of thermoplas-
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`tics and thermosetting plastics.
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`17. The method of claim 16, wherein the dielectric
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`material is a thermoplastic selected from a group consisting
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`of polyimides, polyarylethers, PTFEs, polyquinolines,
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`polyphenylquinoxalines, parylenes, and polynaphthalenes.
`18. The method of claim 16, wherein the dielectric
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`material is a thermosetting plastic selected from a group
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`consisting of benzocyclobutenes,
`fluorinated amorphous
`carbons, and polyimides.
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`19. The method of claim 15, wherein the metal comprises
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`a material selected from a group consisting of copper,
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`aluminum, gold, and silver.
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`Page 9 of 9
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`8
`20. The method of claim 15, wherein the first and second
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`inorganic layers comprise a material selected from a group
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`consisting of silicon nitride, silicon oxynitride, silicon
`
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`dioxide, phosphorous-doped silicon dioxide, and composites
`
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`thereof.
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`21. The method of claim 15, further comprising the step
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`of depositing a passiVation layer over the substrate before
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`the step of depositing the Via interlevel dielectric layer.
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`22. The method of claim 21, wherein the