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`C E R T I F I C A T I O N O F T R A N S L A T I O N
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`The undersigned, Richard Patner, whose address is 26357 Lexington Drive,
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`Bonita Springs, FL 34135, United States of America, declares and states as follows:
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`I am well acquainted with the English and Japanese languages; I have in the
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`past translated numerous Japanese documents of legal and/or technical content into
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`English.
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`I have been requested to translate into English the attached Japanese
`Patent No. 10-079371 titled “Method of forming wiring structure .”
`
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`To a copy of this Japanese document I therefore attach an English translation
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`and my Certification of Translation.
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`I hereby certify that the attached English translation of Japanese Patent No. 10-
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`079371 titled “Method of forming wiring structure” is, to the best of my knowledge
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`and ability, an accurate translation.
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`And I declare further that all statements made herein of my own knowledge are
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`true, that all statements made on information and belief are believed to be true, and that
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`false statements and the like are punishable by fine and imprisonment, or both, under
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`Section 1001 of Title 18 of the United States Code.
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`__ _________ ______May 27, 2016_____________
`Date
`Richard Patner
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`TSMC Exhibit 1014
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`Page 1 of 43
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`[Patent] 1998-079371 (10.03.26)
`[Application] (1) (10-079371) (10.03.26) Designation (7411290311) Application type (01) New law
`Date of publication of application ( ) ( ) Publication date of record (10.03.26) Domestic priority (0)
`Publication ( ) ( ) Priority ( ) Foreign
`Appeal ( ) ( ) ( ) Authority ( ) ( )
`[Registration] ( ) ( ) Objection (0) Number of Claims (9) Application fee (=Y21,000)
`Official Decision (made by ) (authority ) Literature ( ) Originality (0) Bacterial sustenance (0) Pollution ( )
`Investigation and Decision ( )(made by ) (authority ) Pretrial ( ) Cancellation ( ) Public order - Summary (0)
` (Issued) (Agency) Request for Review-Evaluation (0-2) Not yet requested (0) Auto drafting ( )
`Final (A11) (11.10.21) Publication preparations (1) Early review ( )
`Revision destination (1) (11-075519) (01 ) Decision ( ) ( )
`Original Application () () () Type ( )
`Extension of term ( ) Latest drafting date ( )
`
`Publication ( ) ( ) Translation submission ( ) International Application ( )
`Republication ( ) International publication ( )
`Publication IPC4 H01L 21/88 KFIC Designated classification IPC
`Publication IPC
`Title Method of forming wiring structure
`Applicant Representative ( ) Type (2) Code (000005821) Country (27) Panasonic Corporation
`Osaka-fu, Kadoma-shi, Oaza Kadoma 1006
`Representative Type (1) Code (1000077931) Maeda Hiroshi
`Type (1) Code ( ) Koyama Hiroki
`Type (1) Code (100107445) Koneda Ichiro
`Intermediate (A63) Patent Application 10.03.26 (21,000) Complete (A96-1) Ex officio correction 10.04.01 ( )
`Record (A84-a) (Priority Claim 11.03.24 ( ) (A84-3) Priority Claim 11.07.21 ( )
`(A85-1) Issued Claim 12.11.21 ( ) (A86-1) Inspected Claim 15.03.13 ( )
`(A86-1 ) Inspected Claim 15.09.22 ( )
`New Application
`Domestic Priority (Leading)
`Domestic Priority (Trailing) 11-075519 (11.03.19) 1 2000-066163 (12.03.10)
`1 2000-066179 (12.03.10)
`
`Page 2 of 43
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`[Acceptance date] March 26, 1998
`[Document Name] Patent Application
`Page: 1/2
`[Patent] 10-079371 (10.3.26)
`-------------------------------------------------------------------------------------------------------------------------------------------
`-----
`[Name of Document] Patent Application
`[Reference Number] 7411290311
`[Submission Date] March 26, 1998
`[Addressee] Director of Patent Agency
`[International Patent Classification] H01 L 21/316
`[Title of Invention] Method of forming wiring structure
`[Number of Claims] 9
`[Inventor]
`[Address or Location] Osaka-fu, Kadoma-shi, Oaza Kadoma 1006
`Matsushita Electric Industrial Co., Ltd.
`[Name] AOI Nobuo
`[Patent Applicant]
`[Identification Number] 000005821
`[Name] Matsushita Electric Industrial Co., Ltd.
`
`[Agent]
`
`[Identification Number] 1000077931
`[Patent Attorney]
`[Name or Appellation] Maeda Hiroshi
`[Designated Agent]
`[Identification Number] 100094134
`[Patent Attorney]
`[Name or Appellation] Koyama Hiroki
`[Designated Agent]
`[Identification Number] 100107445
`[Patent Attorney]
`[Name or Appellation] Koneda Ichiro
`[Display of Commissions]
`[Prepayment Registry Number] 014409
`[Payment Sum] =Y21,000
`[Record of Submitted Documents]
`[Article Name] Specification 1
`[Article Name] Diagrams 1
`[Article Name] Abstract 1
`[Comprehensive Authorization Number] 9601026
`[Requirement of Proof] Required
`
`Page 3 of 43
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`[Acceptance date] March 26, 1998
`[Document Name] Specification
`Page: 1/40
`[Patent] 10-079371 (10.3.26)
`-------------------------------------------------------------------------------------------------------------------------------------------
`----
`[Name of Document] Specification
`[Title of Invention] Method of forming wiring structure
`[Scope of Patent Claims]
`[Claim 1] A method of forming a wiring structure comprising 11 steps:
`a first step of forming a first insulating film over lower-level metal wiring,
`a second step of forming a second insulating film having a different structure from that of said first insulating film over
`the aforementioned first insulating film,
`a third step of forming a third insulating film having a different structure from that of said second insulating film over the
`aforementioned second insulating film,
`a fourth step of forming a conducting film over the aforementioned third insulating film,
`a fifth step of forming a first resist pattern having an opening for the formation of wiring over the aforementioned
`conducting film,
`a sixth step of forming a mask pattern from the aforementioned conducting film with an opening for the formation of
`wiring by etching the aforementioned conducting film using the aforementioned first resist pattern as a mask,
`a seventh step of forming a second resist pattern with an opening for the formation of contact holes over the
`aforementioned third insulating film,
`an eighth step of patterning the aforementioned third insulating film so as to form an opening for the formation of contact
`holes in said third insulating film by dry etching the aforementioned third insulating film using the first resist pattern or
`the second resist pattern under etching conditions such that the pattern with the higher etching rate is used while the
`pattern with the lower etching rate is used in etching of the aforementioned second insulating film, and by removing the
`entire first resist pattern and second resist pattern or leaving the lower portion,
`a ninth step of patterning the aforementioned second insulating film so as to form an opening for the formation of contact
`holes in said second insulating film by dry etching, using the aforementioned third insulating film that had been patterned
`as a mask, of the aforementioned second insulating film under etching conditions such that the etching rate of the
`aforementioned second insulating film is higher while the etching rate of the aforementioned first insulating film and the
`third insulating film is lower,
`a tenth step of forming wiring grooves in the aforementioned third insulating film and of forming contact holes in the
`aforementioned first insulating film by dry etching using the aforementioned mask pattern for the aforementioned third
`insulating film as a mask and by dry etching using the aforementioned second insulating film that had been patterned for
`the aforementioned first insulating film as a mask under etching conditions such that the etching rate of the
`aforementioned first insulating film and the third insulating film is higher while the etching rate of the mask pattern and
`of the second insulating film is lower,
`and an eleventh step of forming contacts that connect the upper-level metal wiring and the aforementioned lower-level
`metal wiring with the aforementioned upper-level metal wiring by packing metal film in the aforementioned wiring
`grooves and contact holes.
`[Claim 2] The method of forming a wiring structure of Claim 1 in which a step of forming adhesion layers comprising
`metal film in the section of the aforementioned third insulating film exposed in the aforementioned wiring grooves and in
`the section of the aforementioned first insulating film exposed in the aforementioned contact holes is inserted between
`the aforementioned tenth step and the aforementioned eleventh step.
`[Claim 3] The method of forming a wiring structure of Claim 1 in which the principal constituents of the aforementioned
`third insulating film are organic constituents.
`[Claim 4] The method of forming a wiring structure of Claim 3 in which the aforementioned third step also includes the
`step of forming the aforementioned third insulating film by the CVD method using reactive gas that contains
`perfluorodecalin.
`[Claim 5] The method of forming a wiring structure of Claim 3 in which the principal constituents of the aforementioned
`first insulating film are organic constituents.
`[Claim 6] The method of forming a wiring structure of Claim 5 in which a step of forming an adhesion layer by plasma
`treatment using reactive gas containing nitrogen in the section of the aforementioned third insulating film exposed in the
`aforementioned wiring grooves and in the section of the aforementioned first insulating film exposed in the
`aforementioned contact holes is further included between the aforementioned tenth step and the aforementioned eleventh
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`step.
`[Claim 7] The method of forming a wiring structure of Claim 3 in which the aforementioned first step includes a step of
`forming the aforementioned third insulating film by the CVD method using reactive gas that contains perfluorodecalin.
`[Claim 8] A method of forming a wiring structure comprising 12 steps:
`a first step of forming a first insulating film over lower-level metal wiring,
`a second step of forming a second insulating film having a different structure from that of said first insulating film over
`the aforementioned first insulating film,
`a third step of forming a third insulating film having a different structure from that of said second insulating film over the
`aforementioned second insulating film,
`a fourth step of forming a conducting film over the aforementioned third insulating film,
`a fifth step of forming a first resist pattern having an opening for the formation of wiring over the aforementioned
`conducting film,
`a sixth step of forming a mask pattern from the aforementioned conducting film with an opening for the formation of
`wiring by etching the aforementioned conducting film using the aforementioned first resist pattern as a mask,
`a seventh step of forming a second resist pattern with an opening for the formation of contact holes over the
`aforementioned third insulating film,
`an eighth step of patterning the aforementioned third insulating film so as to form an opening for the formation of contact
`holes in said third insulating film by dry etching the aforementioned third insulating film using the aforementioned first
`resist pattern or the second resist pattern as the mask under etching conditions such that the aforementioned third
`insulating film has a higher etching rate while the second insulating film has a lower etching rate relative to the first
`resist pattern and the second resist pattern,
`a ninth step of patterning the aforementioned second insulating film so as to form an opening for the formation of contact
`holes in said second insulating film by dry etching the aforementioned second insulating film using the aforementioned
`first resist pattern or the second resist pattern as the mask under etching conditions such that the aforementioned second
`insulating film has a higher etching rate while the first insulating film and third insulating film have lower etching rates
`relative to the first resist pattern and the second resist pattern,
`a tenth step of removing the aforementioned first resist pattern and the aforementioned second resist pattern,
`an eleventh step of forming wiring grooves in the aforementioned third insulating film and of forming contact holes in
`the aforementioned first insulating film by dry etching of the aforementioned third insulating film using the
`aforementioned mask pattern as a mask and by dry etching of the aforementioned first insulating film using the
`aforementioned patterned second insulating film as a mask under etching conditions such that the etching rate of the
`aforementioned first insulating film and the third insulating film is higher while the etching rate of the aforementioned
`mask pattern and of the second insulating film is lower,
`and a twelfth step of forming contacts that connect the upper-level metal wiring and the aforementioned lower-level
`metal wiring with the aforementioned upper-level metal wiring by packing metal film in the aforementioned wiring
`grooves and contact holes.
`[Claim 9] The method of forming a wiring structure of Claim 8 in which the aforementioned third insulating film is a
`low-dielectric-constant SOG film with a siloxane framework.
`[Detailed Description of the Invention]
`[0001]
`[Technical Field of Invention]
`The present invention concerns a method of forming a wiring structure in semiconductor integrated circuit devices.
`[0002]
`[Related Art]
`Accompanying higher integration of semiconductor integrated circuits, expansion of the wiring delay times attributable
`to increase in the interwiring capacitance, which is parasitic capacitance between metal wiring, has blocked higher
`performance of semiconductor integrated circuits. The wiring delay time is known as the so-called RC delay, which is
`proportional to the product of the metal wiring resistance and the interwiring capacitance.
`[0003]
`Accordingly, the resistance of the metal wiring must be reduced or the inter-wiring capacitance must be reduced in order
`to reduce the wiring delay time.
`[0004]
`Thus, IBM and Motorola have reported semiconductor integrated circuit devices that use copper instead of aluminum
`alloy as material for wiring in order to reduce the wiring resistance. Copper material has a specific resistance about two-
`thirds as high as that of an aluminum alloy material. Accordingly, in accordance with simple calculation, the wiring
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`delay involved with the use of a copper material for wiring material can be about two-thirds of that involved with the use
`of an aluminum alloy material therefor. That is to say, the operating speed can be increased by about 1.5 times.
`[0005]
`However, there is a concern that even the use of copper in metal wiring would not be able to catch up with the
`drastically increasing integration of semiconductor integrated circuits. Also, the specific resistance of copper as wiring
`material is just a little bit higher than, but almost equal to, that of gold or silver. Accordingly, even if gold or silver is
`used instead of copper as a metal wiring material, the wiring resistance would be reduced only slightly.
`[0006]
`Under these circumstances, not only reducing wiring resistance but also suppressing inter-wiring capacitance are
`essential in further increasing the number of devices that can be integrated within a single semiconductor integrated
`circuit. In addition, the relative dielectric constant of an interlevel insulating film must be reduced to suppress the inter-
`wiring capacitance. A silicon dioxide film has heretofore been used as a typical material for an interlevel insulating film.
`However, the relative dielectric constant of a silicon dioxide film is about 4 to 4.5. Thus, it would be difficult to apply a
`silicon dioxide film to a semiconductor integrated circuit that has a higher degree of integration.
`[0007]
`In order to solve such problems, fluorine-doped silicon dioxide film, low-dielectric-constant SOG film, and organic
`polymer film have been proposed as alternate interlevel insulating films with smaller relative dielectric constants than
`that of silicon dioxide film.
`[0008]
`[Problems Solved by the Invention]
`The relative dielectric constant of a fluorine-doped silicon dioxide film is about 3.3 to 3.7, which is about 20 percent
`lower than that of a conventional silicon dioxide film. However, a fluorine-doped silicon dioxide film is highly
`hygroscopic and easily absorbs water in the air, resulting in various problems in practice. For example, when the
`fluorine-doped silicon dioxide film absorbs water, SiOH groups having a high relative dielectric constant are introduced
`into the film. As a result, the relative dielectric constant of the fluorine-doped silicon dioxide film adversely increases or
`the SiOH groups react with the water during a heat treatment to release H2O gas. In addition, fluorine free radicals
`contained in the fluorine-doped silicon dioxide film segregate near the surface thereof during a heat treatment and react
`with Ti contained in a TiN layer formed thereon as an adhesion layer to form a TiF film, which easily peels off.
`[0009]
`An HSQ (hydrogen silsesquioxane film, composed of Si, O and H atoms in which the number of H atoms is about two-
`thirds that of O atoms) is a low-dielectric-constant SOG film that has been examined. However, HSQ film releases a
`larger amount of water than a conventional silicon dioxide film. Accordingly, since it is difficult to form buried wiring in
`the HSQ film, a patterned metal film must be formed as metal wiring on HSQ film.
`[0010]
`Also, since the HSQ film cannot adhere strongly to metal wiring, a CVD oxide film should be formed between the metal
`wiring and the HSQ film to improve the adhesion therebetween. However, in such a case, the problem of greater
`interwiring capacitance compared to the case of using HSQ film alone arises because the interwiring capacitance
`essentially becomes the serial capacitance of HSQ film and CVD oxide film because of the presence of CVD oxide film
`that has great specific interwiring inductive capacitance.
`[0011]
`An organic polymer film as well as the low-dielectric constant SOG film similarly cannot adhere strongly to metal
`wiring. Accordingly, a CVD oxide film must be formed as an adhesion layer between the metal wiring and the organic
`polymer film as well.
`[0012]
`Moreover, the problem arises of the inability to use the conventional resist process because an organic polymer film
`would be damaged when removing a resist pattern by ashing since the etching rate of an organic polymer film is virtually
`equal to the ashing rate when ashing a resist pattern using an oxygen plasma. Thus, a method of etching resist film has
`been proposed in which a CVD oxide film is formed over an organic polymer film, followed by the formation of a resist
`film over said CVD oxide film so that said CVD oxide film would act as an etching stopper,
`[0013]
`However, during the step of forming the CVD oxide film over the organic polymer film, the surface of the organic
`polymer film is exposed to a reactive gas containing oxygen, as a result of which the organic polymer film reacts with
`oxygen to take in polar groups such as carbonyl groups and ketone groups. As a result, the problem arises of increase in
`the relative dielectric constant of the organic polymer film.
`[0014]
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`Also, in forming embedded copper wiring in the organic polymer film, a TiN adhesion layer, for example, should be
`formed around wiring grooves formed in the organic polymer film because the organic polymer film cannot adhere
`strongly to the metal wiring. However, since the TiN film has high resistance, the effective cross-sectional area of the
`metal wiring decreases. Consequently, the intended effect attainable by the use of the copper lines, i.e., reduction in
`resistance, would be lost.
`[0015]
`In light of the aforementioned circumstances, an objective of the present invention is to enable the formation of an
`interlevel insulating film having a low relative dielectric constant while using the conventional resist process.
`[0016]
`[Means of Solving the Problems]
`The first method of forming a wiring structure pursuant to the present invention comprises 11 steps: a first step of
`forming a first insulating film over lower-level metal wiring, a second step of forming a second insulating film having a
`different structure from that of said first insulating film over the first insulating film, a third step of forming a third
`insulating film having a different structure from that of said second insulating film over the second insulating film, a
`fourth step of forming a conducting film over the third insulating film, a fifth step of forming a first resist pattern having
`an opening for the formation of wiring over the conducting film, a sixth step of forming a mask pattern from the
`aforementioned conducting film with an opening for the formation of wiring by etching the conducting film using the
`first resist pattern as a mask, a seventh step of forming a second resist pattern with an opening for the formation of
`contact holes over the third insulating film, an eighth step of patterning the third insulating film so as to form an opening
`for the formation of contact holes in said third insulating film by dry etching the third insulating film using the first resist
`pattern or the second resist pattern under etching conditions such that the pattern with the higher etching rate is used
`while the pattern with the lower etching rate is used in etching of the second insulating film, and by removing the entire
`first resist pattern and second resist pattern or leaving the lower portion, a ninth step of patterning the second insulating
`film so as to form an opening for the formation of contact holes in said second insulating film by dry etching, using the
`third insulating film that had been patterned as a mask, of the second insulating film under etching conditions such that
`the etching rate of the second insulating film is higher while the etching rate of the first insulating film and the third
`insulating film is lower, a tenth step of forming wiring grooves in the third insulating film and of forming contact holes in
`the first insulating film by dry etching using the mask pattern for the third insulation as a mask and by dry etching using
`the second insulating film that had been patterned for the first insulating film as a mask under etching conditions such
`that the etching rate of the first insulating film and the third insulating film is higher while the etching rate of the mask
`pattern and of the second insulating film is lower, and an eleventh step of forming contacts that connect the upper-level
`metal wiring and the lower-level metal wiring with the upper-level metal wiring by packing metal film in the wiring
`grooves and contact holes.
`[0017]
`In the eighth step of forming the first wiring structure, the third insulating film is patterned by dry etching using the first
`resist pattern or the second resist pattern under etching conditions such that the pattern with the higher etching rate is
`used while the pattern with the lower etching rate is used in etching of the second insulating film, and both the first resist
`pattern and the second resist pattern are then removed, as a result of which the step of removing the first resist pattern
`and the second resist pattern by ashing with oxygen plasma is obviated.
`[0018]
`In addition, the second insulating film can be used as an etching stopper in the tenth step when forming wiring grooves
`by dry etching using the mask pattern for the third insulating film as a mask because the structures of the second
`insulating film and of the third insulating film differ.
`[0019]
`The inclusion in the first method of forming a wiring structure of a step between the tenth step and the eleventh step in
`which an adhesion layer comprising metal film is formed in the section of the third insulating film exposed in the wiring
`grooves and in the section of the first insulating film exposed in the contact holes would be desirable.
`[0020]
`Setting the principal constituents of the third insulating film to be organic constituents would be desirable in the first
`method of forming a wiring structure.
`[0021]
`In this case, the inclusion of a third step of forming the third insulating film by the CVD method using reactive gas that
`contains perfluorodecalin would be desirable.
`[0022]
`Setting the principal constituents of the first insulating film to be organic constituents in this case would be desirable.
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`[0023]
`The further inclusion between the tenth step and the eleventh step of a step of forming an adhesion layer by plasma
`treatment using reactive gas containing nitrogen in the section of the third insulating film exposed in the wiring grooves
`and in the section of the first insulating film exposed in the contact holes would be desirable.
`[0024]
`When the principal constituent of the first insulating film is an organic constituent, the inclusion in the first step of a step
`of forming the third insulating film by the CVD method using reactive gas that contains perfluorodecalin would be
`desirable.
`[0025]
`The second method of forming a wiring structure pursuant to the present invention comprises 12 steps: a first step of
`forming a first insulating film over lower-level metal wiring, a second step of forming a second insulating film having a
`different structure from that of said first insulating film over the first insulating film, a third step of forming a third
`insulating film having a different structure from that of said second insulating film over the second insulating film, a
`fourth step of forming a conducting film over the third insulating film, a fifth step of forming a first resist pattern having
`an opening for the formation of wiring over the conducting film, a sixth step of forming a mask pattern from the
`conducting film with an opening for the formation of wiring by etching the conducting film using the first resist pattern
`as a mask, a seventh step of forming a second resist pattern with an opening for the formation of contact holes over the
`third insulating film, an eighth step of patterning the third insulating film so as to form an opening for the formation of
`contact holes in said third insulating film by dry etching the third insulating film using the first resist pattern or the
`second resist pattern as the mask under etching conditions such that the third insulating film has a higher etching rate
`while the second insulating film has a lower etching rate relative to the first resist pattern and the second resist pattern, a
`ninth step of patterning the second insulating film so as to form an opening for the formation of contact holes in said
`second insulating film by dry etching the second insulating film using the first resist pattern or the second resist pattern
`as the mask under etching conditions such that the second insulating film has a higher etching rate while the first
`insulating film and third insulating film have lower etching rates relative to the first resist pattern and the second resist
`pattern, a tenth step of removing the first resist pattern and the second resist pattern, an eleventh step of forming wiring
`grooves in the third insulating film and of forming contact holes in the first insulating film by dry etching of the third
`insulating film using the mask pattern as a mask and by dry etching of the first insulating film using the patterned second
`insulating film as a mask under etching conditions such that the etching rate of the first insulating film and the third
`insulating film is higher while the etching rate of the mask pattern and of the second insulating film is lower, and a
`twelfth step of forming contacts that connect the upper-level metal wiring and the lower-level metal wiring with the
`upper-level metal wiring by packing metal film in the wiring grooves and contact holes.
`[0026]
`Even if a damaged layer is formed in the section exposed in an opening for the formation of contact holes in the second
`insulating film of the first insulating film and the third insulating film in the tenth step of removing the first resist pattern
`and the second resist pattern in the second method of forming a wiring structure, a damaged layer formed in the first
`insulating film and the third insulating film is reliably removed since wiring grooves are formed in the third insulating
`film and since contact holes are formed in the first insulating film by dry etching using a mask pattern for the third
`insulating film as a mask and by dry etching using a second insulating film that had been patterned for the first insulating
`film as a mask under etching conditions such that the etching rate is higher for the first insulating film and the third
`insulating film as well as etching conditions such that the etching rate of the mask pattern and the second insulating film
`is lower.
`[0027]
`The third insulating film in the second method of forming a wiring structure preferably would be a low-dielectric-
`constant SOG film with a siloxane framework.
`[0028]
`[Description of the Preferred Embodiments]
`(First Embodiment)
`The method of forming a wiring structure pursuant to the first embodiment of the present invention is explained below
`with reference to Figure 1 (a) to (c), Figure 2 (a) to (c) and Figure 3 (a) to (c).
`[0029]
`First, as shown in Figure 1(a), a silicon nitride film 102 is formed over a first metal wiring 101 formed on a
`semiconductor substrate 100. The silicon nitride film 102 is formed to be 50 nm thick, for example, and to protect the
`first metal wiring 101 during a subsequent etching process step. Thereafter, a first organic film 103 whose principal
`constituent is an organic constituent and that has a film thickness of 1 µm, for example, is deposited on said silicon
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`nitride film 102. Then, an organic constituent-incorporated silicon oxide film 104 with film thickness of 50 nm that
`contains organic constituents in silicon oxide is deposited on the first organic film 103. Then, a second organic film 105
`with a film thickness of 400 nm whose principal constituent is organic constituent is deposited on said organic
`constituent-incorporated silicon oxide film 104. Subsequently, a titanium nitride film 106 having a film thickness of 50
`nm, for example, is deposited on said second organic film 105.
`[0030]
`There is no specific limitation on the method of depositing the first and second organic films 103 and 105. For example,
`the plasma CVD method using reactive gas whose principal constituent is perfluorodecalin may be used. Furthermore,
`hydrocarbon films or hydrocarbon films containing fluorine formed by the plasma CVD method, the application method
`or by the thermal CVD method may be used as the first and second organic films 103 and 105.
`[0031]
`Moreover, the first organic film 103 may be deposited by a plasma CVD process using a reactive gas mainly composed
`of perfluorodecalin and organic silanes such as hexamethyl disiloxane, arylalkoxy silane or alkylalkoxy silane. In such
`cases, an organic/inorganic hybrid film can be obtained.
`[0032]
`Similarly, there is no specific limitation on the method of deposition of the organic constituent-incorporated silicon oxide
`film 104. For instance, the film 104 may be deposited by a CVD process using a reactive gas mainly composed of
`phenyltrimethoxy silane. In such a case, an organic constituent-incorporated silicon oxide film 104 with a structure in
`which a phenyl group bonded to a silicon atom is incorporated into silicon dioxide can be obtained.
`[0033]
`Next, as shown in Figure 1 (b), a first resist pattern 107 having openings for the formation of wiring grooves is formed
`by lithography on the titanium nitride film 106. Thereafter, the titanium nitride film 106 is dry-etched using the first
`resist pattern 107 as a mask, thereby forming a mask pattern 108 out of the titanium nitride film 106 as shown in Figure
`1 (c).
`[0034]
`Subsequently, a second resist pattern 109 with openings for forming contact holes is formed by lithography on the
`second organic film 105 without removing the first resist pattern 107. Then, the second organic film 105 is dry-etched,
`thereby forming a patterned second organic film 105A having the openings for the formation of contact