`
`FILE HISTORY
`US 6,197,696
`
`6,197,696
`PATENT:
`INVENTORS: Aoi, Nobuo
`
`TITLE:
`
`Method for forming interconnection
`structure
`
`APPLICATION
`NO:
`FILED:
`ISSUED:
`
`US1999274114A
`
`23 MAR 1999
`06 MAR 2001
`
`COMPILED:
`
`12 MAY 2015
`
`TSMC Exhibit 1012
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`Page 1 of 388
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`

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`ISSUE
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`PATENT NUMBER
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`61 97696
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`The iniormation disclosed herein may be restricted. Unauthorized disclosure may be prohibited by the United States Code Title 35, Sections 122, 181 and 368.
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`Page 2 of 388
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`6,197,696
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`METHOD FOR FORMING INTERCONNECTION STRUCTURE
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`Transaction History
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`W Transaction Descri s tion
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`03-23-1999 Workflow - Drawins Finished
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`03-23-1999 Workflow - Drawins Matched with File at Contractor
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`03-23-1999 Workflow - Drawins Received at Contractor
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`03-29-1999
`Initial Exam Team nn
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`IFW Scan & PACR Auto Securit Review
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`A lication Disatched from OIPE
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`Case Docketed to Examiner in GAU
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`Reuest for Foreign Priorit
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`Information Disclosure Statement (IDS Filed
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`Information Disclosure Statement (IDS) Filed
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`Information Disclosure Statement (IDS) Filed
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`Information Disclosure Statement (IDS) Filed
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`Case Docketed to Examiner in GAU
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`Mail Notice of Allowance
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`Workflow - File Sent to Contractor
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`02-04-2001 I A plication Is Considered Ready for Issue
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`INDEX OF CLAIMS .
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`N ............................... .. Non-elected
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`’ SEARCH NOTES
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`(12) United States Patent
`Act
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`(10) Patent No.:
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`(-45) Date of Patent:
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`US 6,197,696 B1
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`Mar. 6, 2001
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`US00t'il.97696Bl
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`(54) METHOD FOR FORMING
`INTERCONNECTION STRUCTURE
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`(75)
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`Inventor: Nohno Aoi, Hyogo (JP)
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`(73) Astignce: Mtttsltshitn Electric Indttstrinl Co,
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`Ltt:l., Osaka (JP)
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`( * ) Notice:
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`Subject to any disclaimer, the term of this
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`patent is extended or adjusted under 35
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`U.S.C. 154-(h) by 0 days.
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`(21) App]. No: 09/274,114
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`(22)
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`Iiiledr
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`Mar. 23, 1999
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`(30)
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`Foreign Application Priority Data
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`Mac. 2.5, 1993
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`(JP) ............................................... .- 10-(179371
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`HIILL 21/311
`Int. (31.7
`(51)
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`..... .. 43St‘70D; 4383706
`(52) US. Cl.
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`(58) Field of Search .................................... .. 438,000. 706
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`
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`References Cited
`U.S. PATENT DO'CUMEN'I‘S
`
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`5,110,712
`531992 Kesslcr et ai. ................... .. 43831523
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`
`
`
`5,518,963 * ,5,=19rtn- Park
`438l62_4
`
`
`
`
`6.31997 Huang cl al.
`....._......t._.......- 438E638
`5.635.423 *
`
`
`
`W199? Dennison el al.
`..
`.. .. 438,I'628s.
`5,651,855
`
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`
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`
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`5__'(TJ2,982 * l2,i1997 Ixzc cl al- ......._...-................. 438,620
`
`
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`
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`(56)
`
`FOREIGN PATENT DOCUMENTS
`
`
`
`
`0 425 787 A2
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`
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`
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`0 680 085 Al
`s-291193
`
`’?—l53»342
`9-640314
`94.53545
`
`5fl99l
`1121995
`(IF)
`ln;199=t
`@1995 (JP)
`331997
`6;‘l99'? (JP)
`
`. . . . . . . .
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`
`
`
`
`(r. ) ............................ .. Hill l.J2lf9[l
`
`
`..... ..
`I'I0lL,J‘2l;’768
`
`
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`..._.._.. HtJ1I.;‘2l;9n
`
`........ Ht'JlLt'21t'7f»5
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`. . . . . ..
`l-I01l..!2lf32CI5
`
`HtJ1LJ21f768
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`
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`
`
`0TH]-ER PUBLICATIONS
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`
`
`
`European Search Report dated Jul. 1, 1999.
`
`
`
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`* cited by examiner
`
`
`
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`Printnzgy Jixarniner—-Benjamin L. Utcch
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`Asstltrnrtr E.a:c1ntirter—-Lynette T. Umez-Eronini
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`(74) Attorney, Agent, or Ft'm:——«Eric .1. Robinson; Nixon
`Peabody LLP
`
`
`
`(57)
`
`ABSTRACT
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`In a method for forming an interconnection structure, first,
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`second and third insulating films and a thin film are sequen-
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`Litilly formed over lower-level metal interconnects. 'lhen, the
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`thin filrn is masked with a lion resist pattern and etched to
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`form a mask pattern with openings for interconnects. Next,
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`The third insulating film is masked with a second resist
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`pattern and dry-etched such that the third insulating film and
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`the first and second resist patterns are etched at a high rate
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`and that the xcond insulating, film is etched at a low rate to
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`for-n1 openings for Contact holes in the third insulating film
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`and remove the that -and second resist patterns. Then, the
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`second insulating film is masked with Ibo third insulating
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`film and dry-etched such that the second insulating film is
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`etched at a high rate and that the firs-t and third insulating
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`films are etched at a low rate to form the openings for contact
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`holes in the second insulating film. Then, the third and first
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`insulating films are masked with the mask pattern and the
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`second insulating filn1,.respectivcly, and dry-etched such
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`that Lhc first and third i_n5Ltla_tiJ:tg films are etched at .3. high
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`rate and that the mask pattern and the second insulating film
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`are etched at a low rate to form wiring grooves and contact
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`holes in the third and first insulating films, respectively.
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`Finally, uppcplevel metal interconnects ‘and contacts are
`formed.
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`15 Claims, 37 Drawing Sheets
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` U.S. Patent
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`Mar. 6, 2001
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`553
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`552
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`551
`
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`Fig. 24 (C)
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`Sheet 25 of 37
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`US 6,197,696 B1
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`:\\\\\\\\V
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`Fig.25(c)
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`556A
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`551
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`550
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`Mar. 6,2001
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`Sheet 26 of 37
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`US 6,197,696 B1
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`m\\.\\.\\\V
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`Fig.26(a)
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`Fig. 25 (5)
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`553A
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`552A
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`551
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`550
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`Mar. 6,2001
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`Sheet 27 of 37
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`US 6,197,696 B1
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`559
`
`II
`,1
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`
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`
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`
`556
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`
`553
`
`
`Fig.27(a)
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`U.S. Patent
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`Mar. 6,2001
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`Sheet 23 of 37
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`US 6,197,696 B1
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`Fig.28(a)
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`US. Patent
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`Mar. 6, 2001
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`Sheet 29 of 37
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`US 6,197,696 B1
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`Sheet 30 of 37
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`US 6,197,696 B1
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`
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`L\\\\\\\\\\\\\\\\\\\\\\\\.\
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`606
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`— 603
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`Flg. 30 (b)
`,
`603
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`% 38%
`&\\ 600
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`607
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`Page 37 of 388
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`605
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`607
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`Sheet 31 of 37
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`US 6,197,696 B1
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`
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`n&\\\\\\\1 -
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`I.
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`ggg
`
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`
`600
`
`
`Fig. 31 (a)
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`
`F1g.31(b)
`
`
`Fig. 31 (c)
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`Mar. 6,2001
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`Sheet 32 of 37
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`US 6,197,696 B1
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`F1g.32(a)
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`
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`605A
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`603
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`602
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`601
`
`600
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`Fig.32(b)
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`608
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`600
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`601
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`612
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`Fig.32(c)
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`513
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`Mar. 6,2001
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`Sheet 33 of 37
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`US 6,197,696 B1
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`656
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`655
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`654
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`223
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`651
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`650
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`657
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`655
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`Fig. 33 (6)
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`651
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`650
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`Sheet 34 of 37
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`US 6,197,696 B1
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`658
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`655
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`Fig.34(b)
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`F1g.34(c)
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`Mar. 6,2001
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`Sheet 35 of 37
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`US 6,197,696 B1
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`Fig.35(a)
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`.\\.\\\\\\1
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`Fig. 35 (b)
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`662
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`663
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`F1g.35(c)
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`Sheet 36 of 37
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`US 6,197,696 B1
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`Fig. 36
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`MASK PATTERN(559)
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`SECOND RESIST PATTERN
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`(560)
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`
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`OPENINGS FOR
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`FORMING CONTACT HOLES
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`OPENINGS FOR
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`FORMING INTERCONNECTS
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`Mar. 6, 2001
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`Sheet 37 of 37
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`US 6,197,696 B1
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`.3.W6.63no
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`US 6,197,696 B1
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`1
`METHOD FOR FORMING-
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`INTERCONNECTION "STRUCTURE
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`BACKGROUND OF THE INVENTION
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`The present invention relates to 3. method for forming an
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`interconnection structure in a semiconductor integrated cir-
`cuit.
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`integrated within a single
`As the number of devices,
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`semiconductor integrated circuit, has been tremendously-
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`increasirtg these days, wiring delay has also been increasing
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`noticeably. This is because the larger the number of devices
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`integrated, the larger line-to-line capacitance (i.e., parasitic
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`capacitance between metal interconnects), thus interfering
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`with the performance irnprcvemerrt of a semiconductor
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`integrated circuit. The wiring delay is soacalled “RC delay”,
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`which is proportional to the product of the resistance of
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`metal interconnection and the line-to-line capacitance.
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`In other words, to reduce. the wiring delay, either the
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`resistance of metal interconnection or the line-to-line capaci-
`tance should be reduced.
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`In order to reduce the interconnection resistance, IBM
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`Corp, Motorola, Inc., etc. have reported semiconductor
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`integrated circuits using copper, not aluminum alloy, "as a
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`material for metal interconnects. A copper material has a
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`specific resistance about two-thirds as high as that of an
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`aluminum alloy material. Accordingly, in -accordance with
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`simple calculation, the wiring delay involved with the use of
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`a copper material for metal
`interconnects can be about
`two—thirds of that involved with the use of an alurninum
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`alloy material therefor. That is to say, the operating speed
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`can be increased by about 1.5 times.
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`integrated within a
`However,
`the number of devices,
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`single semiconductor integrated circuit, is expected to fur-
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`ther increase" by leaps and bounds from now on,
`thus
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`increasing the wiring delay considerably. Therefore, it is
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`concerned that even the use of copper as an alternate metal
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`interconnection material would not be able to catch up with
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`such drastic increase. Also, the specific resistance of copper
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`as a metal interconnection material is just a little bit higher
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`than, but almost equal to, that of gold or silver. Accordingly,
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`even if gold or silver is used instead of copper as a metal
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`interconnection material, the wiring delay can be reduced
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`only slightly.
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`Under these "circumstances, not only reducing intercon-
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`nection resistance but also suppressing 1ine—to'~liue capaci-
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`tance play a key role in further increasing the number of
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`devices that can be integrated within a single semiconductor
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`integrated circuit. And the relative dielectric constant of an
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`interlevel insulating film should be reduced to suppress the
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`line-to-line capacitance. Asilicon dioxide film has hereto-
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`fore been used as a typical material for an interlevel insu-
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`lating "film. The relative dielectric constant of a silicon
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`dioxide film is, however, about 4 to about 4.5. Thus, it would
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`be difficult to apply a silicon dioxide film to a semiconductor
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`integrated circuit incorporating an even larger number of
`devices.
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`In order to solve such a problem, fluorine-doped silicon
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`dioxide film, low-dielectric~constant spin-on-glass (SOG)
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`film, organic polymer film and so on have been proposed as
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`alternate interlcvel insulating films with respective relative
`dielectric constants "smaller than that of a silicon dioxide
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`film.
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`10
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`15
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`25
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`30
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`35
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`45
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`50
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`60
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`The relative dielectric constant of a fluorine-doped silicon
`dioxide film is about 3.3 to about 3.7, which is about 20
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`percent lower than that of a conventional silicon dioxide
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`2
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`film. Nevertheless-,_ a fiuor1'ne~doped silicon dioxide film is
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`highly hygroscopic, and easily absorbs water in the air,
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`resulting" in various problems in practice. For ‘example, when
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`the fluorine-doped silicon dioxide film absorbs water, Si0.H
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`groups, having a high relative dielectric constant, are intro-
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`duced into the film. As a result,
`the relative dielectric
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`constant of the fluorine-doped silicon dioxide fi_lm adversely
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`increases, or the SiOH groups react with the water during a
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`heat treatment to release H20 gas. In addition, fluorine free
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`radicals, contained in the fluorine-doped silicon dioxide
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`film, segregate near the surface thereof during a heat treat-
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`ment _and react with Ti, contained in a TiN layer formed
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`thereon as an adhesion layer, to form a TiF film, which easily
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`peels ofi.
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`An HSQ (hydrogen silscsquioxane) film, composed of Si,
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`O and H atoms,
`is_ an exemplary low-dielectric-constant
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`SOG film. In the I-ISO film, the number of the H atoms is
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`about two-thirds of that of the 0 atoms. However, the I-130
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`film releases a larger amount-of water than a conventional
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`silicon dioxide film. Accordingly, since it is difiicult to. form
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`a buried interconnection line in the H80 film, a patterned
`metal film should be formed as metal interconnects on the
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`H50 film.
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`Also-, since the HSQ film cannot adhere so strongly to
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`metal interconnects, a CVD oxide film should be formed
`between the metal
`in'te_rconne:cts and the H30 film to
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`improve the adhesion therebetween. I-Iovvever,
`in such a
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`the CVD oxide film is formed on the metal
`case,
`it‘
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`interconnects, then the substantial line~to~line capacitance is
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`equal to the serial capacitance formed by the H30 and CVD
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`films. This is because the CVD oxide film with a high
`dielectric constant exists between the metal interconnects.
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`Accordingly, the resulting 1ine'—to—1_i_ne capacitance is larger
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`as compared with using the HS_Q film alone.
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`An organic polymer film, as well as the 1ow~'die1ectric~
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`constant SOG film, cannot adhere“ strongly to metal
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`interconnects, either. Accordingly, a CVD oxide film should
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`be formed as an adhesion layer between the metal intercon-
`nects and the organic polymer film, .t0o.
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`Moreover, an etch rate, at which an organic polymer film
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`is etched, is approximately equal to an -ash rate, at which a
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`resist pattern is ashed with oxygen plasma. Accordingly, -a
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`usual resist application process is not applicable in such a
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`situation, because the organic polymer film is likely to be
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`damaged during ashing and removing the‘ resist p_attern.
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`Therefore, a proposed alternate process includes:.foI’rr1ing. a
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`CVD oxide film on an organic polymer film; forming a resist
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`film on the CVD oxide film; and.then etching the resist film
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`using the CVD oxide film as an etch stopper, or a protective
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`filrn.
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`However, during the step of forming the CVD oxide film
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`on the organic polymer film,
`the surface of the organic
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`polymer film is exposed to a reactive gas containing oxygen.
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`Accordingly, the organic polymer film" reacts-with oxygen to
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`take in polar groups such as carbonyl groups and lretone
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`groups. As a result, the relative dielectric constant of the
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`organic polymer film disadvantageously increases.
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`Also,
`in forming inlaid copper
`in'terconn'ects in the
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`organic polymer film, a 'I‘.iN adhesion layer, for example,
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`should be formed around wiring grooves formed in the
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`organic polymer film, because the organic polymer film
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`cannot adhere strongly to the metal interconnects. However,
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`since the 'l"iN film has a high resistance,
`the effective.
`cross-sectional area of the metal interconnects decreases.
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`Consequently, the intended eifect attainable by the use of the
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`copper lines, i.e., reduction in resistance, would be lost.
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`Page 45 of 388
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`Page 45 of 388
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`US 6,197,696 B1
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`3
`SUMMARY OF THE INVENTION
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`An object of the present invention is providing a method
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`for forming an interconnection structure in which an insu-
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`lating film with a low dielectric constant -can be formed by
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`an ordinary resist application process.
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`A first method for forming an interconnection structure.
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`according to the present invention includes the steps of: a)
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`forming a first insulating film over lower-level metal inter-
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`connects; b) forniing a second insulating film, having a
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`diflferent composition than that of the first" insulating film,
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`over the first insulating film; c) forming a third insulating
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`film, having a different composition than that of the second
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`insulating film, over the second insulating film; d) forming
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`a thin film over the third insulating film; e) forming a first
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`resist pattern, having a plurality of openings for forming
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`wiring grooves, on the thin film; I) etching the thin film
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`using the first resist pattern ‘as a mask, thereby forming a
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`mask pattern but of the thin film" to have the openings for
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`forming wiring grooves; E) forming a second resist pattern,
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`having a plurality of opening for forming contact holes, on
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`the third insulating film; h) dry-etching the third insulating
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`film under such conditions that the third insulating film and
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`the first and "second resist patterns are etched at a relatively
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`high rate and that the second insulating film is etched at a
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`relatively low rate, thereby patterning the third insulating
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`film to have the openings for forming contact holes and
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`removing the first and second resist patterns either entirely
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`or partially with respective lower parts thereof "left;
`i)
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`dry-etching the second insulating film using the patterned
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`third insulating film as.-a mask under such conditions that the
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`second insulating film is etched at a relatively high