United States Patent [19]
`Yu et al.
`
`US006103616A
`[11] Patent Number:
`[45] Date of Patent:
`
`6,103,616
`Aug. 15,2000
`
`[54] METHOD TO MANUFACTURE DUAL
`DAMASCENE STRUCTURES BY UTILIZING
`SHORT RESIST SPACERS
`
`6,037,664
`
`3/2000 Zhao et al. ............................ .. 257/758
`
`FOREIGN PATENT DOCUMENTS
`
`[75] Inventors: Allen .
`Sch0
`Grov
`
`Fremon '
`Jose; P
`Calif.
`
`omas C.
`. Ste?'an, Elk
`
`[73] Assignee: Advan
`Sunny
`
`Micro Devices, Inc.,
`Calif.
`
`410209273
`
`8/1998 Japan .
`
`Primary Examiner—Carl Whitehead, Jr.
`Assistant Examiner—Jamie L. Davis
`Attorney, Agent, or Firm—H. Donald Nelson
`
`[57]
`
`ABSTRACT
`
`[21] Appl. No.: 09/136,867
`[22]
`Filed:
`Aug. 19, 1998
`
`[51] In .
`
`.7
`
`............................ .. H01L 21/4763
`
`[52] U. .
`
`. ........................ .. 438/622; 438/618; 438/
`438
`[58] Field of Search ................................... .. 438/618, 622,
`438/634, 637, 671, 672, 675, 638
`
`'
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,635,423
`5,741,626
`5,916,823
`6,037,213
`
`6/1997 Huang et al. ......................... .. 438/638
`4/1998 Jain et al.
`430/314
`6/1999
`et al.
`438/738
`3/2000
`etal. ............................ .. 438/253
`
`'
`
`acturing semiconductor devices Wherein
`A method of
`d semiconductor device having a ?rst
`a partially c
`f interlayer dielectric and a ?rst and
`and second
`er has the second etch stop layer masked
`second etch sto
`etch pattern having dimensions of the
`and et
`Wit
`trench
`cture to be formed in the second interlayer
`dielectric. Th
`cond layer dielectric and ?rst etch stop
`layer are then
`ked and etched With an etch pattern having
`dimension
`the via structure to be form
`'n the ?rst
`interlayer '
`ctric. The remaining portion
`the hoto
`t1ons
`layer
`resist is removed and exposed por '
`of the sec
`of interlay
`ielectric and
`?rst lay
`'nterlayer
`the
`en etched simultaneously.
`dielectric a
`' structure
`and trench structure are then simultaneou
`d With a
`conductive material.
`
`6 Claims, 6 Drawing Sheets
`
`116
`
`110
`
`108
`
`106
`
`110
`
`108
`
`%////////////////////////////%//2
`
`104
`
`102
`
`TSMC Exhibit 1011
`
`Page 1 of 10
`
`

`

`::=:=:m:m ‘_
`
`'
`
`:
`
`1:t=:= =1‘
`
`‘>I‘t«'t5§:3' 12* =1§'11'
`
`‘i
`
`' 1'
`
`it =13
`
`= 13” E 1?.
`
`: " " "'=§::5"'===§5=:5="=='
`
`1 10
`
`II
`I
`-I
`== : :a"""=::a::':s:":a:s'1'2
`3 ....n:.s=I-:=si::=:5=s'5 ==
`‘ " =.
`--=====:===-:== '
`------------
`-=-
`'.. m“
`--
`-
`-
`--
`n
`..
`.
`:.
`:
`::::::=:=::-:::=.......................
`-
`.'::':::";: A '.
`§§!§§§§!§§§!"!§§§§§§§!¥3!!§E!§!§!§§!!!§EEE§E!!|i!§!2§i!iiiii..ZZI2iE'§§§i§i§§§'s§'-i§E55§i5i§‘=§=§§"E"E‘E5E“;Egggiifiiiiiifiiifiggiéi
`
`Page 2 of 10
`
`

`

`K
`
`110
`
`' " "i"'
`:::::E: 3-".
`ggggggggggggggfiggfigigigggggggiauséiiiiaiiissnfsiggfiasa
`
` ::n:::::::::::---'-- --
`
`J?’ ""'i"""i5 if '3i"""""""""""""""'
`
`'E'Z"EE!'I:E!:55EE5!§E
`
`
`
`1:
`
`Page 3 of 10
`
`

`

`1::
`“°j
`
`K ....::::"=' 17
`
`I-=EE=.EE!EEEE=EEEEEEEEEEE=EEi==“i“=‘=='*i""""
`
`L:
`5:5;5=:...........
`«=
`11
`:::::::'."" """":: "
`. ..
`'5!
`;;;;;§§§5;5§5i;:55§§j€§=i i .2.....i H -5!‘ §=;§ig§ggggggifiiiiiisa5Iszziiassafis5E55525:22asisaaaésss§ea§a§§E:s'::a55§!§!§§§§§§§
`
`Dv
`
`1 10
`
`T
`
`' —1%:1:8
`
`:
`..n
`.u .:.n.. nun .I":'l"'
`‘ ' :
`§§§%“5=?%§%%iiiiiEfii!!!!:tE**i**@%¥§‘53§‘§
`
`I: '
`
`53E3E3E?E3EIEIE35?EIE7§=Si3E3EIEi¢EtEii=3=E=35=E
`
`EIE3I3E1EiiiIC35E‘E33Z32I‘EIE5E3§§"E35E3it553E55355E55555:555E5E3E53555:5E5:553E;E3E5E;555{E555EEEEE;E333E5E353?323E55;:E53:33E-33?}333E=.I3.§I§§:§:§E§E§:§:§:§:5:_
`
`i
`"i§‘§§!§fi§¥3¥§55‘§%§§§§i3*5*5" "
`
`1 10
`
`.n
`
`H4:
`.‘i
`
`”53-3‘5-5'"‘
`i‘iEEEEEF:
`
`Page 4 of 10
`
`

`

`1;?% 1 10
`3::
`E:
`
`ififiifiiiiiiiififiifiiiiififiiiiififiiiiiiiifi J
`
`-nu-nun:
`I
`,
`-
`I
`Inu:
`------IL3-3--------------
`
`E E
`
`.
`
`..
`
`""""'I:=::H:IHH
`:53}:nnnnnnnnnnnnnn
`
`IIIJ-In-auu-nhu-uE="":3nuIu-- nu-u--u
`'"“::==:::=:=::""""""" u--mu In
`.2
`...
`
`can In
`.. .
`
`. 4.
`
`2
`
`izé
`
`/
`
`Page 5 of 10
`
`

`

`U.S. Patent
`
`Aug. 15,2000
`
`Sheet 5 0f6
`
`6,103,616
`
`II
`
`=
`
`DY
`
`Em _; #51
`
`...__.._...._...._u-.. "WWW ......... ,,
`
`Page 6 of 10
`
`

`

`U.S. Patent
`
`Aug. 15,2000
`
`Sheet 6 0f 6
`
`6,103,616
`
`6/6
`
`118
`
`FIGURE 1K
`
`118
`
`2 O 1
`
`2:5..3
`
`. . .
`
`. 0.
`
`FIGURE 1L
`
`Page 7 of 10
`
`

`

`6,103,616
`
`1
`METHOD TO MANUFACTURE DUAL
`DAMASCENE STRUCTURES BY UTILIZING
`SHORT RESIST SPACERS
`
`BACKGROUND OF THE INVENTION
`
`10
`
`15
`
`25
`
`1. Field of the Invention
`This invention relates generally to a method of manufac
`turing high density, high performance semiconductor
`devices that have dual damascene interconnects. More
`speci?cally, this invention relates to a method of manufac
`turing high density, high performance semiconductor
`devices that have dual damascene structures that are formed
`With a reduced number of masks.
`2. Discussion of the Related Art
`The increased demand for higher performance semicon
`ductor devices has required more complex process technolo
`gies and materials to be utiliZed in the manufacture of
`semiconductor integrated devices. One Way to increase the
`performance of a semiconductor integrated device such as a
`microprocessor is to reduce the gate Width of the ?eld effect
`transistors in the device in order to achieve a high internal
`clock speed for the microprocessor. The reduced gate Widths
`have increased the performance signi?cantly, hoWever, the
`interconnect structure of the microprocessor has proved to
`be a roadblock to further increase in performance. This is
`because as increased performance is required, more transis
`tors require more Wiring in the interconnect structure. The
`increased density of the Wiring can result in a decrease in
`performance relating to RC delays. To counteract the deg
`radation in performance due to the RC delays, additional
`layers, commonly referred to as metal layers, in Which
`interconnects are formed are manufactured in the semicon
`ductor device in order to separate the Wiring in both the
`vertical and horiZontal directions. These requirements have
`necessitated the development of novel approaches in the
`methods of forming interconnections that not only integrate
`?ne geometry de?nition but also can be ef?ciently imple
`mented into the manufacturing process.
`One method of forming a trench is a method knoWn as the
`damascene process, Which comprises forming a trench by
`masking and etching techniques and subsequent ?lling of the
`trench With the desired conductive material. The damascene
`process is a useful method for attaining the ?ne geometry
`45
`metalliZation required for advance semiconductor devices. A
`dual damascene process is a tWo step sequential mask/etch
`process to form a tWo level structure such as a via in a ?rst
`metal layer connected to a metal line (in a trench) in a second
`metal layer.
`The typical dual damascene process is to mask and etch
`a ?rst layer of interlayer dielectric in the structure to form
`vias and then ?ll the vias With a conductive material. Once
`the vias have been formed, the neXt step is to form a second
`layer of interlayer dielectric on the ?rst metal layer, mask
`and etch the second layer of interlayer dielectric to form
`trenches, and then ?ll the trenches With a conductive mate
`rial. As is knoWn in the semiconductor manufacturing art,
`the vias are in electrical contact With selected trenches to
`form a desired interconnect pattern, Which forms an elec
`trical circuit.
`Each mask and etch step increases the total time and
`increases the complexity of the manufacturing process as
`Well as potentially increasing the number of defects.
`Therefore, What is needed is a manufacturing process for
`the forming of dual damascene structures that has a reduced
`number of mask and etch steps.
`
`35
`
`55
`
`65
`
`2
`SUMMARY OF THE INVENTION
`According to the present invention, the foregoing and
`other objects and advantages are obtained by a method of
`manufacturing semiconductor devices Wherein a partially
`completed semiconductor device having a ?rst and second
`layer of interlayer dielectric and a ?rst and second etch stop
`layer has the second etch stop layer masked and etched With
`an etch pattern having dimensions of the trench structure to
`be formed in the second interlayer dielectric. The second
`layer dielectric and the ?rst etch stop layer are then masked
`and etched With an etch pattern having dimensions of the via
`structure to be formed in the ?rst interlayer dielectric. The
`remaining portions of the photoresist is removed and
`eXposed portions of the second layer of interlayer dielectric
`and the ?rst layer of interlayer dielectric are then etched
`simultaneously. The via structure and trench structure are
`then simultaneously ?lled With a conductive material. The
`?rst etch stop layer is formed from a material such as SiON,
`Si3N4 or other nitride material. The second etch stop layer,
`Which also served as a hard mask, is formed from a material
`such as SiON, Si3N4, TiN or other nitride material. The
`layers of interlayer dielectric is formed from a loW constant
`dielectric material such as SiO2. The conductive material is
`selected from a material selected from tungsten, aluminum
`and copper.
`The described method thus provides a method of manu
`facturing semiconductor devices Wherein the number of
`masking steps is reduced and the ?nal etch step of the ?rst
`and second layers of interlayer dielectric are etched simul
`taneously.
`The present invention is better understood upon consid
`eration of the detailed description beloW, in conjunction With
`the accompanying draWings. As Will become readily appar
`ent to those skilled in the art from the folloWing description,
`there is shoWn and described an embodiment of this inven
`tion simply by Way of illustration of the best mode to carry
`out the invention. As Will be realiZed, the invention is
`capable of other embodiments and its several details are
`capable of modi?cations in various obvious aspects, all
`Without departing from the scope of the invention.
`Accordingly, the draWings and detailed description Will be
`regarded as illustrative in nature and not as restrictive.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The novel features believed characteristic of the invention
`are set forth in the appended claims. The invention itself,
`hoWever, as Well as a preferred mode of use, and further
`objects and advantages thereof, Will best be understood by
`reference to the folloWing detailed description of an illus
`trative embodiments When read in conjunction With the
`accompanying draWings, Wherein:
`FIG. 1A shoWs a portion of a partially completed semi
`conductor device shoWing a ?rst layer of interlayer dielectric
`formed on a semiconductor substrate in Which active devices
`have been formed, a ?rst etch stop layer formed on the ?rst
`layer of interlayer dielectric, a second layer of interlayer
`dielectric formed on the ?rst etch stop layer, a second etch
`stop layer formed on the second layer of interlayer dielectric
`and a ?rst layer of photoresist formed on the second etch
`stop layer;
`FIG. 1B shoWs the partially completed semiconductor
`device shoWn in FIG. 1A With the layer of photoresist
`patterned and etched;
`FIG. 1C shoWs the partially completed semiconductor
`device shoWn in FIG. 1B after an etch process to remove a
`portion of the second etch stop layer;
`
`Page 8 of 10
`
`

`

`6,103,616
`
`3
`FIG. 1D shows the partially completed semiconductor
`device shoWn in FIG. 1C With the remaining portion of the
`?rst layer of photoresist removed;
`FIG. 1E shoWs the partially completed semiconductor
`device shoWn in FIG. 1D With a second layer of photoresist
`formed on the structure shoWn in FIG. 1D;
`FIG. 1F shoWs the partially completed semiconductor
`device shoWn in FIG. 1E With the second layer of photoresist
`patterned and etched;
`FIG. 1G shoWs the partially completed semiconductor
`device shoWn in FIG. 1F after an etch process to remove a
`portion of the second layer of interlayer dielectric;
`FIG. 1H shoWs the partially completed semiconductor
`device shoWn in FIG. 1G after an etch process to remove a
`portion of the ?rst etch stop layer;
`FIG. II shows the partially completed semiconductor
`device shoWn in FIG. 1H With the remaining portions of the
`second layer of photoresist removed;
`FIG. 1] shoWs the partially completed semiconductor
`device shoWn in FIG. 11 after an etch process that etches a
`portion of the second interlayer dielectric and a portion of
`the ?rst interlayer dielectric;
`FIG. 1K shoWs the partially completed semiconductor
`device shoWn in FIG. 1] With the remaining portions of the
`second etch stop layer removed and the exposed portions of
`the ?rst etch stop layer removed; and
`FIG. IL shoWs the partially completed semiconductor
`device shoWn in FIG. 1K With the etched portion of the
`structure ?lled With a conductive material.
`
`DETAILED DESCRIPTION
`
`4
`second etch stop layer 110 is formed on the surface of the
`second layer of interlayer dielectric 108. The second etch
`stop layer 110 can be formed from a nitride material such as
`silicon oxynitride (SiON), silicon nitride (Si3N4) and tita
`nium nitride (TiN). A ?rst layer of photoresist 112 is formed
`on the surface of the etch stop layer 110.
`FIG. 1B shoWs the partially completed semiconductor
`device 100 as shoWn in FIG. 1A With the layer of photoresist
`112 patterned and etched. All etch process discussed herein
`are anisotropic etch processes, that is, etch processes that are
`directional as opposed to isotropic etch processes that etch
`in all directions. In addition, the etch processes and chem
`istries are Well knoWn in the art and Will not be discussed as
`each etch process can be easily determined by a person of
`ordinary skill in the semiconductor manufacturing art. The
`dimensions of the etched portion 114 are the dimensions of
`a trench structure DT that Will be formed in the second layer
`of interlayer dielectric 108. The etch process exposes a
`portion of the second etch stop layer 110 having dimensions
`of the trench structure DT to be formed in the second layer
`of interlayer dielectric 108.
`FIG. 1C shoWs the partially completed semiconductor
`device 100 as shoWn in FIG. 1B after an etch process to etch
`the exposed portion of the second etch stop layer 110.
`FIG. 1D shoWs the partially completed semiconductor
`device 100 as shoWn in FIG. 1C With the remaining portions
`of the layer of photoresist 112 removed.
`FIG. 1E shoWs the partially completed semiconductor
`device 100 as shoWn in FIG. 1D With a second layer of
`photoresist 116 formed on the surface of the structure as
`shoWn in FIG. 1D.
`FIG. 1F shoWs the partially completed semiconductor
`device 100 as shoWn in FIG. 1E With the second layer of
`photoresist 116 patterned and etched. The dimensions of the
`etched portion 118 are the dimensions of a via structure DV
`that Will be formed in the ?rst interlayer dielectric 104. The
`etch process exposes a portion of the second layer of
`interlayer dielectric 108 having the dimensions of the via
`structure DV that Will be formed in the ?rst interlayer
`dielectric 104.
`FIG. 1G shoWs the partially completed semiconductor
`device 100 as shoWn in FIG. 1F after an etch process to etch
`the second layer of interlayer dielectric 108. The etch
`process etches the second layer of interlayer dielectric 108
`doWn to the surface of the ?rst etch stop layer 106. The etch
`process exposes a portion of the ?rst etch stop layer 106
`having the dimensions of the via structure DV to be formed
`in the ?rst interlayer dielectric 104.
`FIG. 1H shoWs the partially completed semiconductor
`device 100 as shoWn in FIG. 1G after an etch process to etch
`the exposed portion of the ?rst etch stop layer 106. The etch
`process exposes a portion of the ?rst layer of interlayer
`dielectric 104 having the dimensions of the via structure DV
`to be formed in the ?rst interlayer dielectric 104.
`FIG. II shows the partially completed semiconductor
`device 100 as shoWn in FIG. 1H With the remaining portions
`of the layer of photoresist 116 removed. The removal of the
`layer of photoresist 116 exposes portions 120 of the second
`layer of interlayer dielectric 108. In addition, the removal of
`the second layer of photoresist 116 reduces the aspect ratio,
`the aspect ratio being de?ned as the ratio of the depth
`structure to be etched and the Width of the structure to be
`etched. The reduction of the aspect ratio improves the aspect
`ratio dependence etch (ARDC), also knoWn as stop etch of
`the via into the ?rst layer of interlayer dielectric. In this case,
`the ARDC Would stop the etch process of the ?rst layer of
`
`10
`
`15
`
`25
`
`35
`
`45
`
`Reference is noW made in detail to speci?c embodiments
`of the present invention Which illustrate the best mode
`presently contemplated by the inventors for practicing the
`invention.
`FIGS. 1A—1K shoW a method to form dual damascene
`interconnects in accordance With the present invention. FIG.
`1A shoWs a partially completed semiconductor device 100.
`The partially completed semiconductor device 100 is formed
`in a semiconductor substrate on and in Which active devices
`(not shoWn) are formed. The substrate and active devices are
`indicated generally at 102 and Will not be discussed further
`since the methods of forming active devices in and on a
`semiconductor substrate are Well knoWn in the semiconduc
`tor manufacturing art and such methods of formation are not
`a part of the present invention. The surface of the substrate
`102 is planariZed and serves as a uniform ?at surface on
`Which to form further structures on the surface of the
`semiconductor substrate 102. A ?rst layer of interlayer
`dielectric 104 is formed on the planariZed surface of the
`semiconductor substrate 102. The ?rst layer of interlayer
`dielectric 104 is typically formed from a loW dielectric
`constant material such as silicon dioxide (SiOZ). The top
`surface of the interlayer dielectric 104 is planariZed to serve
`as a ?at surface for the formation of further layers. A
`boundary layer of etch stop layer 106 is formed on the
`surface of the interlayer dielectric 104. The etch stop layer
`106 is typically formed from a nitride material such as
`silicon oxynitride (SiON) or silicon nitride (Si3N4). The
`purpose of the etch stop layer 106 is to stop a subsequent
`etch process from etching into the ?rst interlayer dielectric
`104. Asecond layer of interlayer dielectric 108 is formed on
`the surface of the ?rst etch stop layer 106. The second layer
`of interlayer dielectric 108 is also formed from a loW
`dielectric constant material such as silicon dioxide (SiOZ). A
`
`55
`
`65
`
`Page 9 of 10
`
`

`

`6,103,616
`
`5
`interlayer dielectric 104 before the etch process reached the
`surface of the semiconductor substrate 102. Because the etch
`process to etch an oXide is a physical type of etch, it is
`primarily an ion bombardment that generates a large amount
`of polymers. The large amount of polymers buildup on the
`sideWalls as the etch process proceeds. If the aspect ratio is
`too large, the polymer buildup can stop the etch process
`preventing the complete opening of the via. This Would
`result in an open circuit and the circuit Would be inoperative.
`One method that has been used is to increase the poWer
`during the etch process. HoWever, the increase in poWer Will
`consume more photoresist and generate more polymers.
`FIG. 1] shoWs the partially completed semiconductor
`device 100 as shoWn in FIG. 11 after an etch process that
`removes eXposed portions 120 of the second layer of inter
`layer dielectric 108 and the eXposed portion of the ?rst layer
`of interlayer dielectric 104. The etch process etches the
`second layer of interlayer dielectric 108 With dimensions of
`the trench structure DT and etches the ?rst layer of interlayer
`dielectric 104 With dimensions of the via structure DV.
`FIG. 1K shoWs the partially completed semiconductor
`device 100 as shoWn in FIG. 1] With the remaining portions
`of the second etch stop layer 110 removed and the eXposed
`portions of the ?rst etch stop layer 106 removed.
`FIG. 1L shoWs the partially completed semiconductor
`device 100 as shoWn in FIG. 1K With the via structure and
`trench structure ?lled With a conductive material such as
`tungsten, aluminum or copper. As is knoWn in the semicon
`ductor manufacturing art, a barrier layer can be formed on
`the Walls of the etched via structure and trench structure 118.
`The barrier layer can be formed from one of several mate
`rials including TiN (titanium nitride), TaN (tantalum nitride)
`or WZN (tungsten nitride).
`In summary, the results and advantages of the method of
`the present invention can noW be fully realiZed. The bene?ts
`of the present invention include the folloWing:
`1. The number of process steps is reduced;
`2. Interface problems betWeen the via structure and trench
`structure are reduced because the via structure and
`trench structure are formed simultaneously; and
`3. Yields are improved because the number of steps is
`reduced thus reducing the potential defects.
`The foregoing description of the embodiment of the
`invention has been presented for purposes of illustration and
`description. It is not intended to be exhaustive or to limit the
`invention to the precise form disclosed. Obvious modi?ca
`tions or variations are possible in light of the above teach
`ings. The embodiment Was chosen and described to provide
`the best illustration of the principles of the invention and its
`practical application to thereby enable one of ordinary skill
`in the art to utiliZe the invention in various embodiments and
`With various modi?cations as are suited to the particular use
`contemplated. All such modi?cations and variations are
`Within the scope of the invention as determined by the
`appended claims When interpreted in accordance With the
`breadth to Which they are fairly, legally, and equitably
`entitled.
`What is claimed is:
`1. A method of manufacturing a semiconductor device,
`the method comprising:
`
`10
`
`15
`
`25
`
`35
`
`45
`
`55
`
`6
`forming a ?rst layer of interlayer dielectric on a surface of
`a semiconductor substrate that contains active semi
`conductor devices;
`forming a ?rst etch stop layer on a surface of the ?rst layer
`of interlayer dielectic;
`forming a second layer of interlayer dielectric on a surface
`of the ?rst etch stop layer;
`forming a second etch stop layer on a surface of the
`second layer of interlayer dielectric;
`forming a ?rst layer of photoresist on a surface of the
`second etch stop layer;
`etching the ?rst layer of photoresist doWn to the surface
`of the second etch stop layer With an etch pattern
`having dimensions of a trench structure that Will be
`formed in the second layer of interlayer dielectric
`Wherein a portion of the second layer of interlayer
`dielectric is eXposed having dimensions of the trench
`structure;
`removing the ?rst layer of photoresist;
`forming a second layer of photoresist on the surface of the
`second etch stop layer and the eXposed portion of the
`second layer of interlayer dielectric;
`etching the second layer of photoresist doWn to the
`surface of the second layer of interlayer dielectric With
`an etch pattern having dimensions of a via structure to
`be formed in the ?rst layer of interlayer dielectric;
`etching the second layer of interlayer dielectric doWn to
`the surface of the ?rst etch stop layer eXposing a region
`of the ?rst etch stop layer having dimensions of the via
`structure to be formed in the ?rst layer interlayer
`dielectric;
`etching the exposed portions of the ?rst etch stop layer;
`removing the second layer of photoresist eXposing por
`tions of the second layer of interlayer dielectric; and
`etching the eXposed portions of the second layer of
`interlayer dielectric and the ?rst layer of interlayer
`dielectric doWn to the surface of the semiconductor
`substrate eXposing a region of the semiconductor sub
`strate having dimensions of the via structure to be
`formed.
`2. The method of claim 1 further comprising ?lling the via
`structure formed in the ?rst layer of interlayer dielectric and
`the trench structure in the second layer of interlayer dielec
`tric With a conductive material.
`3. The method of claim 2 Wherein the conductive material
`is selected from the group consisting of aluminum, tungsten
`and copper.
`4. The method of claim 3 Wherein the ?rst etch stop layer
`is formed from a material selected from the group consisting
`of SiON and Si3N4 and the second etch stop layer is formed
`from a material selected from the group consisting of SiON,
`Si3N4 and TiN.
`5. The method of claim 4 Wherein the ?rst and second
`layers of interlayer dielectric are formed from a loW dielec
`tric constant material.
`6. The method of claim 5 Wherein the ?rst and second
`layers of interlayer dielectric are formed from silicon dioX
`ide.
`
`Page 10 of 10
`
`