`
`United States Patent
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`
`Jain et al.
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`
`
`[19]
`
`[54] METHOD FOR FORMING A DIELECTRIC
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`TANTALUM NITRIDE LAYER AS AN ANTI-
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`REFLECTIVE COATING (ARC)
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`[75]
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`Inventors: Ajay Jain; Kevin Lucas. both of
`Austin, Tex.
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`_
`[73] Assignee: Motorola, Inc., Schaumburg, lll.
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`
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`Appl. No.: 632,209
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`
`
`APB 15: 1996
`[22] Filed:
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`.
`_I‘.__ G03F 7/00, HOIL 21/314
`Int CL6
`__.I _
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`U.s.c1. .................. 430/314; 430/311; 430/312;
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`430/316; 430/317; 433/626; 433/633; 433/634;
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`438/636; 433/692; 433/694; 433/703; 433/735;
`216/13
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`Field of Search
`430/311. 312,
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`.
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`430/3
`, 56/652.1, 661.11;
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`437/229, 195; 216/18; 438/598, 626, 634,
`636, 637, 638. 618, 703. 692, 694, 126,
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`133. 355, 389. 785. 633
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`.
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`References Cited
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`US‘ PATENT DOCUMENTS
`
`
`5/1975 Kakihama etal.
`3,884,698
`
`
`
`2/1983 Kaneki et al.
`..
`4,374,912
`
`
`
`
`2/1989 011110 ct 81.
`4.804.606
`.
`
`
`
`
`
`
`
`2/1992
`59919244
`9/1995 W00 5‘ 31' "
`5451543
`
`
`
`
`6/1997
`5’635’423
`
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`
`7/1995 European Pat. Oif. .
`066l736Al
`
`
`
`
`
`Japan .............................. .. FO3G 7/06
`60-32980
`2/1985
`
`
`
`
`
`
`H0lL 27/04
`60-55657
`3/1985
`Japan
`
`
`
`
`HOIL 21/30
`63-76325
`4/1988
`
`
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`
`
`4/1992
`Japan ............................. HOIL 27/04
`4—124869
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`433/637
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`
`
`
`HllllllllllllIll||||l||||l||ll|l|||lIlllllllllllllllllllllllllllllllllllll
`
`
`USOO574l626A
`[11] Patent Number:
`
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`
`
`
`
`[45] Date of Patent:
`
`5,741,626
`
`
`Apr. 21, 1998
`
`
`
`
`OTHER PUBLICATIONS
`
`
`
`
`Dan C. Anderson et al., “The Great Static Protection
`
`
`
`
`
`
`
`Debate”. Australian Electronics Engineering 17(10):52—5
`
`
`
`
`
`
`
`
`Oct. 1984, 5 pgs.
`Yasushiro Fukuda et 111., “Electrical Overstress/Electrostatic
`
`
`
`
`
`Dischar e", VLSI BSD Phenomenon and Protectio ——l988
`
`
`
`
`
`
`
`EDS/ESgD Symposium Proceedings’ pp_ 223_234_ n
`
`
`
`
`
`“Dual Darnascene: A ULSI Wiring Technology,” Kaanta, et
`
`
`
`
`
`
`
`
`
`
`
`
`al.; VMIC Conference, Jun. 11, 1991.
`“Chemical Vapor Deposition of Vanadium, Niobium, and
`
`
`
`
`
`
`
`Tantalum Nitride Thin Films,” Fix, et al.; Chem. Mater, vol.
`
`
`
`
`
`
`5* N°' 5* 1993'
`
`
`
`
`
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`
`
`Primary E“1'"*'"‘=’—‘?Cm“Id F} C°dd _
`Attamey, Agent, or Fzrm—Ke1th E. Witek
`
`
`
`
`ABSTRACT
`
`
`[57]
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`The present invention provides an anti—reflective Ta3N5
`coating which can be used in a dual damascene structure and
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`for I line or G line lithographies. In addition, the Ta3N5
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`coating may also be used as an etch stop and a barrier layer.
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`A dual damascene structure is formed by depositing a first
`dielectric layer (16). A dielectric tantalum nitride layer (18)
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`is deposited on top of the first dielectric layer. A second
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`dielectric layer (20) is deposited on the tantalum nitride
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`layer. A dual damascene opening (34) is etched into the
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`dielectric layers by patterning a first opening portion (26)
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`and a second opening portion (32) using photolithography
`operations. Dielectric tantalum nitride layer (18) serves as an
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`ARC layer during these operations to reduce the amount of
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`reflectance from conductive region (14) to reduce distortion
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`of the photoresist pattern. The use of a dielectric tantalum
`
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`nitride layer as an ARC is particularly suitable for 1 line and
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`G line lithography.
`
`27 Claims, 6 Drawing Sheets
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`40
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`46
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`20
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`1_5
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`13
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`.\\\\\\\\\\\\\\\\\Vrn\N
`T
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`13
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`E
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`TSMC Exhibit 1007
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`Page 1 of 12
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`

`

`U.S. Patent
`
`Apr. 21, 1993
`
`Sheet 1 of 6
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`5,741,626
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`-j
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`FIG2
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`26
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`(10
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`Page 2 of 12
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`

`

`U.S. Patent
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`Apr. 21, 1998
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`Sheet 2 of 6
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`5,741,626
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`510.5
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`,/~20
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` 0
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`W////JAI
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`JZ7]?ZEg;(5: 1000
`
`750
`
`REFLECTIVITY,
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`7‘
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`50.0
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`25.0
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`0.0
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`0.8000
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`0.8250
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`OXIDE THICKNESS
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`(um)
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`0.8500
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`0.8750
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`0.9000
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`Page30f12
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`Page 3 of 12
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`

`

`U.S. Patent
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`Apr. 21, 1993
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`Sheet 3 of 6
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`5,741,626
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`100.0
`
`75.0
`
`REFLECTIVITY,
`7‘
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`50.0
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`25.0
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`0.0
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`0.0000
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`0.0500
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`0.1000
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`0.1500
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`0.2000
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`TA3N5 THICKNESS (pm)
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`FIG. 7
`
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`0.0500
`0.1000
`0.1500
`TASN5 THICKNESS1 (pm)
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`0.2000
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`100.0
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`75.0
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`REFLECTIVITY,
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`7‘
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`50.0
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`25.0
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`0.0
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`0.0000
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`FIG8
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`Page 4 of 12
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`Page 4 of 12
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`

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`'/55
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`/“40
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`54 .\
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`g
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`Page 5 of 12
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`Page 5 of 12
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`

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`U.S. Patent
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`Apr. 21, 1998
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`Sheet 5 of 6
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`5,741,626
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`HG J2
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`/‘ 40
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`g
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`Page 6 of 12
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`

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`U.S. Patent
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`Apr, 21, 1998
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`Sheet 6 of 6
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`5,741,626
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`.\\\\\\\\\\\\\\\\\\\\\\\\\m\\\
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`16
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`18
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`34
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`T F
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`IGZ5
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`Page 7 of 12
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`

`

`
`1
`METHOD FOR FORMING A DIELECTRIC
`
`
`
`
`TANTALUM NITRIDE LAYER AS AN ANTI-
`
`
`
`
`
`
`
`REFLECTIVE COATING (ARC)
`FIELD OF THE INVENTION
`
`
`
`The present invention relates to semiconductor devices in
`
`
`
`
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`
`
`
`
`
`
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`general. and more particularly to semiconductor devices
`
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`having anti-reflective coatings to aid in photolithography
`steps, such as those used to form in a dual damascene
`
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`interconnect structure.
`
`
`BACKGROUND OF THE INVENTION
`
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`The semiconductor industry’s continuing drive toward
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`integrated circuits with ever decreasing geometries, coupled
`. with its pervasive use of highly reflective materials, such as
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`polysilicon, aluminum, and :metal silicides, has lead to
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`increased photolithographic patterning problems. Unwanted
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`reflections from these underlying reflective materials during
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`the photoresist patterning process often cause the resulting
`photoresist patterns to be distorted
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`Anti-reflective coatings (ARCs) have been developed to
`minimize the adverse impact due to reflectance from these
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`reflective materials. In many instances, these ARCs are
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`conductive materials which are deposited as a blanket layer
`on top of metal and simultaneously patterned with the metal
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`to form interconnects. A problem with these ARCs is that
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`many of these materials cannot be used in applications such
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`as dual damascene, wherein the metal layer is not patterned.
`In a dual damascene application, openings are formed in the
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`interlayer dielectric. and the metal is blanketly deposited in
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`those openings and subsequently polished back to form a
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`planar inlaid plug. In such application. the metal layer is
`never etched and therefore, any conductive ARC on top of
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`the inlaid metal would cause the metal plugs to be electri-
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`cally short circuited together through the conductive ARC.
`Some dielectric ARCs are also known. such as silicon rich
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`silicon nitride or aluminum nitride, but a disadvantage with
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`these ARCs is that they are most suitable for deep ultraviolet
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`(DUV) radiation, whereas a vast majority of photolithogra-
`phy steps occur at higher wave lengths such as I-line or
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`G-line where these ARCs are not optimal.
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`Accordingly, there is a need for an improved semicon-
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`ductor manufacturing operation which utilizes an anti-
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`reflective coating that is applicable to the more prevalent
`I-line or G-line lithographies and which can be used in
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`applications, such as dual damascene. which require ARCs
`that are nonconductive and potentially used as a damascene
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`etch stop layer.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
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`FIGS. 1-5 illustrate in cross-section a portion of a semi-
`
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`conductor device having a dual damascene structure utiliz-
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`ing an anti-reflective coating in accordance with one
`embodiment of the present invention.
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`FIG. 6 is an X-y graph illustrating the reflectivity of a dual
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`damascene structure without having an ARC layer present.
`FIG. 7 is an x-y graph illustrating the reflectivity of the
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`same dual damascene structure having a dielect:ric tantalum
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`nitride layer used as an ARC between the first and second
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`dielectric layers of the dual damascene structure.
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`FIG. 8 is an x-y graph illustrating the reflectivity in the
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`dual damascene structure wherein a dielectric tantalum
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`nitride ARC is located between the first dielectric layer and
`the metal layer of the dual damascene structure.
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`FIGS. 9-12 illustrate in cross-section a portion of a
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`semiconductor device in which an ARC is used at the bottom
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`5,741,626
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`2
`of a dual damascene structure in accordance with an alter-
`
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`native embodiment of the present invention.
`FIGS. 13-15 illustrate in cross-section an alternative
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`process which may be used to form a dual damascene
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`structure having an ARC layer in accordance with the
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`present invention.
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`DETAILED DESCRIPTION OF A PREFERRED
`
`
`EMBODIMENT
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`5
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`10
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`20
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`25
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`Generally. the present invention involves using a dielec-
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`tric phase of tantalum nitride (Ta3N5)in conjunction with
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`damascene or dual
`inlaid metalization processing.
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`Specifically, a conductive region is provided overlying the
`surface of a semiconductor wafer. A damascene-type contact
`
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`is etched to expose the conductive region. The damascene
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`process typically involves deposition of two dielectric layers
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`with a silicon nitride (PEN) in the middle as an etch stop
`material. In one form. an opening with a small width (via)
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`is fonned using the PEN as an etch stop, followed by a
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`formation of a larger opening (interconnect trench). The
`photolithographic processing used to form this damascene
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`contact would be benefited by the use of an antireflective
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`coating (ARC) layer. In order to reduce reflected light,
`reduce destructive and constructive interference from reflec-
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`tive light. and reduce adverse effects of light reflection
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`during photoresist processing, a tantalum nitride dielectric
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`layer (Ta3N5)is formed overlying the patterned inlaid con-
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`ductive region to function as an anti-reflective coating
`(ARC).
`
`The use of this dielectric phase tantalum nitride ARC
`
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`layer provides several advantages. First. the tantalum nitride
`
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`ARC layer made of Ta3N5has superior light absorption
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`qualities beyond other known ARC layers when I line photo
`
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`processing is used. In addition.
`the dielectric phase of
`tantalum nitride (Ta3N5)is non-conductive and will therefore
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`not produce electrical short circuits of the inlaid damascene
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`structure. In addition, the Ta3N5 dielectric ARC layer may be
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`deposited between the two dielectric layers (or oxide layers)
`to replace the PEN layer so that the tantalum nitride ARC
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`layer can serve the dual purpose of being an anti-reflective
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`coating and being an etch stop layer used to form the
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`damascene contact. In addition, the Ta3N5 coating may be
`
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`deposited directly on top of the underlying conductive
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`region as a barrier layer which prevents atoms of copper or
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`like atoms from diffusing into adjacent dielectric regions.
`The use of a dielectric tantalum nitride layer as an ARC
`
`
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`
`
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`coating/etch stop layer/barrier material can be better under-
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`stood with reference to FIGS. 1-12.
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`FIGS. 1-5 illustrate a method for forming a semiconduc-
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`tor structure 10 using a dielectric phase tantalum nitride
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`(Ta3N5) anti-reflective coating (ARC) layer. In FIG. 1, a
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`semiconductor substrate 12 is provided. Typically, the anti-
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`reflective layer processing taught herein is performed
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`between conductive layers of an integrated circuit which
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`may comprise one or more layers of polysilicon. amorphous
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`silicon. silicides. salicides, metal regions. refractory metals.
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`and the like. Therefore, semiconductor substrate 12 not only
`includes a semiconductor wafer portion, but may also
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`include a plurality of dielectric and conductive layers as are
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`necessary to form active devices on a semiconductor sub-
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`strate. A conductive region 14 is formed overlying the
`semiconductor substrate 12 which contains the active cir-
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`cuitry (not specifically illustrated in FIG. 1). The conductive
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`region 14 is used to electrically connect one active element
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`in the substrate 12 to one or more other active element in the
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`substrate 12 as is known in the art. Conductive region 14 is
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`Page 8 of 12
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`Page 8 of 12
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`10
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`preferably made of 99% aluminum with a remainder of the
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`material comprising copper. In another form. the conductive
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`region 14 may be copper. polysilicon. gold. or any like
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`conductive layer which has a surface that is reflective to light
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`during photolithography processing. The layer 14 may be
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`formed by a damascene process or may be patterned and
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`etched using conventional photolithography and etch tech-
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`nology.
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`A first dielectric layer 16 is deposited over the conductive
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`region 14. In a preferred form. dielectric layer 16 is a
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`tetraethelorthosilicate (TEOS) layer. A dielectric tantalum
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`nitride layer Ta3N5is deposited overlying the first dielectric
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`layer 16. In a preferred form. the layer 18 is deposited
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`having a thickness of 100 angstroms to 1000 angstroms,
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`however. any thickness of layer 18 will provide at least some
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`anti-reflective properties. A second dielectric layer 20 is then
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`deposited over the dielectric tantalum nitride layer 18. In a
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`preferred form. the second dielectric layer 20 is a TEOS
`dielectric layer.
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`In FIG. 1. a photoresist material 22 is formed overlying
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`the second dielectric layer 20. A portion of the photoresist 22
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`is exposed to light or some radiation while other portions of
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`the photoresist 22 are shielded or masked from exposure to
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`the light. Typical wavelengths of light used for this exposure
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`process is a wavelength selected from the range of 200
`nanometers to 440 nanometers. When this light is selectively
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`exposed to photoresist layer 22. the light passes through
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`layer 22. through layer 20. and will encounter the anti-
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`reflective coating dielectric tantalum nitride layer 18. The
`dielectric tantalum nitride layer 18 will attenuate (via
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`absorption of energy) some of the light passing through layer
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`18 and will also phase shift some of the light through layer
`18 so that reflection off a surface of layer 14 will not
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`adversely impact the light exposure and subsequent devel-
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`opment of portions of the photoresist 22. Due to the presence
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`of layer 18. the dimensions of Various openings through the
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`photoresist 22 are rendered more controllable and an open-
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`ing 24 can be developed through photoresist 22 in a manner
`that is much more manufacturable than openings which are
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`manufactured using no anti-reflective coating layer.
`Therefore, FIG. 1 illustrates an opening 24 which is superior
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`to other openings formed in the prior art due to the presence
`of the ARC dielectric tantalum nitride layer 18.
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`It is important to note that the attenuation properties of the
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`Ta3N5 dielectric tantalum nitride layer 18 is maximized at a
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`wavelength of roughly 300 nanometers. Optimal attenuation
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`of reflection is also achieved when the thickness of the
`dielectric tantalum nitride layer 18 is between 100 ang-
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`stroms and 1000 angstroms. An optimal thickness being
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`roughly 500 angstroms in most circumstances. Therefore,
`the dielectric tantalum nitride layer 18 is a superior anti-
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`reflective coating layer when used for I line processing and
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`other photolithographic processing involving light exposure
`in the vicinity of 300 nanometers.
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`FIG. 2 illustrates that the opening 24 in the photoresist
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`layer 22 is extended through the second dielectric layer 20
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`to form a first portion 26 of a contact opening. The chemistry
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`used to etch the opening 26 in second dielectric layer 22 is
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`selective to the layer 18. Therefore. the dielectric tantalum
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`nitride layer 18 functions as an etch stop for the etching
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`process used to form the opening 26. In FIG. 2. the photo-
`resist 22 is illustrated as being removed from the semicon-
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`ductor structure 10 after formation of the opening 26. While
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`this photoresist removal is performed in FIG. 2 in a preferred
`method. in another form. photoresist 22 may remain on the
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`surface of the semiconductor structure 10 and be removed
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`subsequently with photoresist 28 of FIG. 3. The dielectric
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`20
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`25
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`30
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`35
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`40
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`55
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`60
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`65
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`5 ,74l,626
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`3
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`15
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`. 4
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`tantalum nitride layer is preferably etched Via a plasma
`fluorine chemistry (CF4).
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`FIG. 3 illustrates that photoresist 28 is deposited overly-
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`ing the second dielectric layer 20 and the dielectric tantalum
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`nitride layer 18. A second masking and photolithographic
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`process is used to expose the photoresist 28 to light wherein
`the anti-reflective dielectric tantalum nitride layer 18 is once
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`again used to reduce the adverse effects of light reflection
`from the surface of conductive region 14 to improve the
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`critical dimension control of openings formed through pho-
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`toresist layer 28. FIG. 3 illustrates that the opening 30
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`formed through photoresist layer 28 has a width which is
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`less than a width of the opening formed through photoresist
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`layer 22 and second dielectric layer 20. This two-tier etch
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`processing is typical when forming damascene contacts
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`since the opening formed through layer 20 is used to provide
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`an electrical interconnect portion of conductive material
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`between two contact openings and the opening formed using
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`opening 30 as used to form a one Contact portion of the
`darnascene electrical interconnect.
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`FIG. 4 illustrates that the opening 30 through the photo-
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`resist layer 28 is extended through the anti-reflective coating
`dielectric tantalum nitride layer 18 and the first dielectric
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`layer 16 to expose a top surface of the conductive region 14.
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`Therefore, the processing illustrated in FIGS. 2-4 result in
`a two tier Contact having a first portion 26 and a second
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`portion 32 wherein a width of the portion 26 is greater than
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`a width of the portion 32 as illustrated in FIG. 4. I11 FIG. 4.
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`the photoresist layer 28 is removed from a surface of a
`semiconductive structure 10.
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`FIG. 5 illustrates that a conformal conductive layer is
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`deposited overlying the semiconductor structure 10 and that
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`this layer is chemically mechanically polished (CMP) or
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`processed via resist etch back (REB) technology to form a
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`planarized conductive plug 36 within the first portion 26 and
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`second portion 32 of the opening formed via the processing
`illustrated in FIG. 4. It is important to note that since the
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`layer 18 is a dielectric tantalum nitride layer. the layer 18
`does not need to be isolated from any one of layer 14 or
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`conductive plug 36 by dielectric spacers or additional depo-
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`sition steps. Therefore. by using a dielectric tantalum nitride
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`layer 18: (1) reflection from layer 14 is reduced to improve
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`photoresist and photolithographic processing; (2) layer 18 is
`used as an etch stop to properly form darnascene contacts;
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`and (3) no additional processing steps are needed to deposit
`materials which isolate the conductive plug 36 from the
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`layer 18 since the tantalum nitride layer 18 is nonconductive.
`Therefore. in summary. FIGS. 1-5 illustrate a method for
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`forming an inter-metal damascene contact using a dielectric
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`tantalum nitride layer 18 which is superior to that taught in
`the prior art.
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`FIG. 6 illustrates. in an x-y plot, the percentage reflec-
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`tivity of photolithographic light versus the thickness of the
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`dielectric layer 16. FIG. 6 illustrates the reflectivity for light
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`having a wavelength of 365 nanometers. It should be noted,
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`however. that the reflectivity of nearly any wavelength of
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`light and nearly any thickness of TEOS is going to be
`substantial in a manner similar to that illustrated in FIG. 6.
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`FIG. 6 illustrates that when no ARC layer (like layer 18
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`taught herein) is placed onto a semiconductor substrate as
`illustrated in FIGS. 1-5. the reflectivity of light from the
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`surface of conductive region 14 is roughly 90%. This
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`reflected light may cause constructive or destructive inter-
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`ference during photolithographic processing which will ren-
`der the critical dimensions (e.g. width) of contact openings
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`to vary significantly. In addition. the reflected light may
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`result in photoresists not being properly exposed to light and
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`Page 9 of 12
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`Page 9 of 12
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`

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`5,741,626
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`not being properly developed. When photoresist is not
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`properly exposed to light, the yield of the semiconductor
`device may be decreased. Therefore. FIG. 6 illustrates the
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`need for reducing light reflectivity from the layer 14 so that
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`photoresist processing can be improved
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`FIG. 7 illustrates the reflectivity percentage from the
`surface of the conductive region 14 once the ARC dielectric
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`tantalum nitride layer 18 is in place as fllustrated in FIGS.
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`1-5. FIG. 7 clearly indicates that a dielectric tantalum nitride"
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`layer 18 when formed to a thickness of between 100
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`angstroms and roughly 800 angstroms can significantly
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`reduce the reflectivity percentage of light from the surface of
`conductive layer 14. This significant reduction of reflected
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`light results in a more controlled critical dimension process
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`and a higher yield photoresist process than that previously
`available via the reflection illustrated in FIG. 6.
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`FIG. 8 illustrates that the tantalum nitride layer 18 of
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`FIGS. 1-5 may be positioned at the interface of layers 14
`and 16 instead of between layers 16 and 20 as in FIG. 1
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`while still obtaining significant reflection reduction. In
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`addition, the dielectric tantalum nitride layer also provides a
`diffusion barrier for metals such as copper which is known
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`to diifuse easily through dielectric materials (TEOS and
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`polyimide). Therefore, in an alternate embodiment, the layer
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`18 may be placed between the layer 14 and the layer 16 and
`not in between the layer 16 and the layer 20 as illustrated in
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`FIG. 1. In yet another embodiment, the anti-reflective layer
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`18 may be placed between the second dielectric layer 20 and
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`the photoresist layer 22. Experimentation has shown that
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`this upper placement of the dielectric tantalum nitride layer
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`18 still results in significant reduction in light reflectivity
`similar to that indicated in FIGS. 7 and 8.
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`Given that the tantalum nitride dielectric layer 18 may be
`positioned at different places within the interlevel dielectric
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`composite, FIGS. 9-12 illustrate and alternate embodiment.
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`FIG. 9 illustrates a substrate 12 which is analogous to the
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`substrate illustrated in FIG. 1. A conductive region 14 is
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`deposited where conductive region 14 is analogous to the
`conductive region 14 of FIG. 1. The dielectric tantalum
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`nitride layer 18 is deposited on top of the conductive region
`14 as illustrated in FIG. 9. A dielectric layer 16 which is
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`analogous to the dielectric layer 16 of FIG. 1 is then
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`deposited overlying the dielectric tantalum nitride layer 18.
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`A second etch stop layer or anti-reflective coating layer 42
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`is then deposited overlying the first dielectric layer 16. layer
`42 may be made of dielectric tantalum nitride (Ta3N5)or may
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`be made of other dielectric anti-reflective coatings such as
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`silicon rich silicon nitride. An opening 44 is etched through
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`layer 42 using conventional photolithographic and etch
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`processing.
`After formation of the opening 44 as illustrated in FIG. 9,
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`a second dielectric layer 20 is deposited overlying the
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`opening 44 and the layer 42. Dielectric layer 20 in FIG. 9 is
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`analogous to the dielectric layer 20 of FIG. 1. A polish stop
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`layer 46 is then deposited overlying a top portion of the
`dielectric layer 20. The polish stop layer 46 may be formed
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`from tantalum nitride (Ta3N5)or may be formed by any
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`polish stop material which is suitable for stopping a cherni—
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`cal mechanical polishing (CMP) operation. It is important to
`note that any one layer, several layers, or all of the layers 18.
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`42. and 46 may be used to provide anti-reflective properties
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`druing the formation of the semiconductor structure 40.
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`FIG. 10 illustrates that a photoresist layer 48 is formed
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`over a top of the polish stop layer 46. The photoresist layer
`48 of FIG. 10 is analogous to the photoresist layer 22 of FIG.
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`1. Therefore. the opening 24 of FIG. 1 is analogous to the
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`Page 10 of 12
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`opening 50 of FIG. 10. It is important to note that the
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`opening 50 through the photoresist layer 48 has a width
`which is greater than a width of the opening 44 as illustrated
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`in FIG. 10.
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`FIG. 11 illustrates that the polish stop layer 46 and the
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`second dielectric layer 20 are etched by exposing the layers
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`46 and 20 to an etch chemistry. The etch chemistry used to
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`etch the dielectric layer 20 is selective to the layer 42.
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`Therefore, layer 42 will provide a self-alignment mechanism
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`whereby the etch chemistry used to etch layers 20 and 16
`will automatically, in a self-aligning manner, allow for the
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`formation of a first opening portion 52 and a second opening
`portion 54. The first opening portion 52 has a width which
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`is greater than the second opening portion 54 due to the
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`smaller radius opening 44 of FIG. 10. Therefore, the final
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`structure resulting in FIG. 11 is nearly identical
`to the
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`structure illustrated in FIG. 4 with the exception of the
`additional layers 46 and 42 illustrated in FIG. 11.
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`FIG. 12 illustrates that a conductive layer 58 is deposited
`and is chemical mechanically polished (CMPed) to form a
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`conductive plug 58. Conductive plug 58 fonns an electrical
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`interconnect portion and an electrical contact portion which
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`allows for electrical signals to be provided between conduc-
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`tive region 14 and other conductive portions of the substrate
`12.
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`FIGS. 13-15 illustrate an alternative embodiment for
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`forming a dual damascene opening 34 in accordance with
`another embodiment of the present
`invention.
`In this
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`embodiment, rather than forming the larger portion of the
`dual damascene opening first as in FIGS. 1-5, the smaller
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`portion of the opening is fonned first. More specifically, in
`reference to FIG. 13, photoresist mask 60 is formed over-
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`lying substrate 12, conductive region 14. first dielectric layer
`16, dielectric tantalum nitride layer 18, and second dielectric
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`layer 20. An opening 62 is formed in photoresist mask 60.
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`and the device is etched to form a first portion 64 of an
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`opening through second dielectric layer 20 and dielectric
`tantalum nitride layer 18. as illustrated in FIG. 13. First
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`portion 64 of the opening is used to define the smaller hole
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`opening portion of the dual damascene structure. After
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`forming first portion 64, another photoresist mask 66 is
`formed on the device and is patterned to include an opening
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`68. as illustrated in FIG. 14. Opening 68 will be used to
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`define the larger portion of the darnascene opening while
`also etching a smaller opening in the dielectric layer 16. An
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