United States Patent [19J
`Grill et al.
`
`111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US006140226A
`[11] Patent Number:
`[45] Date of Patent:
`
`6,140,226
`Oct. 31, 2000
`
`[54] DUAL DAMASCENE PROCESSING FOR
`SEMICONDUCTOR CHIP INTERCONNECTS
`
`[75]
`
`Inventors: Alfred Grill, White Plains; John
`Patrick Hummel, Millbrook;
`Christopher Vincent Jahnes, Monsey;
`Vishnubhai Vitthalbhai Patel,
`Yorktown Heights; Katherine Lynn
`Saenger, Ossining, all of N.Y.
`
`[73] Assignee: International Business Machines
`Corporation, Armonk, N.Y.
`
`[21] Appl. No.: 09/126,212
`
`[22] Filed:
`
`Jul. 30, 1998
`
`Related U.S. Application Data
`[60] Provisional application No. 60/071,628, Jan. 16, 1998.
`Int. CI? ................................................. HOlL 21!4763
`[51]
`[52] U.S. Cl. ........................... 438/637; 438/701; 438/638
`[58] Field of Search ..................................... 438/637, 636,
`438/700, 701, 702, 638, 640
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,604,156
`
`2/1997 Chung et a!. .
`
`5,882,996
`
`3/1999 Dai .......................................... 438/597
`
`FOREIGN PATENT DOCUMENTS
`
`905768
`
`3/1999 European Pat. Off ..
`
`Primary Examiner---Caridad Everhart
`Attorney, Agent, or Firm-Robert M. Trepp
`
`[57]
`
`ABSTRACT
`
`The present invention relates to lithographic methods for
`forming a dual relief pattern in a substrate, and the appli(cid:173)
`cation of such methods to fabricating multilevel interconnect
`structures in semiconductor chips by a Dual Damascene
`process in which dual relief cavities formed in a dielectric
`are filled with conductive material to form the wiring and via
`levels. The invention comprises a twice patterned single
`mask layer Dual Damascene process modified by the addi(cid:173)
`tion of an easy-to-integrate sidewall liner to protect organic
`interlevel and intralevel dielectrics from potential damage
`induced by photoresist stripping steps during lithographic
`rework. The invention further comprises a method for form(cid:173)
`ing a dual pattern hard mask which may be used to form dual
`relief cavities for use in Dual Damascene processing, said
`dual pattern hard mask comprising a first set of one or more
`layers with a first pattern, and a second set of one or more
`layers with a second pattern.
`
`48 Claims, 8 Drawing Sheets
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`38
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`TSMC Exhibit 1005
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`Page 1 of 17
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`U.S. Patent
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`Oct. 31, 2000
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`Sheet 1 of 8
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`6,140,226
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`Fig. 1A
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`v4:4 c: ~ 0
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`12
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`PRIOR ART
`Fig. 1 B
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`Fig. 1 C
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`Oct. 31, 2000
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`Sheet 2 of 8
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`6,140,226
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`Fig. 2A
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`Fig. 28
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`Oct. 31, 2000
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`Sheet 3 of 8
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`6,140,226
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`Fig. 3A
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`Fig. 3C
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`Oct. 31, 2000
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`Sheet 4 of 8
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`6,140,226
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`Fig. 4A
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`Fig. 48
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`Fig. 4C
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`12
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`46
`14
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`Fig. 40
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`Fig. 4E
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`Fig. 4F
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`46
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`Page 5 of 17
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`U.S. Patent
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`Oct. 31, 2000
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`Sheet 5 of 8
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`6,140,226
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`Fig. SA
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`Fig. 58
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`Fig. SC
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`Page 6 of 17
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`U.S. Patent
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`Oct. 31, 2000
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`Sheet 6 of 8
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`Fig. 6A
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`Fig. 61
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`U.S. Patent
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`Oct. 31, 2000
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`Sheet 7 of 8
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`6,140,226
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`Fig. 7A
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`Fig. 78
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`Fig. 7C
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`Oct. 31, 2000
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`Sheet 8 of 8
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`Fig. Sa
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`Fig. Bb
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`6,140,226
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`5
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`15
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`2
`layer of masking material that is patterned twice, the first
`time with a via pattern and the second time with a wiring
`pattern. This procedure typically comprises the steps of:
`forming one or more layers of dielectric having a total
`thickness equal to the sum of the via level and wiring
`level thicknesses,
`applying a layer of a hard mask material such as Si02 or
`Si3N4 having different etch characteristics than the
`underlying dielectric,
`patterning the hard mask material with the via level
`pattern, typically by etching through a photoresist
`stencil,
`transferring said via level pattern into a first upper thick(cid:173)
`ness of said one or more layers of dielectric by a
`process such as etching,
`repatterning the same layer of hard mask material with the
`wiring level pattern,
`transferring the wiring level pattern into a second upper
`thickness of said one or more layers of dielectric in
`such a manner as to simultaneously transfer the previ(cid:173)
`ously etched via pattern to a bottom thickness of said
`one or more layers of dielectric, said second upper and
`bottom thicknesses closely approximating the wiring
`and via level thicknesses, respectively.
`While this "twice patterned single mask layer" process
`has the virtue of simplicity, difficulties in reworking the
`second lithography step may occur if the interconnect
`dielectric and the photoresist stencil used to pattern the hard
`30 mask have similar etch characteristics. Such would be the
`case with an organic photoresist and a carbon-based inter(cid:173)
`connect dielectric such as DLC. A typical cause for rework
`might be a misalignment between the via-patterned hard
`mask/upper dielectric layers and the wiring-patterned resist
`layer. However, lithographic rework at this stage is a prob(cid:173)
`lem because the sidewalls of the via -patterned dielectric are
`not protected from the resist stripping steps necessary for
`removing a misaligned wiring-patterned resist layer.
`
`1
`DUAL DAMASCENE PROCESSING FOR
`SEMICONDUCTOR CHIP INTERCONNECTS
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`
`The present application claims priority to co-pending U.S.
`provisional application Ser. No. 60/071,628 filed Jan. 16,
`1998.
`
`FIELD OF THE INVENTION
`
`The present invention relates to lithographic methods for
`forming a dual relief pattern in a substrate, and the appli(cid:173)
`cation of such methods to fabricating multilevel interconnect
`structures in semiconductor chips.
`
`BACKGROUND OF THE INVENTION
`
`Device interconnections in Very Large Scale Integrated
`(VLSI) or Ultra-Large Scale Integrated (ULSI) semiconduc-
`tor chips are typically effected by multilevel interconnect 20
`structures containing patterns of metal wiring layers called
`traces. Wiring structures within a given trace or level of
`wiring are separated by an intralevel dielectric, while the
`individual wiring levels are separated from each other by
`layers of an interlevel dielectric. Conductive vias are formed 25
`in the interlevel dielectric to provide interlevel contacts
`between the wiring traces.
`By means of their effects on signal propagation delays, the
`materials and layout of these interconnect structures can
`substantially impact chip speed, and thus chip performance.
`Signal propagation delays are due to RC time constants
`wherein R is the resistance of the on-chip wiring, and C is
`the effective capacitance between the signal lines and the
`surrounding conductors in the multilevel interconnection
`stack. RC time constants are reduced by lowering the 35
`specific resistance of the wiring material, and by using
`interlevel and intralevel dielectrics with lower dielectric
`constants.
`A preferred metal/dielectric combination for low RC
`interconnect structures might be Cu metal with a carbon- 40
`based dielectric such as diamond-like-carbon (DLC) or an
`organic polymer. Due to difficulties in subtractively pattern(cid:173)
`ing copper, however, interconnect structures containing cop(cid:173)
`per are typically fabricated by a Damascene process. In a
`Damascene process, metal patterns inset in a layer of dielec- 45
`tric are formed by the steps of
`etching holes (for vias) or trenches (for wiring) into the
`interlevel or intralevel dielectric,
`optionally lining the holes or trenches with one or more 50
`adhesion or diffusion barrier layers,
`overfilling said holes and trenches with a conductive
`wiring material, by a process such as physical vapor
`deposition (for example, sputtering or evaporation),
`chemical vapor deposition, or plating, and
`removing the metal overfill by planarizing the metal to be
`even with the upper surface of the dielectric.
`This process is repeated until the desired number of wiring
`and via levels have been fabricated.
`Fabrication of interconnect structures by Damascene pro(cid:173)
`cessing can be substantially simplified by using a process
`variation known as Dual Damascene, in which a wiring level
`and its underlying via level are filled in with metal in the
`same deposition step. However, fabrication by this route
`requires transferring two patterns to one or more layers of 65
`dielectric in a single block of lithography and/or etching
`steps. This has previously been accomplished by using a
`
`SUMMARY OF THE INVENTION
`
`The present invention relates to improved methods for
`defining and transferring two patterns (or a single dual relief
`pattern) to one or more layers of dielectric in a single block
`of lithography and/or etching steps. The invention comprises
`two preferred modifications of a prior art "twice patterned
`single mask layer" Dual Damascene process and two pre-
`ferred embodiments of a fabrication process for a dual
`pattern hard mask which may be used to form dual relief
`cavities for Dual Damascene applications.
`The first and second preferred modifications of a prior art
`"twice patterned single mask layer" process introduce an
`easy-to-integrate sidewall liner which protects organic inter(cid:173)
`level and intralevel dielectrics from potential damage
`55 induced by photoresist stripping steps which may be needed,
`for example, during rework processing to correct for litho(cid:173)
`graphic misalignment. In the first modification, the liner may
`be permanent, in which case portions of the liner can remain
`in the final structure. In the second modification, the liner
`60 may be disposable, in which case the liner would be
`removed from the finished structure. Use of these inventive
`modifications allows problem-free rework with minimal
`impact on processing.
`The two preferred embodiments of a dual pattern hard
`mask fabrication process provide a mask wherein the litho(cid:173)
`graphic alignment for both via and wiring levels is com(cid:173)
`pleted before any pattern transfer into the underlying
`
`Page 10 of 17
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`6,140,226
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`3
`interlevel/intralevel dielectric. The dual pattern hard mask
`might preferably comprise a bottom layer of silicon nitride
`with a first pattern and a top layer of Si02 with a second
`pattern. The two embodiments differ by the order in which
`said first and second patterns are transferred into the hard
`mask layers.
`It is thus an object of the present invention to improve the
`existing "twice patterned single mask layer" Dual Dama(cid:173)
`scene process by adding a protective sidewall liner which
`may or may not remain in the final structure.
`It is a further object of the present invention to teach the
`use of a Dual Damascene process in which a dual pattern
`hard mask containing both via and wiring level patterns is
`fabricated on a substrate comprising at least one layer of an
`interlevel/intralevel dielectric, prior to any pattern transfer 15
`into the interlevel/intralevel dielectric.
`It is a further object of the present invention to provide a
`general method for forming a dual pattern hard mask, said
`dual pattern hard mask comprising a first set of one or more
`layers with a first pattern, and a second set of one or more
`layers with a second pattern.
`It is a further object of the present invention to teach a
`method for transferring said first and second patterns of said
`dual pattern hard mask to an underlying substrate to form a
`dual relief patterned structure.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`4
`A layered dielectric stack 13 compnsmg an optional
`dielectric passivation/adhesion layer 7, a via level dielectric
`8, an optional dielectric etch stop layer 10, and a wiring level
`dielectric 12 are then applied to produce the structure of
`5 FIG. lB. Via and wiring dielectrics 8 and 12 might be
`carbon-based materials such as DLC or fluorinated DLC
`(FDLC), SiCO or SiCOH compounds, or organic or inor(cid:173)
`ganic polymer dielectrics, and optional dielectric etch stop
`10 might be a silicon-containing material such as Si02,
`10 Si3N4, SiOxNy, SiCOH compounds, silicon-containing
`DLC (SiDLC), etc. The total thickness of layered dielectric
`stack 13 closely approximates the sum of the via and wiring
`level thicknesses.
`For a description of DLC and SiDLC, reference is made
`to U.S. Pat. No. 5,559,367 which is incorporated here by
`reference, for a description of FDLC reference is made to
`U.S. Pat. Nos. 5,462,784 and 5,674,638 which is incorpo(cid:173)
`rated herein by reference. For a description of hydrogenated
`oxidized silicon carbon material (SiCOH) and a method for
`20 making layers thereof reference is made to U.S. Pat. Ser. No.
`09/107,567 filed Jun. 29, 1998 by A Grill et al entitled
`"Hydrogenated Oxidized Silicon Carbon Material" which is
`incorporated herein by reference.
`A hard mask layer 14, formed from a material such as
`25 Si02 or Si3N4 having different etch characteristics from the
`underlying dielectric 12, is then applied to produce the
`structure of FIG. lC. Hard mask layer 14 is more resistant
`than photoresist to the etching condidtions used for trans(cid:173)
`fering the photoresist pattern into underlying dielectric 12. A
`30 photoresist forms a soft mask and is mainly composed of
`organic material. The hard mask may be composed of
`inorganic materials. A resist layer 16 patterned with a first
`pattern is then formed on hard mask 14, as shown in FIG.
`lD. The first pattern in patterned resist layer 16 would
`35 typically be a via level pattern. If resist layer 16 is for some
`reason misaligned with respect to underlying structures such
`as via 4, resist layer 16 may be removed by a process such
`as ashing or wet chemical etching without damaging under(cid:173)
`lying dielectric 12, since dielectric 12 is still protected by
`hard mask 14. Resist 16 is then reapplied and patterned until
`the desired alignment is achieved. Hard mask layer 14 is
`then patterned with said first pattern by etching through the
`openings in patterned resist layer 16, as shown in FIG. lE.
`Said first pattern is then transferred into the entire thickness
`of dielectric 12 by an etching process such as reactive ion
`etching (RIE), as shown in FIG. lF. This etching process
`typically also removes all residuals of patterned resist layer
`16.
`A resist layer 18 patterned with a second pattern is then
`formed on the structure of FIG. lF to produce the structure
`of FIG. lG. Said second pattern in patterned resist layer 18
`would typically be a wiring level pattern. Hard mask layer
`14 is then patterned with said second pattern by etching
`through the openings in patterned resist layer 18, as shown
`in FIG. lH. Exposed regions of optional dielectric etch stop
`10 would typically also be removed during this etching step,
`as well. Dielectrics 8 and 12 are then etched to transfer the
`second pattern into the entire thickness of dielectric 12, and
`the first pattern into the entire thickness of dielectric 8, as
`60 shown in FIG. 11. This etching process typically also
`removes all residuals of patterned resist layer 18. Exposed
`regions of optional dielectrics 10 and 7 are then removed to
`produce the structure ofFIG.lJ containing dual relief cavity
`20. Cavity 20 is optionally lined with one or more adhesion
`65 or diffusion barrier layers (not shown) and then overfilled
`with conductive wiring material 22, by a process such as
`physical vapor deposition, chemical vapor deposition, solu-
`
`45
`
`These and other features, objects, and advantages of the
`present invention will become apparent upon a consideration
`of the following detailed description of the invention when
`read in conjunction with the drawings, in which:
`FIGS. lA-lL show in cross section view the prior art
`"twice patterned single mask layer" Dual Damascene pro(cid:173)
`cess flow for forming a wiring layer and its associated
`underlying via layer;
`FIGS. 2A-2D show in cross section view an exaggeration
`of the rework problem that may be encountered with the
`process flow of FIG. 1;
`FIGS. 3A-3G show in cross section view a first preferred 40
`modification of the FIG. 1 process;
`FIGS. 4A-4F show in cross section view a second pre(cid:173)
`ferred modification of the FIG. 1 process;
`FIGS. 5A-5H illustrate in cross section view a Dual
`Damascene process flow utilizing a first preferred embodi-
`ment of the disclosed dual pattern hard mask;
`FIGS. 6A-6J illustrate in cross section view a Dual
`Damascene process flow utilizing a trilayer variation of a
`first preferred embodiment of the disclosed dual pattern hard 50
`mask;
`FIGS. 7A-7I illustrate in cross section view a Dual
`Damascene process flow utilizing a second preferred
`embodiment of the disclosed dual pattern hard mask; and
`FIGS. 8A-8D illustrate in cross section view a three 55
`pattern hard mask, and some associated materials issues.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`FIGS. lA-lL show in cross section view a prior art "twice
`patterned single mask layer" Dual Damascene process flow
`for forming a wiring layer and its underlying via layer. The
`process flow may be exercised on a variety of substrates but
`is illustrated for the simplified substrate of FIG. lA which
`comprises a semiconductor base 2 containing arrays of
`electrical devices (not shown), conductive via 4, and dielec(cid:173)
`tric passivation layer 6.
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`5
`tion deposition, or plating to produce the structure of FIG.
`1K. Conductive wiring material 22 is then planarized by a
`process such as chemical mechanical polishing (CMP) to be
`approximately even with the top surface of dielectric 12
`and/or remaining hard mask 14. Remaining hard mask 14 is
`then optionally removed to produce the structure of FIG. 1L.
`Additional wiring/via levels may be fabricated by repeating
`the steps shown in FIGS. 1B-1L.
`FIGS. 2A-2D show in cross section view an exaggeration
`of the rework problem that may be encountered with the
`process flow of FIGS. 1B-1L if resist 18 of FIG. 1G is
`misaligned. FIG. 2A shows the structure of FIG. 1F after
`application of resist 26. FIG. 2B shows the structure of FIG.
`2A after resist layer 26 has been patterned with said second
`pattern to produce misaligned patterned resist layer 28. FIG. 15
`2C shows the structure of FIG. 2B after removal of mis-
`aligned patterned resist layer 28 by a process such as ashing
`or wet chemical etching. Sidewalls 30 of dielectric 12 are
`clearly undercut. Such a result may not be a problem when
`the dimensions of said second pattern substantially exceed
`the dimensions of the first pattern, since the undercut regions
`would be etched anyway. However, it will be a problem for
`cases in which the dimensions of the first and second
`patterns are similar, as shown in FIG. 2D, since the undercut
`sidewall profile will persist in the final structure. Such
`undercutting makes critical dimension (CD) control more
`difficult and produces cavities that are more difficult to line
`with a conductive liner and fill with a conductive wiring
`material 22. An additional problem encountered with this
`technique is that resist layer 26 is necessarily thicker over
`the via areas. For positive-tone resist systems, this thicker
`resist will require higher dose exposures, with consequent
`loss in CD control.
`FIGS. 3A-3G show a first preferred modification of the
`FIGS. 1A-1L, "twice patterned single mask layer" process
`described above, in cross section view. The process of FIGS.
`3A-3G differs from that of FIGS. 1A-1L by the addition of
`a sidewall liner which may remain in the final structure. In
`addition, the first and second patterns to be transferred are
`the wiring and via patterns in the process of FIGS. 3A-3G,
`as opposed to the via and wiring patterns in the process of
`FIGS. 1A-1L.
`FIG. 3A shows the structure of FIG. 1C after application
`of an overlayer of resist 34 analogous to resist layer 16, but
`patterned with a wiring level pattern. Hard mask layer 14 is
`then patterned with the wiring pattern of resist layer 34, to
`produce the structure of FIG. 3B. The wiring pattern of resist
`layer 34 is then transferred to dielectric layer 12, and
`preferably to dielectric etch stop layer 10 as well, to form
`cavity 36 in FIG. 3C. A thin layer of conductive or insulating
`liner material38 that may also be used as a hard mask is then
`conformally deposited over the topography of FIG. 3C to
`form the lined cavity 40 shown in FIG. 3D. Possible hard
`mask/liner materials for hard mask/liner material 38 include
`conductive materials such as the metals W, Ta, Ti, Zr, Cr, Hf,
`the metal nitrides WN, TaN, TiN, ZrN, HfN, and metal
`silicon nitrides such as TaSiN, TiSiN, ZrSiN, and HfSiN,
`semiconductors such as amorphous hydrogenated silicon
`(a-Si:H), and insulators such as Si02, Si3N4, and SiCOH
`compounds. Hard mask/liner material 38 is preferably con- 60
`ducting if any of it is to be left in the final structure.
`FIG. 3E shows the structure of FIG. 3D after application
`of an overlayer of resist 42 patterned with a via level pattern.
`In the event patterned resist 42 is misaligned, patterned resist
`42 may be removed by a process such as ashing or wet
`chemical etching without damaging the sidewalls of dielec(cid:173)
`tric layer 12 or the top surface of dielectric layer 8. The steps
`
`6
`of applying an overlayer of resist 42 and patterning resist 42
`may be repeated until patterned resist 42 is properly aligned.
`The pattern of resist layer 42 is then transferred to hard
`mask/liner layer 38, to produce the structure of FIG. 3F, and
`then transferred further to dielectric layers 8 and 7 to
`produce the dual relief cavity 44 in FIG. 3G. After optional
`removal (not shown) of some or all of patterned hard
`mask/liner 38 by a selective etching process such as CMP,
`RIE, or wet etching, the structure is overfilled with a
`10 conductive material and planarized, as shown in FIGS. 1K
`and 1L. Any portions of hard mask/liner 38 remaining above
`dielectric 12 after the final polishing step are preferably
`removed before fabrication of any overlying wiring or via
`levels.
`FIGS. 4A-4F show a second preferred modification of the
`FIGS. 1A-1L. "twice patterned single mask layer" process,
`in cross section view. The process of FIGS. 4A-4F differs
`from that of FIGS. 1A-1L by the addition of a disposable
`sidewall coating which is removed from the structure at an
`20 intermediate stage in processing. However, it is similar to
`the prior art FIGS. 1A-1L process in that a single hard mask
`layer is patterned twice, first with a via pattern and then with
`a wiring pattern.
`FIG. 4A shows the structure of FIG. 1F after application
`25 of thin disposable liner 46 conformally deposited over the
`topography of FIG. 1F to form lined cavity 50. Liner 46 may
`be conductive or insulating, and is preferably selected from
`the group of materials resistant to the oxygen ashing or wet
`chemical etching of the resist stripping process, and prefer-
`30 ably has a thickness between 1 and 50 nm. Possible liner
`materials include conductive materials such as the metals W,
`Ta, and Cr, metal nitrides such as WN, TaN, TiN, ZrN, and
`Hfn, metal silicon nitrides such as TaSiN, TiSiN, ZrSiN, and
`HfSiN, and insulating materials such as amorphous hydro-
`35 genated silicon (a-Si:H), Si02, Si3N4, SiOxNy, SiCOH
`compounds, SiDLC, and other silicon-containing materials.
`Resist layer 18 patterned with a wiring level pattern is then
`formed on the structure of FIG. 4A. If resist layer 18 must
`be reworked, liner 46 will protect dielectric 12 from damage
`40 during processing.
`If alignment of resist layer 18 with the via level pattern is
`satisfactory, the wiring level pattern is then transferred into
`disposable liner 46, hard mask 14, and etch stop 10 to form
`45 the structure of FIG. 4C which is shown with the disposable
`liner sidewalls 52 which may sometimes be left after dis(cid:173)
`posable liner 46 patterning. The wiring pattern of hard mask
`14 is then transferred into dielectric layers 12 and 10 while
`the via pattern in dielectrics 12 and 10 is transferred into
`50 dielectrics 8 and 7. If sidewall liner 52 is still present after
`these etching steps, it is removed by a selective etching
`process such as RIE or wet etching to produce the structure
`of FIG. 4D containing cavity 54 which would then be
`overfilled with conductive material 22 and planarized as
`55 shown in FIGS. 1K and 1L.
`A satisfactory approximation to the structure of FIG. 4C
`may be formed from the structure of FIG. 1F by etching
`exposed etch stop 10 in such a manner as to redeposit etch
`stop material to form sidewall liners 52, as illustrated in FIG.
`4E. A preferred resputtering process to form sidewall liners
`52 would be ion beam sputtering or low pressure, high bias
`voltage RIE.
`Alternatively, the structures of FIGS. 4E and 4F might be
`formed by the selective deposition of a liner material 55 on
`65 the sidewalls of dielectric 12 or on both the sidewalls of
`dielectric 12 and the exposed top surface of dielectric 8.
`Selectively deposited liner material 55 might be deposited
`
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`6,140,226
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`7
`by selective chemical vapor deposition, or by a surface
`modification treatment which could, for example, selec(cid:173)
`tively add Si or SiOx functionality to exposed surfaces of an
`organic dielectric not containing Si.
`Dual pattern hard masks may comprise a first layer of a
`first material with a first pattern and a second layer of a
`second material with a second pattern. While materials of
`said first and second mask layers may be the same (and
`deposited as a single layer), they are preferably different.
`More generally, a dual pattern hard mask may comprise a 10
`first set of one or more layers with a first pattern, and a
`second set of one or more layers with a second pattern,
`materials of said first and second sets of layers selected
`respectively from a first group of materials and a second
`group of materials.
`FIGS. 5A-5E show a first preferred embodiment of a
`method for forming a dual pattern hard mask comprising a
`first layer of a first material with a first pattern, and a second
`layer of a second material with a second pattern; FIGS.
`5F-5H show how this dual pattern hard mask may be used 20
`to fabricate a dual relief cavity for use in a Dual Damascene
`process. For purposes of illustration, one of said first and
`second patterns will be a via level pattern, and the other of
`said first and second patterns will be a wiring level pattern.
`However, this combination of via and wiring level patterns 25
`should be viewed as a special case of the general category
`of dual relief patterns in which all features of a smaller area
`(via) pattern substantially overlap with the features of a
`larger area (wiring) pattern.
`FIG. SA shows the structure of FIG. 1B after application
`of lower hard mask layer 56 and upper hard mask layer 58.
`Hard mask layers 56 and 58 are preferably formed from
`different materials which have different etch properties from
`each other and from the dielectric underlayers 12 and 8. For 35
`example, lower hard mask layer 56 might be formed from
`Si3N4 and upper hard mask layer 58 might be formed from
`Si02. Other suitable hard mask materials may include
`Si02-based materials, other oxides, nitrides other than
`Si3N4, carbon-based dielectrics, SiC-based dielectrics,
`polycrystalline silicon, amorphous hydrogenated silicon,
`and metals. A first resist layer 60, patterned with a first
`(wiring level) pattern, is formed on layer 58 to form the
`structure of FIG. 5B. If resist layer 60 is misaligned, rework
`at this stage presents no problem. The pattern of resist layer 45
`60 is transferred into upper hard mask layer 58 by an etching
`process to form the structure of FIG. 5C. The etching
`process is preferably selective, for example a selective Si02
`to Si3N4 etch, so that lower hard mask layer 56 will remain
`intact during any overetching of hard mask layer 58.
`Patterned resist layer 60 is then removed by a process
`such as ashing or wet chemical etching, and a second resist
`layer 62, patterned with a second (via level) pattern, is then
`formed on the structure of FIG. 5C to produce the structure
`of FIG. 5D. Again, resist rework at this stage presents no
`problem because lower hard mask layer 56 is still in place
`to protect dielectric 12. The pattern of resist layer 62 is then
`transferred into lower hard mask layer 56. FIG. 5E shows the
`completed dual pattern hard mask, comprising patterned
`hard mask layers 56 and 58, with patterned resist layer 62
`still in place.
`The via level pattern is then transferred into dielectric 12
`by an etching process such as reactive ion etching, to
`produce the structure of FIG. SF. Patterned second resist
`layer 62 is absent from FIG. SF because it is typically 65
`removed by the etching process used to pattern dielectric 12.
`The etching conditions are then changed to removed
`
`8
`exposed portions of lower hard mask layer 56 and optional
`etch stop 10, to form the structure of FIG. 5G. Dielectrics 8
`and 12 are then etched to transfer said second pattern into the
`entire thickness of dielectric 12, and said first pattern into the
`5 entire thickness of dielectric 8, as shown in FIG. 5H. The
`cavity structure may then be completed as shown in FIG. 11,
`and, for interconnect applications, filled with wiring material
`22 as shown in FIGS. 1K and 1L.
`FIGS. 6A-6F show a trilayer variation of the FIG. 5
`method for forming a dual pattern hard mask; FIGS. 6G-6J
`show how this dual pattern hard mask may be used to
`fabricate a dual relief cavity for use in a Dual Damascene
`process. This trilayer variation may be preferable to the FIG.
`5 dual layer dual pattern hard mask because it provides a
`15 resist-free dual pattern hard mask prior to any pattern
`transfer into the substrate. This can be desirable when resist
`loading is a concern, or if the resist thickness has to be
`thinned to allow its removal to coincide with the endpoint of
`the cavity patterning process.
`FIG. 6A shows the structure of FIG. 1B after application
`of lower hard mask layer 66, middle hard mask layer 68, and
`upper hard mask layer 70. hard mask layers 66, 68, and 70
`are preferably formed from materials having different etch
`properties than dielectric underlayers 12 and 8. Hard mask
`layers 66 and 70 may be formed from the same material, but
`preferably one different from that of hard mask layer 68. For
`example, lower hard mask layer 66 might be formed from a
`20 nm thickness of Si3N4, middle hard mask layer 68 might
`be formed from a 50 nm thickness of Si02, and upper hard
`mask layer 70 might be formed from a 40 nm thickness of
`Si3N4. Other suitable hard mask materials may include
`Si02-based materials, other oxides, nitrides other than
`Si3N4, carbon-based dielectrics, SiC-based dielectrics,
`polycrystalline silicon, amorphous hydrogenated silicon,
`and metals.
`A first resist layer 72, patterned with a first (wiring level)
`pattern, is formed on layer 70 to form the structure of FIG.
`6B. If resist layer 72 is misaligned, rework at this stage
`presents no problem. The pattern of resist layer 72 is
`transferred into upper hard mask layer 70 by an etching
`process. Said etching process might preferably be selective
`with respect to hard mask layer 68, but it may be nonselec(cid:173)
`tive as well. Patterned resist layer 72 is then removed by a
`process such as ashing or wet chemical etching to form the
`structure of FIG. 6C.
`A second resist layer 74, patterned with a second (via
`level)