`
`United States Patent
`
`Humphreys
`
`
`
`1191
`
`
`
`
`
`(11]
`3,838,442
`
`
`
`[45] Sept. 24, 1974
`
`
`
`
`
`
`[54]
`
`SEMICONDUCTOR STRUCTURE HAVING
`
`
`
`3,584,264
`6/1971 McLouskiet al... 317/234
`
`
`
`
`
`
`
`METALLIZATION INLAID IN INSULATING
`
`
`
`3,597,834 8/1971=Lathrop et al. ...cccseceese 29/576
`
`
`
`
`
`
`
`
`
`
`Davey et aliases 117/212
`3,622,384
`11/1971
`
`
`LAYERS AND METHOD FOR MAKING
`
`
`
`
`
`
`
`
`
`
`SAME
`3,649,888 3/1972—Pitzer et alo. 317/235
`
`
`
`
`
`
`
`
`
`OTHER PUBLICATIONS
`
`
`
`Inventor: Charles B, Humphreys, Pleasant
`
`
`
`
`
`IEEE Transactions on Elec. Devices, Oct. 1969, pp.
`
`
`
`
`
`
`Valley, N.Y.
`
`
`
`
`876-877.
`
`
`[73]
`
`Assignee:.International Business Machines
`
`
`
`IBM (TDB), Vol. 8, No. 11, April 1966, p. 1687.
`
`
`
`
`
`
`
`
`
`
`
`Corporation, Armonk, N.Y.
`
`
`
`Filed:
`June 9, 1972
`
`
`
`
`
`Appl. No.: 261,348
`
`
`
`Related U.S. Application Data
`
`
`
`Continuation of Ser. No. 28,891, April 15, 1970,
`
`
`
`
`
`
`abandoned.
`
`
`
`Primary Examiner—Rudolph V. Rolinec
`
`
`
`
`Assistant Examiner—E. Wojciechowicz
`
`
`‘Attorney, Agent, or Firm—Thomas F. Galvin
`
`
`
`
`
`
`
`
`
`[75]
`
`
`
`[22]
`
`[21]
`
`
`
`
`[63]
`
`
`
`
`
`
`
`(57]
`ABSTRACT
`
`
`
`
`In a semiconductor structure with multiple levels of
`
`
`
`
`
`metallization on the surface, each metallization pat-
`
`
`
`
`
`
`
`
`
`tern is inlaid in trenches formed in an insulating layer.
`
`
`
`
`
`
`
`
`
`
`The surface of the metallization is flush with or some-
`
`
`
`
`
`
`
`
`
`
`whatlower than the surface ofits associated insulating
`
`
`
`
`
`
`
`layer. In a preferred embodiment, the different etch-
`
`
`
`
`
`ing characteristics of glass and silicon nitride are uti-
`
`
`
`
`
`
`
`
`
`
`lized to form the trenchesin the glass layer. The glass
`
`
`
`
`
`
`
`
`
`
`comprises the insulating layer and the nitride forms
`
`
`
`
`
`
`the bottom of the trench.
`
`
`
`
`
`
`
`
`5 Claims, 12 Drawing Figures
`
`
`[52]
`[51]
`[58]
`
`
`
`
`
`[56]
`
`
`
`3,461,347
`3,461,357
`3,479,237
`
`
`
`
`
`
`
`US. Chiscciscee cones 357/54, 357/68, 357/71
`
`
`
`
`
`
`Int. C1. oo ccccecesceccsscssenssecessesersecees HO11 29/34
`
`
`
`
`
`
`Field of Search... ccecceeesees 317/234, 235
`
`
`
`References Cited
`
`
`UNITED STATES PATENTS
`
`
`
`
` Lemelson.....cc cece 317/101
`8/1969
`
`
`
`
`8/1969 Mutter et al.
`317/234
`
`
`
`
`
`
`Bergh etal. wo 156/11
`11/1969
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`ai
`
`CLL
`ES SSE
`ESSPE
`
`cy
`
`
`
`
`
`
`Lay(fe GyMS A7S7D
`
`
`
`Ke
`RG AN
`J)
`Zi
`are
`ZoeDgrr
`PLOY
`
`Ce SSSe?
`
`
`
`
`
`Page 1 of 9
`
`TSMC Exhibit 1004
`
`TSMC Exhibit 1004
`
`Page 1 of 9
`
`
`
`PATENTEDSEP24ig74
`
`
`
`
`
`
`SHEET 1 OF 2
`
`
`
`3,838,442
`
`|
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`SSeS
`ow (a
`LeeRM
`
`
`
`
`
`
`
`FIG.2
`
`<a Trem
`5 Crtot
`
`
`
`Ap
`cj
`SYARSSS
`LSSol
`[SoS
`KASSSSa A
`14 LLNeBedppeled
`
`
`
`
`
`
`P
`
`NS
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 2 of 9
`
`
`INVENTOR
`
`
`B. HUMPHREYS
`CHARLES
`
`Aaerces
`Lys
`e
`
`
`
`.
`—)_ATTORNE
`
`Page 2 of 9
`
`
`
`
`PATENTED SEP2 41374
`
`
`|
`
`
`SHEET 2 OF 2
`
`
`
`3,838,442.
`
`
`
`128 Ba
`
`
`YFZS
`
`TeSSSSASS
`LLLRRO
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`34. KS
`
`SSG
`
`
`MRL
`SSSSESESSE
`SS oS
`cee
`2 Zee
`
`
`
`
`
`
`=SS
`
`sseera
`
`Pee
`
`ie
`
`MNSSSHEYSETS
`
`
`
`
`
`
`
`
`
`Page 3 of 9
`
`Page 3 of 9
`
`
`
`
`1
`
`2
`SEMICONDUCTOR STRUCTURE HAVING
`
`
`
`depositing a second pattern of metallization atop the
`
`
`
`
`
`
`
`
`METALLIZATION INLAID IN INSULATING
`
`
`
`
`
`insulation; (5) simultaneously connecting selectively
`
`
`
`
`
`LAYERS AND METHOD FOR MAKING SAME
`
`
`
`
`
`
`
`
`the first level of metallization with the second level
`
`
`
`
`
`
`
`through the via holes; and reproducing steps 2, 3, 4,
`
`
`
`
`
`
`
`
`
`Thisis a continuation of application Ser. No. 28,891
`
`
`
`
`
`5
`
`
`
`
`
`
`
`
`and 5 to formathird level. This technique, and the
`
`
`
`
`
`
`
`
`
`
`filed Apr. 15, 1970 and now abandoned.
`
`
`
`
`
`
`
`manyvariations of it which have been suggested in the
`
`
`
`
`
`
`
`
`prior art, has resulted in a commercially acceptable
`
`
`
`
`
`BACKGROUNDOF THE INVENTION
`
`
`
`
`
`
`
`transistor structure. However, in production the ratio
`
`
`
`
`
`
`
`1. Field of the Invention
`
`
`
`
`
`
`of acceptable finished circuits to the total number of
`
`
`
`
`
`
`
`
`This invention relates to semiconductor structures
`
`
`
`
`
`
`circuits started initially, i.e., the yield, has remained
`
`
`
`
`
`
`
`
`wherein crossover connections between active devices
`
`
`
`
`
`
`
`lower than desired. The basic problem lies in the humps
`
`
`
`
`
`
`
`
`within the structure, external leads and powerbuses are
`
`
`
`
`
`
`
`
`
`
`
`
`formed by the conductive lands at the locations where
`
`
`
`
`
`
`
`formed on the surface of the semiconductor body.
`
`
`
`
`
`
`
`
`
`an insulation layer passes over or under the conductive
`
`
`
`
`
`
`
`
`
`
`2. Description of the Prior Art
`
`
`
`
`
`lands which form the metallization pattern. These
`
`
`
`
`
`
`Recent technological advances have enabled transis-
`
`
`
`
`
`
`humpsarepresentin all techniques which appearin pa-
`
`
`
`
`
`
`
`
`
`
`tor manufacturers to place more and more active and
`
`
`
`
`
`
`
`
`
`tents and technical publications directed to insulating
`
`
`
`
`
`passive elements into the body of a semiconductor
`
`
`
`
`
`
`
`
`
`the multilevel metallization patterns printed on top of
`
`
`
`
`
`
`
`
`chip. For example,it is possible to form more than 500
`
`
`
`
`
`
`
`
`
`
`
`
`the chip. They are not evident in many drawings, prob-
`
`
`
`
`
`
`
`
`such elements into a chip having an area ofless than
`
`
`
`
`
`
`
`
`
`
`
`ably for reasonsofclarity and because they had not
`
`
`
`
`
`
`
`
`
`
`
`
`100 by 100 mils. This has presented a serious problem
`
`
`
`
`
`
`
`caused noticeable problemsin the particular processes
`
`
`
`
`
`
`in interconnecting the devices within the chip to form
`
`
`
`
`
`
`
`
`
`
`
`or structures involved. However,
`these humps have
`
`
`
`
`
`circuits and in providing external connections from the
`
`
`
`
`
`
`
`
`
`
`been found to be a principal cause of the formation of
`
`
`
`
`
`
`
`
`chip.
`
`pinholes and stress cracks in the insulation layer and
`
`
`
`
`
`
`
`
`
`Several alternative techniques have been advanced,
`
`
`
`
`
`
`
`pinholes in the metallization. One reason forthis lies in
`
`
`
`
`
`
`
`
`
`
`
`none of which have met with great success.
`
`
`
`
`
`
`the discontinuity present in the otherwise smooth insu-
`
`
`
`
`
`
`
`In one method, the connections are formed sepa-
`
`
`
`
`
`
`
`
`lation layer whereit passes over the conductive metalli-
`
`
`
`
`
`
`
`rately on multilayered ceramic substrates. With this
`
`
`
`
`
`
`
`zation pattern. The stress on the insulation layer is
`
`
`
`
`
`
`
`
`method, manyofthe interconnections between individ-
`
`
`
`
`
`
`
`
`
`
`greatestat that location. In addition, there are locations
`
`
`
`
`
`ual devices as well as substantially all of the external
`
`
`
`
`
`
`
`
`
`
`
`in a non-planar insulation layer whereits thickness is
`
`
`
`
`
`
`
`
`
`connections to other sources are formed onthe various
`
`
`
`
`
`
`
`
`
`
`less than the average thickness. These locations will
`
`
`
`
`
`
`layers of the laminated ceramic structure. However,
`
`
`
`
`
`
`
`
`have more pinholes than average. These pinholes and
`
`
`
`
`
`
`
`this method has the basic flaw of consuming a large
`
`
`
`
`
`
`
`
`
`
`
`
`
`stress cracks may cause one portion of a metallization
`
`
`
`
`
`
`
`
`
`
`
`area as comparedtothesize of the semiconductor chip
`
`
`
`
`
`
`
`pattern to “short” with another; or cause one portion
`
`
`
`
`
`
`
`mounted thereon. In addition to the basic flaw,there is
`
`
`
`
`
`
`
`
`
`
`
`
`of one level of metallization to short with anotherlevel.
`
`
`
`
`
`
`
`
`
`a problem ofthe length of the connection between the
`
`
`
`
`
`
`
`
`Pinholes and stress cracks in the insulation layer may
`
`
`
`
`
`
`
`
`
`
`device within the chip and the connection on the ce-
`
`
`
`
`
`
`
`
`also cause pinholes in the metallization. During an
`
`
`
`
`
`
`
`
`ramic. The longer the lead, other factors being equal,
`
`
`
`
`
`
`
`
`
`etching process on the metallization, the etchant may
`
`
`
`
`
`
`
`
`
`
`
`the longerit will take a signal to propagate. This has led
`
`
`
`
`
`
`
`
`
`
`seep through the insulation and attack the metal at an
`
`
`
`
`
`
`
`
`
`to the rather anomalous result of having the transistor
`
`
`
`
`
`
`
`undesired location,resulting in the pinhole. Pinholes in
`
`
`
`
`
`
`
`
`
`
`“package” cause a considerable portion of the total
`
`
`
`
`
`
`
`the metal may,in turn, cause pinholes in the insulation
`
`
`
`
`
`
`
`
`
`
`
`delay in signal propagation. Of course, as the art has
`
`
`
`
`
`
`
`
`layer if an insulation etchant seeps through the metal.
`
`
`
`
`
`
`
`
`
`
`advanced in forming a device within a smaller area of
`
`
`
`
`
`
`
`
`Any of these occurrences can cause a defective chip.
`
`
`
`
`
`
`
`
`
`the semiconductorchip,this problem has grownstead-
`
`
`
`
`
`
`
`
`ily worse, relatively speaking.
`
`
`
`
`A second technique which has received considerable
`
`
`
`
`
`
`
`
`publicity is the bonding of external connections at the
`
`
`
`
`
`
`
`
`
`periphery of the chip itself or on a ceramic substrate
`
`
`
`
`
`
`
`
`
`
`which holds the chip. These connections, in the form
`
`
`
`
`
`
`
`
`
`
`of wires of minute diameter, jump over the active areas
`
`
`
`
`
`
`
`
`
`
`of the chip, very similarly to conventional wiring. The
`
`
`
`
`
`
`
`problems with this technique are the fragility of the
`
`
`
`
`
`
`
`
`
`
`wires and the great difficulty in bonding the wires to
`
`
`
`
`
`
`
`
`small contact areas.
`:
`
`
`
`
`
`
`A third technique, to which the present invention is
`
`
`
`
`
`
`
`
`directed, is to produce most of the conductive connec-
`
`
`
`
`
`
`
`
`tions in multiple levels on the surface ofthe chipitself.
`
`
`
`
`
`
`
`
`
`
`
`In circuits requiring relatively few interconnections be-
`
`
`
`
`
`
`
`tween devices and few power connections,all of the
`
`
`
`
`
`
`
`
`metallization may be confined to one level. However,
`
`
`
`
`
`
`
`
`the art has progressed to having such increased density
`
`
`
`
`
`
`
`
`
`
`
`of devices per chip that more than one metallization
`
`
`
`
`
`
`
`level is required. In general, the prior art multilevel
`
`
`
`
`
`
`
`
`metallization technique has comprised:
`
`
`
`
`
`
`
`(1) the deposition of ohmic contacts and certain de-
`
`
`
`
`
`
`vice interconnections on a first level; (2) depositing
`
`
`
`
`
`
`
`
`
`
`one or more insulation layers atop thefirst metalliza-
`
`
`
`
`
`
`tion; (3) producing via holes within the insulation; (4)
`
`
`
`
`
`
`
`
`
`SUMMARYOF THE INVENTION
`
`
`
`
`It is therefore an object of this invention to provide
`
`
`
`
`
`
`
`
`
`an improved semiconductor structure with multilevel
`
`
`
`
`
`metallization on the surface thereof and a method for
`
`
`
`
`
`
`
`
`
`makingit.
`
`
`A further object is to provide an improved method
`
`
`
`
`
`
`
`
`for eliminating humps occurring at crossover points of
`
`
`
`
`
`
`
`insulation and metallization patterns.
`
`
`
`
`
`Anotherobject is to substantially eliminate pinholes
`
`
`
`
`
`
`
`and stress cracks commonlyoccurring in semiconduc-
`
`
`
`
`
`
`
`tor structures having multilevel metallization.
`
`
`
`Anotherobject is to provide a method for accurately
`
`
`
`
`
`
`
`forming trenchesin an insulating layer which allows an
`
`
`
`
`
`
`
`
`
`
`
`accurate deposition of metallization in the trenches.
`
`
`
`
`
`
`The preset invention accomplishes these and other
`
`
`
`
`
`
`
`objects by providing a structure in which each level of
`
`
`
`
`
`
`
`
`
`metallization is inlaid within an associated insulating
`
`
`
`
`
`
`
`layer and bottomed ona passivatinglayer. In each lami-
`
`
`
`
`
`
`
`
`nated section formed by the passivating and insulating
`
`
`
`
`
`
`
`
`layers and the metallization, the surface of the metalli-
`
`
`
`
`
`
`
`
`
`zationis flush with or somewhat lowerthan the surface
`
`
`
`
`
`
`
`
`of the insulating layer. However, good results are ob-
`
`
`
`
`
`
`
`
`
`tained if the surface of the metallization lies within the
`
`
`
`
`
`
`
`
`3,838,442
`
`
`
`
`
`15
`
`
`20
`
`
`
`
`
`25
`
`
`30
`
`
`
`35
`
`
`
`40
`
`
`
`45
`
`
`
`
`
`55
`
`
`
`
`
`
`
`
`
`
`
`
`Page 4 of 9
`
`Page 4 of 9
`
`
`
`3,838,442
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`15
`
`
`25
`
`
`30
`
`
`
`35
`
`
`
`40
`
`
`
`45
`
`
`
`
`
`50
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`3
`4
`
`
`
`
`
`
`
`
`
`
`
`
`range of 50A higher than the surface of the insulating
`
`
`
`
`
`
`
`is important only that the ohmic
`ductor material.
`It
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`layer and 2500A lower than the surface of the insulat-
`
`
`
`
`
`contacts be formedat the surface of the device, the sur-
`
`
`
`
`
`
`
`
`
`
`
`ing layer. This range as defined is termed ‘‘substantially
`
`face being substantially planar.
`
`
`
`
`
`
`
`
`
`
`
`
`flush” in this application and the term will be under-
`
`
`
`
`
`
`Coating 12 is preferrably an oxide of silicon. Any
`
`
`
`
`
`
`
`
`stood to mean that range.
`
`
`
`
`
`
`conventional technique may be used to form thesilicon
`
`
`
`
`
`
`
`
`
`- The preferred methodis to etch a trench in the insu-
`
`
`
`
`
`
`
`
`
`oxide layer. The particular choice will depend on the
`nature of the semiconductor material. In the case of a
`
`
`
`
`
`
`
`
`
`lating layer and then deposit the metallization into the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`trench. The bottom of the trench comprises the upper
`
`
`
`
`
`
`
`silicon wafer, a silicon dioxide coating is formed prefer-
`
`
`
`
`
`
`
`
`
`surface of a passivating layer whichis insensitive to the
`
`
`
`
`
`
`
`
`
`rably as a genetic coating formed by thermal growth
`
`
`
`
`
`
`
`
`etchant used to etch the insulating layer. Preferrably,
`
`
`
`
`
`
`
`from the silicon bodyitself. One preferred technique is
`
`
`
`
`
`
`
`
`
`
`the insulating layer is glass and the passivating layeris
`
`
`
`
`
`
`
`
`
`
`
`to heat the body to between 900° C.to 1400° C. in an
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`a conjoint layer of silicon oxide andsilicon nitride; the
`
`
`
`
`
`
`
`
`oxidizing atmosphereof air saturated with water vapor
`
`
`
`
`
`
`
`
`nitride is the upper portion of the conjoint layer.
`
`
`
`
`
`
`
`
`
`
`or in an atmosphereof steam, thus formingasilicon di-
`
`
`
`
`
`
`
`oxide coating. Alternately, an R.F. sputtering method
`IN THE DRAWING
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`may be used to form the silicon dioxide coating. If the
`
`
`
`
`
`
`
`
`
`FIG.1 is a sectional perspective view of the junctions
`
`
`
`
`
`semiconductor material is germanium rather than sii-
`
`
`
`
`
`
`
`of a single active device within a passivated planar
`
`
`
`
`
`
`
`
`
`con,a silicon oxide coating may be formed by pyrolytic
`
`
`semiconductorchip.
`
`
`
`
`
`
`
`decomposition of ethyl silicate vapor. In the present
`
`
`
`
`
`
`
`
`
`
`FIG. 1A is a view of the top surface of a portion of
`
`
`
`
`
`
`
`
`embodiment, coating 12 is silicon dioxide with a depth
`20
`
`
`
`
`
`
`
`the chip showing twoactive device areas.
`
`
`
`
`
`
`
`
`of 600a. The thickness preferrably ranges from 2000A
`
`
`
`
`
`
`FIG. 2-5 show various stages of producing ohmic ©
`
`
`
`
`
`
`
`
`
`
`to 8000A. In the remainder of the specification, the
`contacts and the first metallization level of active de-
`term silicon oxide will be understoodto also includesil-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`vices in accordance with the invention.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`icon dioxide. The silicon nitride coating 14 is contigu-
`FIGS. 6 and 7 show an active device with second and
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`ous with silicon oxide coating 12. The silicon nitride
`
`
`
`
`
`
`third levels of metallization, respectively,
`in accor-
`
`
`
`
`
`
`
`
`
`coating may be formed by known techniques such as
`dance with the invention.
`
`
`
`
`
`
`
`
`
`
`
`R.F. sputtering, as described in co-pending application
`
`
`
`
`
`
`
`
`
`
`
`
`FIGS. 6A and 7A are views of the top surface of the
`
`
`
`
`
`
`
`
`
`
`Ser. No. 494,789, filed Oct. 11, 1965, or by reactive
`
`
`
`
`
`chip showing the metallization patterns connecting the
`
`
`
`
`
`
`
`
`sputtering, as described in co-pending application Ser.
`active devices.
`
`
`
`
`
`
`
`
`
`
`
`No. 583,175, filed Sept. 30, 1966. Both of these appli-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`All of the figures are not necessarily to scale. In some
`
`
`
`
`
`
`cations are assigned to the assignee of the present in-
`
`
`
`
`
`
`
`
`
`
`instances, the dimensions have been exaggerated for
`
`
`
`
`
`
`
`vention. A third technique which could be used to form
`
`
`
`
`
`
`
`
`clarity and to show particular aspects of the invention.
`
`
`
`
`
`
`
`
`the silicon nitride coating is the pyrolytic decomposi-
`
`
`
`
`
`
`
`
`
`tion of a gaseous mixture of silane and ammonia which
`
`
`
`
`
`
`
`
`
`
`is heated to around 900° C. The preferred technique is
`
`
`
`
`
`
`
`
`
`to R.F. sputter the silicon nitride coating to a thickness
`
`
`
`
`
`
`
`
`of around 1000A, but preferrably below 2000A.
`
`
`
`
`
`
`
`
`The ranges of thickness of silicon oxide coating 12
`
`
`
`
`
`
`
`
`
`and silicon nitride coating 14 may vary from the pre-
`
`
`
`
`
`
`ferred thickness. However,
`in the preferred embodi-
`
`
`
`
`
`
`
`
`
`
`ment of this invention, it is important that the total
`
`
`
`
`
`
`
`
`thickness of the conjoint layer be precisely controlled
`
`
`
`
`
`
`
`
`or measuredafter deposition, as the metallization layer
`
`
`
`
`
`
`
`
`
`
`to be applied will be substantially flush with a glass
`
`
`
`
`
`
`
`
`
`
`
`
`layer which will be applied in a later step. In place of
`
`
`
`
`
`
`
`
`the conjoint passivating layer 12/14 of oxide and ni-
`
`
`
`
`
`
`
`
`
`
`tride, a single layer of silicon nitride might be used.
`
`
`
`
`
`
`
`
`
`However, the nitride layer alone may not insure the
`
`
`
`
`
`
`requisite passivation for structures with extensive met-
`
`allurgy.
`
`
`
`
`
`
`
`
`The precise depth of the oxide and nitride coatings
`
`
`
`
`
`
`
`may be calculated by standard techniques. For exam-
`
`
`
`
`
`
`
`
`
`ple, the thicknesses may be measured by meansof a
`
`
`
`
`technique described in “Non-Destructive Technique
`
`
`
`
`
`
`for Thickness and Refractive Index Measurements of
`
`
`
`
`
`
`
`
`
`
`
`Transparent Films,” W. A. Pliskin and E. E. Conrad,
`
`
`
`
`
`
`
`
`IBM Techincal Disclosure Bulletin, Vol. 5, No. 10,
`
`
`
`
`
`
`
`
`March 1963, pp. 6-8. Preferrably, this technique is
`
`
`
`
`
`
`
`augmented with a spectrophotometer as described in
`
`
`
`
`
`“Transparent Thin-Film Measurements by Visible
`
`
`
`
`
`
`Spectrophotometry,” A. Decobert and M. Lachaud,
`
`
`
`
`
`
`
`
`IBM Technical Disclosure Bulletin, Vol. 10, No. 11,
`
`
`
`
`
`
`April 1968, p. 1799. Besides this non-destructive
`
`
`
`
`
`
`
`
`
`method of testing. the thickness of transparent thin
`
`
`
`
`
`
`
`
`films, any well-known destructive method using a test
`wafer could be used. One known destructive methodis
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the so-called angle-lap technique. One end ofthe test
`
`
`
`
`
`
`
`
`
`
`wafer is beveled at a very small angle to expose a rela-
`
`
`
`
`
`
`
`
`
`Referring now to FIG. 1 and FIG. 1A, a semiconduc-
`
`
`
`
`
`
`
`
`
`
`tor chip 8 is shown having a substrate 10 which is cov-
`
`
`
`
`
`
`
`
`
`ered by two passivating coatings 12 and 14, The chip
`
`
`
`
`
`
`
`
`
`
`
`is one section of perhaps 50 or 60 such chips whichto-
`
`
`
`
`
`
`
`gether form a semiconductor wafer. Within the sub-
`
`
`
`
`
`
`
`
`
`
`strate 10 are areas, generally denoted as 16 and 18,
`
`
`
`
`
`
`
`containing surface junctions which form active devices.
`
`
`
`
`
`
`
`The bulk of substrate 10 may comprise a monocrystal-
`
`
`
`
`
`
`
`line p-type silicon semiconductor body having an ori-
`
`
`
`
`
`
`ented surface and exhibiting relatively high resistivity,
`
`
`
`
`
`
`
`e.g., in the order of 10 ohm-cm.
`
`
`
`
`
`
`
`
`
`
`
`Typically, chip 8 is around 100 by 100 mils, and, of
`
`
`
`
`
`
`
`
`
`course, contains many active areas of which areas 16
`
`
`
`
`
`
`
`
`
`
`and 18 are merely illustrative. In addition, the chip may
`
`
`
`
`
`
`contain regions whichare passive,i.e., resistive and ca-
`
`
`
`
`
`
`
`
`
`
`
`pacitive, which may also be. connected on top of the
`
`
`
`
`
`
`
`chip in accordance with the present invention.
`
`
`
`
`
`
`
`
`
`FIG. 1 is a sectional perspective view of area 16,
`
`
`
`
`
`
`
`
`
`
`taken along line 1—1 of FIG. 1A. Area 16 is totally
`
`
`
`
`
`
`
`
`
`within chip 8 except for the upper surface, which ini-
`
`
`
`
`
`
`tially is completely covered by conjoint passivating
`
`
`
`
`
`
`
`
`coatings 12 and 14 which together form a passivating
`
`
`
`
`
`
`
`
`layer. For simplicity and ease of understanding, area 16
`
`
`
`
`
`
`
`
`is depicted as a segment removed from chip 8. Further-
`
`
`
`
`
`
`
`
`
`more, it will be understood that each of the processes
`
`
`
`
`
`
`
`
`
`to be performed on area 16 is also performed, prefera-
`
`
`
`
`
`
`
`
`bly simultaneously, on area 18. Within area 16, there
`
`
`
`
`
`
`
`
`is shown a planar N-P-N junction device. The fabrica-
`tion of this kind of device is well knownto those skilled
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`in the art. It will be recognized that the invention is not
`
`
`
`
`
`
`
`
`
`
`confined to a particular type of device or process of
`forming the device. For instance, the device could be
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`a P-N-P type with an N type substrate 16. Also, germa-
`nium instead of silicon could be used as the semicon-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`.
`
`
`
`60
`
`
`
`
`
`
`
`Page5 of 9
`
`Page 5 of 9
`
`
`
`3,838,442
`
`
`
`
`
`
`
`
`6
`Pat. No. 3,369,991, P. D. Davidse et al. Other deposi-
`
`
`
`
`
`
`
`
`
`tion methods maybe used,such assilk screeningorpy-
`
`
`
`
`
`
`
`
`
`
`
`rolytic deposition. In any method the chemical compo-
`
`
`
`
`
`
`sition of the glass is SiO,. As with the conjoint coatings
`
`
`
`
`
`
`
`
`
`
`
`12 and 14, the thickness of glass layer 26 must be accu-
`
`
`
`
`
`
`
`
`
`
`
`rately controlled or measured to insure that the quan-
`
`
`
`
`
`
`
`
`tity of metal deposited in a later step will be substan-
`
`
`
`
`
`
`
`
`
`
`tially flush with glass layer 26. The thickness of the
`
`
`
`
`
`
`
`
`
`
`glass is preferrably from 5000A to 20,000A. In the
`
`
`
`
`
`
`
`
`
`present embodimentit is 10,000A. The measurement
`
`
`
`
`
`
`
`
`of the glass depth may be determinedor controlled in
`
`
`
`
`
`
`
`
`
`the same manneraspreviously described for the oxide
`
`
`
`
`
`
`
`
`
`and nitride coatings.It is evident that the measurement
`
`
`
`
`
`
`
`
`
`of the depth of conjoint passivating layer 12/14 could
`
`
`
`
`
`
`
`
`be performed after layer 26 has been formed.
`
`
`
`
`
`
`
`
`FIG. 4 is a sectional perspective view showing the
`
`
`
`
`
`
`
`
`
`ohmic contact regions 21-24 re-exposed. FIG. 4 also
`
`
`
`
`
`
`
`
`shows area 27 and trench 28 which have been formed
`
`
`
`
`
`
`
`
`
`
`by conventional techniquesin glass layer 26, but which
`
`
`
`
`
`
`
`
`
`
`do not penetrate nitride layer 14. Area 27 is sur-
`
`
`
`
`
`
`
`
`
`
`rounded on three sides by glass layer 26 and is bot-
`
`
`
`
`
`
`
`
`
`tomed atnitride coating 14. Area 28 is a trench etched
`
`
`
`
`
`
`
`
`
`in glass layer 26 and is also bottomedatnitride coating
`
`
`
`
`
`
`
`
`
`
`
`14. FIG. 4A is a top view of wafer8 at this point in the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`process. FIG. 4A showsthat areas 77 and 78,similar to
`
`
`
`
`
`
`
`
`
`
`
`area 27 and trench 28, have also been formed over de-
`
`
`
`
`
`
`
`
`
`vice 18 and that trenches 75 and 76 have been formed
`
`
`
`
`
`
`
`
`
`
`in glass layer 26 to connect appropriate contacts of de-
`
`
`
`
`
`
`
`
`
`vices 16 and 18. Trenches 75 and 76 are also bottomed
`
`
`
`
`
`
`
`
`
`
`
`at nitride coating 14,
`
`
`
`In forming the trenches and area 27, use is made of
`
`
`
`
`
`
`
`
`
`
`
`
`the fact that the glass etchant, whichis preferrably the
`
`
`
`
`
`
`
`
`
`buffered hydrofluoric acid used previously to etch
`
`
`
`
`
`
`oxide coating 12, will not attack the nitride to any sig-
`
`
`
`
`
`
`
`
`
`
`
`nifiant degree. In the etching process, a photoresist
`
`
`
`
`
`
`
`
`mask corresponding to openings 21-24, 27 andtrench
`
`
`
`
`
`
`
`
`
`28 is placed on the surface of glass 26. The surface of
`
`
`
`
`
`
`
`
`
`
`glass 26 is then exposed to a buffered etchant, as previ-
`
`
`
`
`
`
`
`
`
`
`ously described, which does not attack the nitride coat-
`
`
`
`
`
`
`
`
`ing 14, Nitride coating 14 protects the surface of oxide
`
`
`
`
`
`
`
`
`
`coating 12. The buffered etchant does not significantly
`
`
`
`
`
`
`
`
`
`attack oxide coating 12 which surrounds resigns 21~24,
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`20
`
`
`
`
`
`30
`
`
`
`
`
`35
`
`
`
`
`
`
`
`
`5
`
`tively broad surface of the layer to be measured. The
`
`
`
`
`
`
`
`
`
`
`beveled surface of the sample is stained or otherwise
`
`
`
`
`
`
`
`
`
`
`treated to delineate clearly the exposed surface ofthe
`
`
`
`
`
`
`
`layer. Monochromaticlightis then directed through an
`
`
`
`
`
`
`
`
`optically flat glass plate onto the beveled surface. Light
`
`
`
`
`
`
`
`
`
`reflected from the beveled surface interfaces with light
`
`
`
`
`
`
`
`
`reflected from the glass plate to establish interface
`
`
`
`
`
`
`
`
`fringes along those locationsof the beveled surface that
`
`
`
`
`
`
`
`
`
`
`are displaced from theflat glass plate by some multiple
`
`
`
`
`
`
`
`
`
`of a half wavelength of the light. These fringes can
`
`
`
`
`
`
`
`
`
`therefore be interpreted as being contourlines repre-
`
`
`
`
`
`
`
`senting successive gradationsof height on the beveled
`
`
`
`
`
`
`
`
`surface. The distance between each pair of fringes,
`
`
`
`
`
`
`
`
`called an order ofinterference, is representative of a
`
`
`
`
`
`
`
`
`
`vertical distance of one-half wavelength. An operator
`
`
`
`
`
`
`
`counts the numberoffringes located along the beveled
`
`
`
`
`
`
`
`
`layer surface to be measured, and thereby estimates the
`
`
`
`
`
`
`
`
`
`
`total thickness of the layer.
`
`
`
`
`
`
`In the modern manufacturing process, of course,
`
`
`
`
`
`
`there are other methods to determine and control the
`
`
`
`
`
`
`
`
`thickness of the coatings. For example, the process may
`
`
`
`
`
`
`
`
`
`
`be calibrated based on a test batch of wafers and the
`
`
`
`
`
`
`
`
`
`
`results used in succeeding batches with no further .
`
`
`
`
`
`
`
`
`measurements being needed.In addition,it may be pos-
`
`
`
`
`
`
`
`25
`sible to monitor the deposition of the coatings during
`
`
`
`
`
`
`
`
`
`
`the process, eliminating the need for thickness meas-
`
`
`
`
`
`
`
`
`
`urements at the completion of the process.
`
`
`
`
`Referring now to FIG. 2, device 16 is shown after
`
`
`
`
`
`
`
`
`
`having received ohmic contacts at base regions 21 and
`
`
`
`
`
`
`
`
`
`23, emitter region 22 andcollector region 24. FIG. 2A
`
`
`
`
`
`
`
`
`is a top view of the wafer showingidentical contacts
`
`
`
`
`
`
`
`
`
`
`having been formed in both devices 16 and 18. The
`
`
`
`
`
`
`
`
`openings for contacts 21-24 are formed by first provid-
`
`
`
`
`
`
`
`
`ing a conventional photoresist mask corresponding to
`
`
`
`
`
`
`
`the openings. Thesilicon nitride coating 14is then sub-
`
`
`
`
`
`
`
`jected to an etchant which in the present embodiment
`
`
`
`
`
`
`
`
`
`
`does not attack the oxide layer 12. Molten ammonium
`
`
`
`
`
`
`
`
`hypophosphate (NH,H,PO,) is preferrable. Alterna-
`
`
`
`
`
`tively, hot phosphoric acid may be used. After the ni-
`
`
`
`
`
`
`
`
`
`
`tride is removed from the areas not masked,thesilicon
`
`
`
`
`
`
`
`
`dioxide is removed from the same areas by a conven-
`
`
`
`
`
`
`
`
`
`tional buffer etchant which does not attack thenitride.
`
`
`
`
`
`
`
`
`
`
`
`A solution of hydrofluoric acid buffered in ammonium
`
`
`
`
`
`
`fluoride is suitable. This procedure exposes the sur-
`
`
`
`
`
`
`
`
`faces of the active regionsat 21, 22, 23, and 24. Ohmic
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`contacts are then deposited, preferrably by applying a
`
`
`
`
`
`blanketlayerof metalto the entire surface of the struc-
`
`
`
`
`
`
`
`
`
`
`
`ture. A preferred metal is a 200A blanket of platinum
`
`
`
`
`
`
`
`
`
`which may be applied by sputtering. The platinum is
`
`
`
`
`
`
`
`
`
`then sintered at about 450° C.
`to form a: platinum-
`
`
`
`
`
`
`
`
`silicide ohmic contact. The contact causes only a slight
`
`
`
`
`
`
`
`
`
`topology shift at surfaces 21-24, of around 40 A, most
`
`
`
`
`
`
`
`
`
`of the platinum diffusing into the active regions. This
`
`
`
`
`
`
`
`
`
`is too small
`to affect the desired substantially flush
`
`
`
`
`
`
`
`
`
`characteristic of the metallization to be applied ina
`
`
`
`
`
`
`
`
`
`later step and can beaccurately estimated if necessary.
`
`
`
`
`
`
`
`
`
`Other metals, such as molybdenum or tungsten, may be
`
`
`
`
`
`
`
`
`
`
`
`usedin lieu of platinum.In addition,this step might be
`
`
`
`
`
`
`
`
`
`dropped altogether,
`if desired. The ohmic contact
`
`
`
`
`
`
`
`might be formed at the sametimeasthelater step of
`
`
`
`
`
`
`
`
`
`
`
`
`metallization. In the preferred embodimentofthis in-
`
`
`
`
`
`
`
`
`
`vention, the blanket of platinum which coversthe ni-
`
`
`
`
`
`
`tride surface 14 is then removed bya conventional sub-
`
`
`
`
`
`
`
`
`tractive etch process. Referring now to FIG.3, a blan-
`
`
`
`
`
`
`
`
`ket glass layer 26 is shown deposited over the entire
`
`
`
`
`
`
`
`
`
`
`surface of the structure. Layer 26is preferrably depos-
`
`
`
`
`
`
`
`
`ited using R.F. sputtering apparatus described in U.S.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIG. 5 shows the structure after metallization has
`
`
`
`
`
`
`
`been applied. The metal may be deposited by anysuit-
`
`
`
`
`
`
`
`
`
`
`able means such as evaporation, pyrolytic decomposi-
`
`
`
`
`tion, or sputtering. The preferred metallization process
`
`
`
`
`
`
`
`
`is to mask the entire surface except contact regions
`
`
`
`
`
`
`
`
`21-24. A first blanket layer of metal is now evaporated
`
`
`
`
`
`
`
`
`
`
`
`with a thickness equal to the depth of conjoint pasivat-
`
`
`
`
`
`
`
`ing layer 12/14. This first mask is then replaced with a
`
`
`
`
`
`
`
`
`
`
`
`second mask which masks the entire surface except
`
`
`
`
`
`
`
`
`contact regions 21-24, area 27-and trench 28. A sec-
`
`
`
`
`
`
`
`
`
`ond blanket of metal is now evaporated with a thick-
`
`
`
`
`
`
`
`
`
`
`ness equal to or somewhatless than the depth of glass
`
`
`
`
`
`
`
`
`
`
`layer 26. In FIG. 5, the metallization in area 27 is de-
`
`
`
`
`
`
`
`
`
`
`
`
`
`notedby the corresponding notation 127. Similar nota-
`
`
`
`
`tion 121-124 and 128is used for the metallization ap-
`
`
`
`
`
`
`
`
`
`
`
`plied in areas 21-24 and trench 28, respectively. It will
`
`
`
`
`
`
`
`
`
`be apparent that other techniques might be used to
`
`
`
`
`
`
`
`
`
`apply the metallization. For example, a mask might be
`
`
`
`
`
`
`
`
`placed over only area 27 andtrench 28.A first blanket
`
`
`
`
`
`
`
`
`
`
`
`of metallization might then be applied over the entire
`
`
`
`
`
`
`
`
`
`surface 26 and into the uncovered regions 21-24. The
`
`
`
`
`
`
`
`
`metallization on the surface would then be stripped off
`
`
`
`
`
`
`
`
`
`
`
`by a subtractive etch technique. A second blanket
`
`
`
`
`
`
`might then be applied overthe entire surface,all open-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page6 of 9
`
`Page 6 of 9
`
`
`
`3,838,442
`
`
`7
`
`
`
`
`ings being uncovered. The quantity applied in the sec-
`
`
`
`
`
`
`ond blanket would bring the level of metallization in
`
`
`
`
`
`
`the openings to be substantially flush with the glass
`
`
`
`
`
`
`
`
`
`
`
`layer 26. The metallization on the surface would then
`
`
`
`
`
`be stripped off by subtractive etching.
`
`
`
`
`
`
`The amountof metal to be deposited may be calcu-
`
`
`
`
`
`
`
`
`
`lated accurately prior to the evaporation process by
`
`
`
`
`
`
`
`
`calculating the volume of the openings and trenchesin
`
`
`
`
`
`
`
`
`
`the passivating and insulating layers. Th surface area of
`
`
`
`
`
`
`
`
`
`the opening and trenches are precisely defined by the
`
`
`
`
`
`
`
`
`
`masks used to form them. This is well known. The
`
`
`
`
`
`
`
`
`
`
`depth of the passivating and insulating layers is calcu-
`
`
`
`
`
`
`
`
`lated as previously described. In practice, however, the
`
`
`
`
`
`
`
`
`depth is the only key factor, because in either method
`
`
`
`
`
`
`
`
`
`
`of depositing the metallization, a uniform blanket will
`
`
`
`
`
`
`
`
`descend on the entire surface of the chip. As a result,
`
`
`
`
`
`
`
`
`
`
`
`all openingsare filled uniformly with respect to the sur-
`
`
`
`
`
`
`
`
`
`face area. The depth of metal deposited may be con-
`
`
`
`
`
`
`
`
`trolled by conventional techniques. In the method of
`
`
`
`
`
`
`
`
`evaporation, a crystal oscillator oscillating at a known
`
`
`
`
`
`
`frequencyis placed inside the evaporation chamber. As
`
`
`
`
`
`
`
`the metal is deposited on the wafers and the oscillator,
`
`
`
`
`
`
`
`
`
`
`
`the frequency changein the oscillator serves as a mea-
`
`
`
`
`
`
`
`
`sure of the amountof metal deposited. For more details
`
`
`
`
`on this technique, see ‘Automatic Control of Film De-
`
`
`
`
`
`
`p