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`US005592024A
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`[11] Patent Number:
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`[45] Date of Patent:
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`5,592,024
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`Jan. 7, 1997
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`FOREIGN PATENT DOCUMENTS
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`0040745 12/1970
`Japan .
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`0040515 10/1972
`Japan .
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`0242331
`10/1987
`............................. 257/760
`Japan
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`257/760
`0082653
`3/1989
`Japan
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`2—78769
`11/1990
`257/760
`Japan
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`0270256 12/1991
`257/760
`Japan
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`0343541
`12/1993
`Japan ................................... .. 257/760
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`OTHER PUBLICATIONS
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`IBMTDB, Lithographic Patterns With a Barrier Liner, vol.
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`32, No. 103, Mar. 1990, pp. 1l4~l15.
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`IBMTDB, Copper Multilevel Interconnections, vol. 33, No.
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`11, Apr. 1991, pp. 299-300.
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`IBMTDB, AG Metallurgy System for Integrated Circuit
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`Devices vol. 13, No. 2, Jul. 1970, pp. 511-512.
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`Primary Examiner—Peter Toby Brown
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`Attorney, Agent, or Firm——Ob1on, Spivak, McClelland,
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`Maier & Neustadt, RC.
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`ABSTRACT
`[57]
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`A semiconductor device comprises a semiconductor sub-
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`strate in which a semiconductor element
`is formed, an
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`interlayer insulating film formed on the semiconductor sub-
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`strate, an insulating barrier layer, formed on the interlayer
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`insulating film by plasma nitriding, for preventing dilfusion
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`of a metal constituting a wiring layer, a conductive barrier
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`layer, formed on the insulating barrier layer, for preventing
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`diffusion of the metal, and a wiring layer formed of the metal
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`on the conductive barrier layer. A bottom portion of the
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`wiring layer is protected by the conductive barrier layer and
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`the insulating barrier layer. Therefore, the diffusion of the
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`metal constituting the wiring layer can be surely prevented.
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`5 Claims, 35 Drawing Sheets
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`United States Patent
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`Aoyama et al.
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`[19]
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`[54] SEMICONDUCTOR DEVICE HAVING A
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`WIRING LAYER WITH A BARRIER LAYER
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`Inventors: Hisako Aoyama, Kawasaki; Kyoichi
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`Suguro, Yokohama; I-Iiromi Niiyama,
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`Yokohama; Hitoshi Tamura,
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`Yokohama; Hisataka Hayashi,
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`Yokohama; Tomonori Aoyama; Gaku
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`Minamihaba, both of Kawasaki;
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`Tadashi Iijima, Yokohama, all of Japan
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`Assignee: Kabushiki Kaisha Toshiba, Kawasaki,
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`Japan
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`App]. No.2 330,998
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`Oct. 28, 1994
`Filed:
`[22]
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`Foreign Application Priority Data
`[30]
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`[JP]
`Japan .................................... 5—272784
`Oct. 29, 1993
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`[JP]
`Japan
`Mar. 15, 1994
`6-070156
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`Japan .................................. .. 6—249984
`[JP]
`Sep. 19, 1994
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`Int. Cl.6 ......................... H0lL 23/535; I-IO1L 29/41;
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`H0lL 29/43
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`.......................... 257/751; 257/752; 257/760;
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`257/763; 257/764; 257/762; 257/915
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`[58] Field of Search ..................................... 257/750-753,
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`257/759, 760, 762, 773, 763, 764, 915
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`[51]
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`[52] U.S. Cl.
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`[56]
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`References Cited
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`U.S. PATENT DOCUMENTS
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`4,091,406
`5/1978 Lewis ...................................... 257/760
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`4,789,648 12/1988 Chow et al.
`. 437/225
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`4/1994 Joshi et al. ............................ .. 257/752
`5,300,813
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`TSMC Exhibit 1018
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`FIG. 2A PRIOR ART
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`F I G. 3B PRIOR ART
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`FIG. 4A PRIOR ART
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`F |G_ 5C PRIOR ART
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`IG. 4B PRIOR ART
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`FIG_ 4C PRIOR ART
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`U.S. Patent
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`PRIOR ART ‘II In
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`PRIOR ART
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`FIG. so
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`23 V2—2-5.
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`PRIOR ART
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`PRIOR ART
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`Sheet 5 of 35
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`5,592,024
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`F|G. 20B
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`FIG. zoc
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`F I G. 200
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`-——
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`VIII’; II‘
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`if
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`Page 18 of 53
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`U.S. Patent
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`Page 22 of 53
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`Jan. 7, 1997
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`U.S. Patent
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`Jan. 7, 1997
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`U.S. Patent
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`Jan. 7, 1997
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`Page 27 of 53
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`U.S. Patent
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`Jan. 7, 1997
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`Jan. 7, 1997
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`Sheet 28 of 35
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`5,592,024
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`dominant with respect to the difiusion, it is difiicult to coat
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`the wiring 208 uniformly with the oxide film or nitride film
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`209. These problems lead to degradation in reliability.
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`FIGS. 4A to 4D are cross-sectional views showing steps
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`of another conventional wiring forming process.
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`As is shown in FIG. 4A, an interlayer insulating film 202
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`having a wiring groove in a surface portion thereof is formed
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`on a semiconductor substrate 201.
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`A dilfusion prevention layer 210 is formed on the entire
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`structure, as shown in FIG. 4B, thereby to prevent a wiring
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`material from diifusing into the interlayer insulating film
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`202. Subsequently, a conductor layer 211 which will become
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`a buried wiring portion is formed on the entire structure. The
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`material of the diffusion prevention film 210 is, for example,
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`a material tending to be oxidized or nitrided more easily than
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`the wiring material.
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`Then, as shown in FIG. 4C, the entire surface of the
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`resultant structure is etched so as to leave the conductor film
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`211 only in the wiring groove,
`thus forming the buried
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`wiring portion 211.
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`Lastly, as shown in FIG. 4D, the resultant structure is
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`annealed in an atmosphere including a slight amount of
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`oxygen or nitrogen, and diffusion is eifected in a region from
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`the dilfusion prevention film 210 up to the surface of the
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`buried wiring portion 211. Thus, an oxide film or nitride film
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`212 is formed in a surface portion of the buried wiring 211.
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`According to this method, since the surface of the wiring
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`211 can be coated with the oxide film or nitride film 212 in
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`a self-alignment manner,
`the number of steps
`is not
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`increased.
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`However, since the intergranular diffusion is dominant
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`with respect to the difl’usion, the oxide film or nitride film
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`212 is not formed uniformly although the conductor film 211
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`is not alloyed. Therefore, there is a problem in reliability.
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`In addition, like the process illustrated in FIGS. 3A and
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`3B, high—temperature heat treatment is required to form the
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`oxide film or nitride film 212. The high—temperature heat
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`treatment adversely aflects transistor characteristics and
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`requires completeness of the diifusion prevention film 210.
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`Furthermore, since the width of the wiring 211 is
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`decreased by the degree corresponding to the presence of the
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`1
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`SEMICONDUCTOR DEVICE HAVING A
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`WIRING LAYER WITH A BARRIER LAYER
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`5
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`65
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
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`The present invention relates to techniques of buried
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`wiring in semiconductor technology.
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`2. Description of the Related Art
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`With higher operation speed and higher integration den-
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`sity, wiring has become thinner and more rnultilayered.
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`Since thinning of wiring results in an increase in resistance
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`and a decrease in reliability,
`it is required to use low-
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`resistance, high-reliability wiring materials such as Au, Ag,
`and Cu.
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`Such materials, however, have problems with respect to
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`adhesion to an interlayer insulating film, diffusion into the
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`interlayer insulating film, oxidation and agglomeration, as
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`compared to conventional Al-based materials.
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`In order to solve these problems, when this kind of
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`material is used, the periphery of wiring is coated with a film
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`of a material different from the material of the wiring. This
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`kind of wiring is formed, for example, by a process illus-
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`trated in FIGS. 1A to 1D.
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`As is shown in FIG. 1A, at first, a semiconductor substrate
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`201, on the surface of which an interlayer insulating film 202
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`is formed, is prepared. A barrier metal layer 203, having
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`effects in preventing diifusion of material wiring and
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`enhancing adhesion, is formed on the interlayer insulating
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`film 202 by means of vapor deposition or sputtering. A
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`conductor 204, which will become wiring, is formed on the
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`barrier metal layer 203. A barrier metal layer 205 having the
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`same eifects as the barrier metal layer 203 is formed on the
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`conductor film 204. A resist is coated on the barrier metal
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`layer 205, exposed, and developed, thereby forming a resist
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`pattern 206 for forming wiring.
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`Then, as shown in FIG. 1B, with the resist pattern 206
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`used as a mask, the barrier metal layer 205, conductor film
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`204 and barrier metal layer 203 are etched in a shape of
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`wiring.
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`Subsequently, as shown in FIG. 1C, a barrier metal layer
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`207, which is dilferent from the wiring 204 and has the same
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`effects as the barrier metal layer 203, is formed on the entire
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`resultant structure, thereby covering side walls of the wiring
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`portion.
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`Lastly, as shown in FIG. 1D, the barrier metal layer 207
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`is anisotropically etched,
`thereby selectively leaving the
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`barrier metal layer 207 on the side walls of the wiring
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`portion.
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`According to this process, since the wiring structure
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`wherein the outer surfaces of the conductor film 204 or
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`wiring body is coated with barrier metal layers 203, 205 and
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`207 is obtained, oxidation and difiusion of the wiring
`material can be prevented.
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`This process, however, has the following problems: the
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`number of steps is large, and the insulating film provided on
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`the wiring must be flattened, and thus this process is not
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`suitable for multilayer structure.
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`If the wiring portion obtained in the step shown in FIG.
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`1B is formed in a tapered shape, the barrier metal layer 207
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`may not be formed on the side walls of the wiring portion,
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`as shown in FIG. 2A, or the conductor film 207 on the side
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`walls of the wiring portion may be etched at the time of the
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`anisotropic etching, as shown in FIG. 2B, and, as a result, the
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`Page 37 of 53
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`Page 37 of 53
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`

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`5,592,024
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`3
`the wiring resistance
`diffusion prevention film 210,
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`increases. If the width of the wiring groove is enlarged, the
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`problem of wiring resistance does not occur. However,
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`because of the increase in width of the wiring groove, the
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`wiring cannot be thinned elfectively.
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`FIGS. 5A to 5D are cross-sectional views showing steps
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`of a process for forming a through-hole in buried wiring. A
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`wiring groove and a through-hole are formed in this order.
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`In this invention, “through-hole” refers to a via hole for
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`connection between wiring layers or a contact hole for
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`connection between a wiring layer and a semiconductor
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`substrate.
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`At first, as shown in FIG. 5A, a first interlayer insulating
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`film 221 and a second interlayer insulating film 222 are
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`formed on the semiconductor substrate 220 in this order.
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`Then, a wiring groove 223 is formed in the second interlayer
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`insulating film 222.
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`Subsequently, as shown in FIG. 5B, a resist pattern 224
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`for forming the through-hole is provided. In this case, the
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`resist pattern 224 is displaced to the right owing to rnis-
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`alignment.
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`the first
`With the resist pattern 224 used as a mask,
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`interlayer insulating film 221 is etched to form a through-
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`hole 225, as shown in FIG. 5C.
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`Since the resist pattern 224 is displaced a predetermined
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`portion of the first interlayer insulating film 221 remains
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`unetched while a non—predeterrnined portion of the second
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`interlayer insulating film 222 is etched.
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`Thus, as shown in FIG. SD, a contact area of the tl1rough-
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`hole 225 decreases by a degree corresponding to displace-
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`ment of the resist pattern 224, and the width of the wiring
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`groove 223 increases at the through-hole 225.
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`The decrease in contact area of the through-hole 225 leads
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`to an increase in contact resistance and a degradation in
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`shape of a contact electrode at the through-hole, resulting in
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`degradation in reliability. On the other hand, the increase in
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`width of the wiring prevents an increase in integration
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`density.
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`FIGS. 6A to 6D are cross-sectional views showing steps
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`of another process for forming a through-hole in buried
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`wiring. In this process, a through-hole is formed prior to a
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`wiring groove.
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`At first, as shown in FIG. 6A, a first interlayer insulating
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`film 221 and a second interlayer insulating layer 222 are
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`formed in this order on a semiconductor substrate 220, and
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`that portion of the second interlayer insulating film 222,
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`where the through-hole will be formed, is etched.
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`A resist pattern 226 for forming a wiring groove is
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`provided on the entire structure, as shown in FIG. 6B. In this
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`case, the resist pattern 226 is displaced to the right owing to
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`misalignment.
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`With the resist pattern 226 used as a mask, the first and
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`second interlayer insulating films 221 and 222 are etched.
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`Thereby, a wiring groove 223 and a through-hole 225 are
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`simultaneously formed.
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`Since the resist pattern 226 is displaced, that portion of the
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`first interlayer insulating film 221, at which the through-hole
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`should be formed, is not etched.
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`the contact area of the
`Like the preceding process,
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`through-hole 225 decreases, as shown in FIG. 6D, and the
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`width of the wiring groove 223 increases at the through-hole
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`225. Consequently, the same problem as mentioned above
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`occurs.
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`FIGS. 7A to 7F are cross-sectional views showing steps of
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`a conventional wiring forming process in the case where an
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`underlayer includes a stepped portion.
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`10
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`60
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`65
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`Page 38 of 53
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`4
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`At first, as is shown in FIG. 7A, a field oxide film 402 is
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`formed on a semiconductor substrate 401. Then, a gate oxide
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`film 404, a gate electrode 405 and a diifusion layer 403 are
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`formed. Thereafter, an interlayer insulating film 406 is
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`formed on the entire structure.
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`By means of a CMP method or an etch-back method, the
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`surface of the interlayer insulating film 406 is flattened.
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`Subsequently, as shown in FIG. 7C, through-holes 407a
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`and 407b are formed by means of photolithography. In this
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`case, the depth of the through-hole 407b formed in the
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`region of the gate electrode 405 is less than the through-hole
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`407a formed in the region of the diffusion layer 403 by a
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`degree corresponding to the total thickness of the field oxide
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`film 402, gate oxide film 404 and gate electrode 405.
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`In the next step shown in FIG. 7D, contact layers 408a
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`and 408}: made of a metal such as W are selectively formed
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`in the through-holes by means of selective CVD method so
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`that the deeper through-hole may be filled with the contact
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`layer 408a. In this case, the contact layer 4081: formed in the
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`shallower through-hole is overfilled from the through-hole.
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`The contact layer 408b overfilled from the through-hole is
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`etched away, as shown in FIG. 7E, thereby flattening the
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`Contact layer 40817.
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`Lastly, as shown in FIG. 7F, wirings 409a and 409b are
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`formed on the contact layers 408a and 408b.
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`This wiring forming process, however, as the problem.
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`Since the contact layers buried in the through-holes differ
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`in thickness, the contact layers in the through-holes differ in
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`resistance and reliability. Moreover, a stepped portion is
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`created by the wirings 409a and 409b and the flatness of the
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`surface is not obtained.
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`If the contact layers 408a and 408b are formed so that the
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`shallower through-hole may be filled with the contact layer
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`408b, as shown in FIG. 8A, a stepped portion is created in
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`the deeper through-hole. If wiring is formed in this state,
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`unevenness appears in the surface of the wiring formed in
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`the deeper through—hole, as shown in FIG. 8B.
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`Whether the contact layers are formed so that the deeper
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`through-hole may be filled or the shallower through-hole
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`may be filled, surface unevenness occurs and it becomes
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`difficult to flatten an interlayer insulating film to be formed
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`in a later step.
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`FIGS. 9A to 9D are cross-sectional views showing steps
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`of another conventional wiring forming process in the case
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`where an underlayer includes a stepped portion.
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`At first, as is shown in FIG. 9A, a field oxide film 402 is
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`formed on a semiconductor substrate 401. Then, a diffusion
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`layer 403, a gate oxide film 404, a gate electrode 405 and an
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`interlayer insulating film 406 are formed.
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`In the next step shown in FIG. 9B, through-holes 407a
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`and 407b are formed on the difl’usion layer 403 and gate
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`electrode 405. In this case, since the interlayer insulating
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`film 406 is not flattened, the two through-holes 407a and
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`40712 are equal in size.
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`As is shown in FIG. 9C, a metal is selectively deposited
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`in the through-holes,
`for example, by selective CVD,
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`thereby forming contact layers 408a and 408b.
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`Wiring portions 409a and 409b are formed on the contact
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`layers 408a and 40812, as shown in FIG. 9D.
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`According to this process, since the through-holes 407a
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`and 407b are equal
`in depth,
`the contact layers in the
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`through-holes are equal in resistance and reliability at any
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`portions.
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`However, since the interlayer insulating film 406 is not
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`flattened, a focus error, etc. occurs at the time of forming a
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`Page 38 of 53
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