CERTIFICATE OF TRANSLATION
`
` I
`
` Roger P. Lewis, whose address is 42 Bird Street North,
`Martinsburg WV 25401, declare and state the following:
`
` I
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` am well acquainted with the English and Japanese languages
`and have in the past translated numerous English/Japanese
`documents of legal and/or technical content.
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` I
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` hereby certify that the Japanese translation of the
`attached document identified as:
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`
`JP Hei. 11 [1999] – 075519 Part I
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`is true, and that all statements of information and belief
`are believed to be true, and that these and similar
`statements are punishable by fines or imprisonment, or both,
`under Section 1001 of Title 18 of the United States Code.
`
`
`SINCERELY,
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`
`
`ROGER P. LEWIS
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`
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`Date: June 30, 2016
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`1
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`TSMC Exhibit 1016
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`Page 1 of 72
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` [Receipt Date] Hei.11. 3. 9 [March 9, 1999]
`[Document Name] Patent Application
`[Patent] Hei. 11 [1999] – 075519 (11. 3. 19)
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`Document Name
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`Patent Application
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`Docket Number
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`2926400241
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`11th Year of Heisei, 3rd Month, 19th Day
`Submission Date
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`[March 19, 1999]
`Director General of the Patent Office
`H01L 21/3205
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`Submitted To
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`International Classification
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`Inventor
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`Address or Residence
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`/o Matsushita Electric Industry Co., Ltd.
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`Number 1006 Ōaza Kadoma, Kadoma-shi,
`Ōsaka-fu
`Nobuo Aoi
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`00077931
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`Hiroshi MAEDA
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`100077931
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`Specifications
`Figures
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`000005821
`Matsushita Electric Industry Co., Ltd.
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`Name
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`Patent Applicant
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`Identification Number
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`Name
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`Agent
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`Benrishi
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`Benrishi
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`Hiroki OYAMA
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`Name
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`Assertion of Priority Rights Based on Earlier Application
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`10th Year of Heisei Pat. App. Number 79371
`Application Number
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`10th Year of Heisei, 3rd Month, 26th Day
`Application Date
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`[March 26, 1998]
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`Indication of Fee
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`Deposit Account Number
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`Monetary Amount Paid
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`¥21,000
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`Index of Submitted Items
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`Page 2 of 72
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` [Receipt Date] Hei.11. 3. 9 [March 9, 1999]
`[Document Name] Patent Application
`[Patent] Hei. 11 [1999] – 075519 (11. 3. 19)
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`Name of Item
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`Abstract
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`1
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`General Power of Attorney Number
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`9601026
`Proofing – Required/Not Required
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` [Receipt Date] Hei.11. 3. 9 [March 9, 1999]
`[Document Name] Specifications
`[Patent] Hei. 11 [1999] – 075519 (11. 3. 19)
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` Pages: 1/69
`Document Name
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`Specifications
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`Name of Invention
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`Formation Method of Wiring Structure
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`Scope of the Patent Claims
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`Claim 1
`A formation method of wiring structure that is characterized by the following:
`
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`Process 1, by which a 1st insulating film is formed over the lower layer of metal
`wiring, and Process 2, by which a 2nd insulating film that differs in composition from the
`afore described 1st insulating film is formed over this 1st insulating film, and
`Process 3, by which a 3rd insulating film that differs in composition from the afore
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`described 2nd insulating film is formed over this 2nd insulating film, and
`Process 4, by which a thin film is formed over the afore described 3rd insulating
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`film, and
`Process 5, by which a 1st resist pattern that has opening(s) for forming wiring is
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`formed over the afore described thin film, and
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`Process 6, by which etching is performed vis-à-vis the afore described thin film
`whilst using the afore described 1st register pattern as a mask, thus forming from the
`afore described thin film a mask pattern that has opening(s) for forming wiring, and
`Process 7, by which a 2nd resist pattern that has opening(s) for contact hole
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`formation is formed over the afore described 3rd insulating film, and
`Process 8, by which dry etching is performed vis-à-vis the afore described 3rd
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`insulating film so that the etching conditions for the etching rate for the afore described
`3rd insulating film vis-à-vis the 1st resist pattern and the 2nd resist patter is high whilst the
`etching rate vis-à-vis the afore described 2nd insulating film is low, so that together with
`pattern formation on the afore described 3rd insulating film of opening(s) for contact hole
`formation on this 3rd insulating film, and the total or partial removal of the afore
`described 1st resist pattern and the 2nd resist pattern, and
`Process 9, by which the etching conditions are such that the etching rate vis-à-
`vis the afore described 2nd insulating film is high, the etching rate vis-à-vis the 3rd
`insulating film is low, the patterning is in such a way as to form on the afore described
`2nd insulating film contact hole formation opening(s) on this 2nd insulating film, with, as a
`mask, the afore described 3rd insulating film that has been patterned vis-à-vis the afore
`described 2nd insulating, and
`Process 11, by which, under etching […]
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`Page 4 of 72
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` [Receipt Date] Hei.11. 3. 9 [March 9, 1999]
`[Document Name] Specifications
`[Patent] Hei. 11 [1999] – 075519 (11. 3. 19)
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` Pages: 2/69
` […] conditions such that the etching rate vis-à-vis the afore described 1st insulating film
`and 3rd insulating film is high whilst the etching rate vis-à-vis the afore described mask
`pattern and 2nd insulating pattern is low, are conducted dry etching vis-à-vis the afore
`described 3rd insulating film as the afore described mask pattern and also conducting
`dry etching vis-à-vis the afore described 1st insulating pattern as the patterned afore
`described 2nd insulating film, resulting in the formation of the wiring groove(s) in the
`afore described 3rd insulating film together with the contact hole(s) in the afore
`described 1st insulating film, and
`
`Process 11, by which the filling of the afore described wiring groove(s) and
`contact hole(s) with a metal film so as to form the contact that connects the upper level
`metal wiring & the afore described lower level metal wiring and the afore described
`lower level metal wiring & the afore described upper level metal wiring.
`Claim 2
`The formation method of wiring structure of Claim 1 that is characterized by
`
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`the fact that it is further equipped with a process between the afore described Process
`10 and Process 11 of the formation of an adhesive layer consisting of a metal film that is
`formed in the exposed portion(s) of the afore described wiring groove(s) in the afore
`describe 3rd insulating film and the exposed portion(s) of the afore described contact
`hole(s) of the afore described 1st insulating film.
`
`Claim 3
`The formation method of wiring structure described in Claim 1 that is
`
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`characterized by the fact that the afore described 3rd insulating film is mainly composed
`of organic component(s).
`Claim 4
`The formation method of wiring structure described in Claim 3 that is
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`characterized by the fact it includes the formation of the afore described 3rd insulating
`film by means of the CVD method wherein a perfluorodecalin containing reactive gas is
`used.
`The formation method of wiring structure described in Claim 3 that is
`Claim 5
`
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`characterized by the fact that the afore described 1st insulating film is mainly composed
`of organic component(s).
`Claim 6
`The formation method of wiring structure of Claim 5 that is characterized by
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`the fact that it is further equipped with a process between the afore described Process
`10 and Process 11 of the formation of an adhesive layer by the plasma processing
`wherein nitrogen-containing reactive gas(es) is/are used on the exposed portion(s) of
`the afore described wiring groove(s) in the afore describe 3rd insulating film and the
`exposed portion(s) of the afore described contact hole(s) of the afore described 1st
`insulating film.
`Claim 7
`The formation method of wiring structure described in Claim 3 that is
`
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`characterized by the fact it includes the formation of the afore described 1st insulating
`film by means of the CVD method wherein a perfluorodecalin containing reactive gas is
`used.
`A formation method of wiring structure that is characterized by the following:
`Claim 8
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`Process 1, by which a 1st insulating film is formed over the lower layer of metal
`wiring, and […]
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`Page 5 of 72
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` [Receipt Date] Hei.11. 3. 9 [March 9, 1999]
`[Document Name] Specifications
`[Patent] Hei. 11 [1999] – 075519 (11. 3. 19)
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` Pages: 3/69
`[…] Process 2, by which a 2nd insulating film that differs in composition from the afore
`described 1st insulating film is formed over this 1st insulating film, and
`Process 3, by which a 3rd insulating film that differs in composition from the afore
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`described 2nd insulating film is formed over this 2nd insulating film, and
`Process 4, by which a thin film is formed over the afore described 3rd insulating
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`film, and
`Process 5, by which a 1st resist pattern that has opening(s) for forming wiring is
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`formed over the afore described thin film, and
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`Process 6, by which etching is performed vis-à-vis the afore described thin film
`whilst using the afore described 1st register pattern as a mask, thus forming from the
`afore described thin film a mask pattern that has opening(s) for forming wiring, and
`Process 7, by which a 2nd resist pattern that has opening(s) for contact hole
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`formation is formed over the afore described 3rd insulating film, and
`Process 8, by which etching conditions are such that the etching rate is high vis-
`à-vis the afore described 3rd insulating film whilst the etching rate is low for the etching
`vis-à-vis the afore described 2nd insulating film and the 1st resist pattern & the 2nd resist
`pattern is low, and dry etching is performed vis-à-vis the afore described 3rd insulating
`film, whilst using the afore described 1st resist pattern and the 2nd resist pattern as a
`mask, thus patterning so as to form in the afore described 3rd insulating film the opening
`portion(s) for the contact hole formation of this 3rd insulating film.
`Process 9, by which etching conditions are such that the etching rate is high vis-
`à-vis the afore described 2nd insulating film whilst the etching rate is low for the etching
`vis-à-vis the afore described 1st insulating film, the 3rd insulating film, the 1st resist
`pattern and the 2nd resist pattern, the patterning is in such a way as to form on the afore
`described 2nd insulating film the contact hole opening portion(s) on this 2nd insulation fil,
`by means of performing dry etching with the afore described 1st resist pattern and the
`2nd resist pattern vis-à-vis the afore described insulating film, and
`Process 10, by which the afore described 1st resist pattern and the 2nd resist
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`pattern are removed, and
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`Process 11, by which etching conditions are such that the etching rate is high vis-
`à-vis the afore described 3rd insulating film and 1st insulating film whilst the etching rate
`is low for the etching vis-à-vis the afore described mask pattern and the 2nd insulating
`film, the 3rd insulating film, the 1st resist pattern and the 2nd resist pattern, by means of
`performing dry etching vis-à-vis the afore described 3rd insulating film with the afore
`described mask pattern as a mask, and together with performing dry etching vis-à-vis
`the afore described 1st insulating film with the afore described patterned 2nd […]
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`Page 6 of 72
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` [Receipt Date] Hei.11. 3. 9 [March 9, 1999]
`[Document Name] Specifications
`[Patent] Hei. 11 [1999] – 075519 (11. 3. 19)
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` Pages: 4/69
`[…] insulating film as a mask in such a way as to form on the afore described wiring
`groove(s) of the afore described 3rd insulating film as well as the contact hole(s) of the
`afore described 1st insulating film, and
`
`Process 12, by which the filling of the afore described wiring groove(s) and
`contact hole(s) with a metal film so as to form the contact that connects the upper level
`metal wiring & the afore described lower level metal wiring and the afore described
`lower level metal wiring & the afore described upper level metal wiring.
`Claim 9
`The formation method of wiring structure described in Claim 8 that is
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`characterized by the fact that afore described 3rd insulating film is mainly a low dielectric
`constant SOG film that has a siloxane skeleton.
`Claim 10
`A formation method of wiring structure that is characterized by the
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`
`following:
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`Process 1, by which a 1st insulating film is formed over the lower layer of metal
`wiring, and
`Process 2, by which a 2nd insulating film that differs in composition from the afore
`described 1st insulating film is formed over this 1st insulating film, and
`Process 3, by which a 3rd insulating film that differs in composition from the afore
`described 2nd insulating film is formed over this 2nd insulating film, and
`Process 4, by which a 4th insulating film that differs in composition from the 3d
`insulating film is formed over the afore described 3rd insulating film, and
`Process 5, by which a thin film is formed over the afore described 4th insulting
`film, and
`Process 6, by which is formed on the afore described 4th insulating film a 1st
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`resist pattern that has wiring formation opening portion(s), and
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`Process 7, by which etching is performed vis-à-vis the afore described thin film
`with the fore described 1st resist pattern as a mask, to form from the afore described thin
`film a mask pattern that has wiring formation opening portion(s), and
`Process 8, by which, after removing the 1st resist pattern, the 2nd resist pattern on
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`the afore described 4th insulating film is formed such that a 2nd resist pattern that has
`wiring formation opening portion(s), and
`Process 9, by which dry etching is performed vis-à-vis the afore described 4th
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`insulating film with the afore described 2nd resist pattern and a mask pattern are used as
`a mask so as to form patterning on the afore described 4th insulating film such that this
`4th insulating film has wiring formation opening portion(s), and
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`Page 7 of 72
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` [Receipt Date] Hei.11. 3. 9 [March 9, 1999]
`[Document Name] Specifications
`[Patent] Hei. 11 [1999] – 075519 (11. 3. 19)
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` Pages: 5/69
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`Process 10, by which dry etching is performed, with the patterned afore
`described 4th insulating film as a mask, vis-à-vis the afore described 3rd insulating film in
`a way so as to form on the afore described 3rd insulating film control hole formation
`opening portion(s) of this 3rd insulating film, and
`
`Process 11, by which dry etching is performed, with the afore described mask
`pattern as a mask, vis-à-vis the patterned afore described 4th insulating film together
`with dry etching, with the patterned afore described 3rd insulating film as a mask, vis-à-
`vis the afore described 2nd insulating film so as to form the wiring groove(s) of the
`patterned afore described 4th insulating film together with the patterning of the afore
`described 2nd insulating film so that contact hole formation opening portion(s) is/are
`formed on this 2nd insulating film, and
`
`Process 12, by which dry etching is performed, with the afore described mask
`pattern as a mask, vis-à-vis the patterned afore described 3rd insulating film together
`with dry etching, with the patterned afore described 2nd insulating film as a mask, vis-à-
`vis the afore described 1st insulating film so as to form the wiring groove(s) of the
`patterned afore described 4th insulating film together with the patterning of the afore
`described 2nd insulating film so that contact hole(s) is/are formed on afore described 1st
`insulating film, and
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`Process 13, by which the filling of the afore described wiring groove(s) and
`contact hole(s) with a metal film so as to form the contact that connects the upper level
`metal wiring & the afore described lower level metal wiring and the afore described
`lower level metal wiring & the afore described upper level metal wiring.
`Claim 11
`The formation method of wiring structure described in Claim 10 that is
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`characterized by the fact that at least 1 of the afore described 2nd insulating film and the
`3rd insulating film is such that the main composition component is organic, and
`Claim 12
`The formation method of wiring structure described in Claim 11 that is
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`characterized by the fact that the dimensions of the contact hole formation opening
`portion(s) are, vis-à-vis the dimensions of the contact hole(s), larger in the vertical
`direction vis-à-vis the direction in which the afore described upper level of the metal
`wiring extends.
`Claim 13
`A formation method of wiring structure that is characterized by the
`
`
`following:
`
`Process 1, by which a 1st insulating film is formed over the lower layer of metal
`wiring, and
`Process 2, by which a 2nd insulating film that differs in composition from the afore
`described 1st insulating film is formed over this 1st insulating film, and
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`
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`Page 8 of 72
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` [Receipt Date] Hei.11. 3. 9 [March 9, 1999]
`[Document Name] Specifications
`[Patent] Hei. 11 [1999] – 075519 (11. 3. 19)
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` Pages: 6/69
`Process 3, by which a 3rd insulating film that differs in composition from the afore
`described 2nd insulating film is formed over this 2nd insulating film, and
`Process 4, by which a thin film is formed over the afore described 4th insulting
`film, and
`Process 5, by which is formed on the afore described 4th insulating film a 1st
`resist pattern that has wiring formation opening portion(s), and
`Process 6, by which etching is performed vis-à-vis the afore described thin film
`with the fore described 1st resist pattern as a mask, to form from the afore described thin
`film a mask pattern that has wiring formation opening portion(s), and
`Process 7, by which, after removing the 1st resist pattern, the 3rd resist pattern on
`the afore described 4th insulating film is formed such that a 2nd resist pattern that has
`wiring formation opening portion(s), and
`Process 8, by which dry etching is performed vis-à-vis the afore described 3rd
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`insulating film with the afore described 3rd resist pattern and a mask pattern are used as
`a mask so as to form patterning on the afore described 3rd insulating film such that this
`4th insulating film has wiring formation opening portion(s), and
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`Process 9, by which dry etching is performed, with the patterned afore described
`3rd insulating film as a mask, vis-à-vis the afore described 2nd insulating film in a way so
`as to form on the afore described 2nd insulating film control hole formation opening
`portion(s) of this 2nd insulating film, and
`
`Process 10, by which dry etching is performed, with the afore described mask
`pattern as a mask, vis-à-vis the patterned afore described 3rd insulating film together
`with dry etching, with the patterned afore described 1st insulating film as a mask, vis-à-
`vis the afore described 2nd insulating film so as to form the wiring groove(s) of the
`patterned afore described 3rd insulating film together with the patterning of the afore
`described 1st insulating film so that contact hole formation opening portion(s) is/are
`formed on afore described 1st insulating film, and
`
`Process 11, by which the filling of the afore described wiring groove(s) and
`contact hole(s) with a metal film so as to form the contact that connects the upper level
`metal wiring & the afore described lower level metal wiring and the afore described
`lower level metal wiring & the afore described upper level metal wiring.
`Claim 14
`The formation method of wiring structure described in Claim 10 that is
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`characterized by the fact that at least 1 of the afore described 2nd insulating film and the
`3rd insulating film is such that the main composition component is organic, and
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` [Receipt Date] Hei.11. 3. 9 [March 9, 1999]
`[Document Name] Patent Application
`[Patent] Hei. 11 [1999] – 075519 (11. 3. 19)
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` Pages: 8/69
`Claim 15
`The formation method of wiring structure described in Claim 13 tht is
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`characterized by the fact that the dimensions of the contact hole formation opening
`portion(s) are, vis-à-vis the dimensions of the contact hole(s), larger in the vertical
`direction vis-à-vis the direction in which the afore described upper level of the metal
`wiring extends.
`Detailed Explanation of the Invention
`
`0001
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`
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`The present invention relates to a formation method of wiring structure in semi-
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`conductor integrated circuit devices.
`Technical Field of the Invention
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`0002
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`Prior Art
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`With the progression of integration on semi-conductor integrated circuits, he
`increase in wiring delay time, for which the increase in wiring capacity, which is the
`parasitic capacitance amongst the metal wires, has interfered with improving the
`performance of semi-conductor integrated circuits. This wiring delay time is what is
`called RC delay, and it is proportional to product of the resistance of the metal wiring
`and the line-to-line capacitance.
`0003
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`Thus, in order to reduce the wiring delay time it is necessary to make the metal
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`wiring resistance smaller or to reduce the line-to-line capacitance.
`0004
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`With that, IBM Corporation and Motorola, Inc. have reported on semi-conductor
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`integrated circuit devices wherein copper is used as the material for the wiring instead
`of aluminum alloys for the purpose of reducing the wiring resistance. Because copper
`materials have specific resistance that is two-thirds that of aluminum allow materials,
`when copper materials are used as wiring materials, it is possible to actualize a high
`speed that is 1.5 times as compared with when aluminum alloy materials are used
`because simple calculation shows that the wiring delay time is reduced by two-thirds.
`0005
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`
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`However, there is the concern that as the integration of semi-conductor circuits
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`proceeds, even with the use of copper wiring wherein copper is used, there may be
`limitations in terms of speed. Also, when copper is used as wiring material, because the
`specific resistance of copper is the next smallest as compared to gold or silver so that
`even if gold or silver were to be used for metal wiring instead of copper, the […]
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` [Receipt Date] Hei.11. 3. 9 [March 9, 1999]
`[Document Name] Patent Application
`[Patent] Hei. 11 [1999] – 075519 (11. 3. 19)
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` Pages: 8/69
`[…] decrease in wiring resistance would only be slight.
`0006
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`
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`Because of this, suppressing the line-to-line capacitance as well as reducing the
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`wiring resistance are important, and to reduce the line-to-line capacitance it is
`necessary to reduce the relative dielectric constant of the inter-level insulating films.
`Heretofore, silicon dioxide films have been used for inter-level insulating films but the
`relative dielectric constant is about 4 to 4.5, and there are difficulties in using them fr
`inter-level integrating films in the more and more integrated semi-conductor integrated
`circuits.
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`0007
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`With that, the use of such as fluorine-doped silicon dioxide films, low dielectric
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`constant SOG films and organic polymer films, which have smaller relative dielectric
`constants as compared to silicon dioxide films have been proposed.
`0008
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`
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`Problems the Invention Seeks to Resolve
`
`0009
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`
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`Although the relative dielectric constant of fluorine-doped silicon dioxide films is
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`about 3.3 to 3.7, which is about 20% lower than that of conventional silicon dioxide films,
`fluorine-doped silicon dioxide films are highly hygroscopic and readily absorb moisture
`from the atmosphere, and this results in numerous problems such as the adverse
`increase in the relative dielectric constant of fluorine-doped silicon dioxide films and the
`reaction of SiOH groups with water during thermal treatment resulting in the release of
`H2O gases, the segregation of the fluorine free radicals contained within fluorine-doped
`silicon dioxide films near the surface thereof during thermal treatment and the reaction
`and the reaction of SiOH groups with water during thermal treatment, so that the
`segregated fluorine reacts with the Ti and such of the TiN film that serves as an
`adhesive level forming a TiF film that tends to peel; there are numerous practical
`problems related to the use of fluorine-doped silicon dioxide films.
`0009
`
`
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`HSQ (hydrogen silsesquioxane: composed of Si, O and H atoms, and which
`
`contains about two-thirds the number of O atoms as H atoms) have been considered
`but HSQ films release a larger quantity of moisture when compared with conventional
`silicon dioxide films, and as such it is difficult to process and when forming a metal
`wiring on HSQ films, it is necessary to use patterned metal wiring for the metal film.
`
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` [Document Name] Patent Application
`[Patent] Hei. 11 [1999] – 075519 florine (11. 3. 19)
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`0010
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`
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`Furthermore, because HSQ films have low adhesion vis-à-vis the metal wiring, it
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`is necessary to form a CVD film between the metal wiring and the HSQ film in order to
`form a CVD oxide film as an adhesion layer. However, when a CVD oxide film is formed
`on the metal wiring, there is a CVD oxide film with a large relative dielectric capacitance
`between metal wiring so that the actual line-to-line capacitance is equal to the serial
`capacitance formed by the HSQ film and the CVD film because of the presence of a
`CVD oxide film that has a high dielectric constant resulting in a line-to-line capacitance
`that is larger than when HSOQfilm alone is used.
`0011
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`
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`Because, like low dielectric constant SOG films, organic polymer films do not
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`adhere strongly to the metal wiring, it is necessary to form a CVD oxide film as an
`adhesion layer between the metal wiring.
`0012
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`
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`Furthermore, the etch rate used for etching organic polymer films is
`
`approximately equal to the ash rate at which the resist pattern is ashed with oxygen
`plasma so that there is the problem that it is not possible to use the usual resist
`application process in such situations since organic polymer films are likely to be
`damaged during the ashing and the resist pattern removal. Thus forming a CVD oxide
`film on an organic film and forming a resist film on the CVD oxide film and then etching
`the resist film using the CVD oxide film as an etch stopper (protective film) have been
`proposed.
`
`
`0013
`
`
`However, when a CVD film is formed on an organic polymer film, the surface of
`
`the organic polymer film is exposed to oxygen containing reactive gases so that the
`organic polymer film reacts with the oxygen to take in polar groups such as carbonyl
`groups and ketone groups, and as a result, there is the problem of a disadvantageous
`increase in the relative dielectric constant of the organic polymer film.
`0014
`
`
`
`Also, when the filled-in wiring wherein copper is filled into the organic polymer
`
`film, because organic polymer films do not adhere well to the metal wiring, there is the
`need to form an adhesion layer in the wiring depressions that are formed in the organic
`polymer film by means of something like an adhesion layer made of TiN, etc. but
`because the resistance of a TiN film is high, there is the problem of the effective cross
`sectional area of the metal wiring is decreased, thus negating the low resistance merits
`of using metal wiring with copper.
`
`
`
`Page 12 of 72
`
`

`

` [Receipt Date] Hei.11. 3. 9 [March 9, 1999]
`[Document Name] Patent Application
`[Patent] Hei. 11 [1999] – 075519 florine (11. 3. 19)
`
` Pages: 10/69
`0015
`
`
`
`In consideration of the afore description, the objective has been a method for the
`
`formation of inter-layer films with low dielectric constant whilst using conventional resist
`processing.
`
`
`0016
`
`
`
`Means for Resolving the Issues
`
`
`The 1st method for the formation of wiring structure in accordance with the
`
`present invention includes as the 1st process of the formation of a 1st insulating film over
`the lower-level metal wiring, the 2nd process of the formation of a 2nd insulating film
`wherein the composition differs from that of the 1st insulating film, the 3rd process of the
`formation on the 1st insulating film of a 3rd insulating film wherein the composition differs
`from that of the 2nd insulating film, the 4th process of the formation of a thin film on the
`3rd insulating film, the 5th process of the formation on the thin film of a 1st resist pattern
`wherein there is a plurality of openings for the formation of wiring grooves, the 6th
`process of the etching of the thin film with the use of the 1st resist pattern as a mask
`thus forming a mask pattern out of the thin film so that there are openings for the
`formation of the wiring grooves, the 7th process of the formation on the 3rd insulating film
`of a 2nd resist pattern wherein there is a plurality of openings for the formation of contact
`holes, the 8th process of dry etching the 3rd insulating film under conditions such that the
`3rd insulating film and 1st resist pattern & the 2nd resist pattern re etched at high rate
`whilst the 2nd insulating film is etched at a low rate so that the 3rd insulating film is
`patterned so as to have openings for the formation of contact holes, and the total or
`partial removal of the lower parts of the 1st resist pattern & the 2nd resist pattern, the 9th
`process of dry etching using the mask pattern and the patterned 2nd insulating film as
`the respective masks the 3rd insulating film & the 1st insulating film under conditions
`such that the 1st insulating film & the 3rd insulating film are etched at a high rate and the
`mask pattern & the 2nd insulating film are etched at a low rate so as to respectively form
`wiring grooves and contact holes in the 3rd insulating film & the 1st insulating film, the
`10th process of dry etching the 3rd insulating film & the 1st insulating film using the mask
`pattern & the patterned 2nd insulating film as the respective masks under conditions […]
`
`
`
`Page 13 of 72
`
`

`

` [Receipt Date] Hei.11. 3. 9 [March 9, 1999]
`[Document Name] Patent Application
`[Patent] Hei. 11 [1999] – 075519 (11. 3. 19)
` Pages: 11/69
`[…] such that the 1st insulating film & the 3rd insulating film are etched at a high rate and
`the mask pattern & the 2nd insulating film are etched at a low rate so as to respectively
`form the wiring grooves and the contact holes in the 3rd insulating film & the 1st
`insulating film, and the 11th process of filling the wiring grooves and the contact holes
`with a metal film in order to form upper-level metal wiring and contacts that connect the
`lower-level metal wiring and the upper-level metal wiring.
`0017
`
`
`
`In the 1st method of the method for the formation of the wiring structure, the 3rd
`insulating film is dry etched under conditions such that the 3rd insulating film and the 1st
`resist pattern & the 2nd resist pattern are etched a high rate whilst the 2nd insulating film
`is etched at a low rate so that the patterning of the 3rd insulating film and the removal of
`the 1st resist pattern & the 2nd resist pattern as described in Process 8 so that it not
`necessary to perform the ashing process and the process of removing the 1st resist
`pattern & the 2nd resist pattern using oxygen plasma, which in turn means that because
`it is possible to prevent the 3rd insulating from being damaged during the ashing and the
`resist pattern removal, a low dielectric constant insulating film that would otherwise be
`readily damaged by oxygen plasma may be used for the 3rd insulating film; thus it is
`possible to use a low dielectric constant film for the inter-level insulating film for the
`formation with the use of n ordinal resist application process.
`0018
`
`
`
`Also, the 2nd insulating film can be used as an etching stopper during the course
`of the wiring groove formation by the dry etching of the 3rd insulating film using the mask
`pattern as a mask in Process 10 so that the depth of each of the wiring grooves can be
`equalized with the thickne