Monolithic Spiral Inductors Fabricated Using a VLSI Co-Damascene
`Interconnect Technology and Low-Loss Substrates
`
`J. N. Burghartz, D. C. Edelstein, K. A. Jenkins, C. Jahnes, C. Uzoh,
`E. J. O'Sullivan, K. K. Chan, M. Soyuer, P. Roper, and S. Cordes
`
`IBM Research Division, T.J.Watson Research Center, P.O.Box 218,
`Yorktown Heights, N.Y. 10588, USA, (914)945-3246, burgh@watson.ibm.com.
`
`Abstract
`
`This paper presents spiral inductor structures optimized in a
`Cu-damascene VLSI interconnect technology with use of
`silicon, high-resistivity silicon (HRS), or sapphire substrates.
`Quality factors (Q) of 40 at 5.8 GHz for a 1.4 nH-inductor
`and 13 at 600 MHz for a 80 nH-inductor have been achieved.
`
`(a)
`
`Introduction
`
`The integration of spiral inductors is one of the most
`challenging
`tasks for
`the realization of monolithic rf
`transceivers on silicon substrates. Maximum quality-factors
`(Qmax) up to 24 were obtained by employing five levels of AI
`interconnects, as presented at last year's IEDM (1). While this
`result was based on standard silicon processing, the adoption
`of a low-resistive metal like gold, (2), or copper (Cu), (3), and
`of low-loss Stibstrates such as high-resistivity silicon (HRS),
`(2), sapphire (Ab03), or silicon-on-insulator with a thick
`buried oxide (SOl) give promise to increase the Q even more
`and to enter the domain governed by discrete inductors. In
`this paper, we present the results of a rigorous optimization of
`monolithic inductors by employing the technology options
`given with advanced silicon process technology.
`
`Fabrication Process
`
`M3
`~
`
`(b) H1~
`
`t
`
`Substrate
`
`t
`
`Fig. I Spiral inductor structure in (a) plan view and (b) cross-section. The
`spiral coil was built using the M3 metal layer, and the underpass was at
`M2; the layer Ml was not used.
`
`A three-level Cu-damascene process with 2.5 J.tm-thick Cu(cid:173)
`interconnects and oxide (Si02) isolation, which was similar to
`the technology described in (3), was developed to build spiral
`inductor structures at the upper two metal levels (M2 and M3
`in Fig. 1). The spiral coil was built at M3, and the underpass
`contact was at M2. The first metal level was not fabricated in
`our experiments. The metal layer M2 was formed in a
`single-damascene step, while both the vias V2 and the metal
`layer M3 were fabricated in one dual-damascene process step
`(Fig. 2). A liner film, which acts as a diffusion barrier and
`adhesion promoter, was deposited prior to the metal. The
`dual-damascene process involved two cycles of lithography
`and dry-etching, one Cu-deposition step, removal of the metal
`overburden through chemical-mechanical polishing (CMP),
`and electroless capping of the exposed Cu-surface. The
`
`Cu-resistivity in the metal layers and the vias was about 1.9
`J.t!l-cm.
`
`Three different types of substrates were used (Cul, Cu2, and
`Cu3 in Table I). One set of test devices was built on
`conventional 10 0-cm silicon wafers (Cul). A second series
`of inductors used HRS wafers that were diced from floatzone
`silicon rods (Cu2). A third group of devices was built on
`sapphire substrates, as used in silicon-on-saphire (SOS)
`technology (Cu3).
`
`For comparisons, two Al-interconnect processes with three
`(All, (4)) or five (Al2, (1)) metal levels, which have been
`used in our previous experiments, are described in Table I as
`well. The lateral dimensions of some of the inductors that
`
`0-7803-3393-4 $5.00 © 1996 IEEE.
`
`IEDM 96-99
`
`4.5.1
`
`TSMC Exhibit 1009
`
`Page 1 of 4
`
`

`

`TABLE II
`DIMENSIONS OF THE TEST INDUCTORS
`
`LA2
`
`LA4
`
`LB2
`
`LBS
`
`LBS
`
`Area (j.1ID2
`)
`
`500x500
`
`500x500
`
`226x226
`
`226x226
`
`226x226
`
`No. turns (n)
`
`Wire Width (W)
`
`Wire Space (S)
`
`16
`
`9 j.IID
`
`4 j.IID
`
`8
`
`22 j.IID
`
`4 j.IID
`
`4
`
`6
`
`18 j.IID
`
`16 j.IID
`
`12 j.IID
`
`18 j.IID
`
`10 j.IID
`
`4 j.IID
`
`M1 not used), but a standard silicon substrate (Cu1), had a
`Qmax that came close to the one achieved with the five-level
`Al-structure (Al2), as shown in Table III. The comparison of
`Cu1 and Al2 indicated that a single, 2.5 j..lm-thick Cu-layer
`can nearly substitute for three shunted Al-layers to form the
`spiral coil structure. The Qmax of Cul was -1.7x greater than
`in a comparable three-level metal Al structure (All). With use
`of a HRS substrate, the Qmax was raised to 30, and for a
`represents an
`to 40, which
`substrate even
`sapphire
`improvement of 1.7x over the Qmax of 24 published in (1) and
`a 3.8x increase over the three-level metal process All.
`
`It becomes apparent from Fig. 4 that the slope of Q at low
`frequency depends to first order on the de resistance of the
`spiral coil and on the inductance and is therefore similar for
`the three cases. The comparison of the inductor, which was
`fabricated by using the process Cu1, to those built with the
`
`D Cu1
`0 Cu2
`V Cu3
`
`Frequency 0.1 to 15 GHz
`
`Fig. 3 Smith chart with measured S,, parameters of LB2-structures
`fabricated by using the processes CuI, Cu2, and Cu3.
`
`low-loss substrate processes Cu2 and Cu3 shows that the
`to significantly higher
`improved substrate quality leads
`Qmax-values but also to a shift of the Qmax to a higher
`frequency. The frequency dependence of the inductance and
`the Q can be modeled with good accuracy by using the
`lumpe_d-element model in Fig. 6, as obvious from the example
`
`Fig. 2 Cross-sectional SEM of a five-level Cu-damascene interconnect
`structure with oxide isolation. (Note that the structure is illustrated to
`demonstrate the VLSI capability of the process; the dimensions of metal
`layers, vias, and oxide isolation are different from the ones used for the
`inductor fabrication.)
`
`were fabricated are listed in Table II. According to the two
`different area sizes, the inductors are grouped in two types,
`the LA-type and the LB-type. The LB-type structures were
`the same as the ones used in (1). It is important to note that
`the Cu-damascene process is capable of providing a metal
`pitch as required for VLSI circuits, even though the inductor
`structures fabricated here had coarse dimensions (Fig. 2).
`
`Results and Discussion
`
`One-port S-parameter measurements were performed for
`inductor characterization (Fig. 3). Measurements up to 20
`GHz were carried out on-wafer using high-frequency probes.
`The calibration procedure included de-embedding of the
`on-chip contact pad capacitance and the contact resistance.
`The error in de-embedding the contact resistance was not
`more than 0.2 n.
`
`The inductances and Q-factors of the devices LA2 and LB2
`as a function of frequency are shown in Fig. 4 and Fig. 5. The
`level
`three
`the
`fabricated by using
`inductor LB2,
`Cu-interconnect process (spiral coil at M3, underpass at M2,
`TABLE I
`PARAMETERS OF THE INTERCONNECT PROCESSES
`
`Metal
`Layers
`in Coil
`
`M3
`
`M3/M4/M5
`
`M3
`
`M3
`
`M3
`
`Metal
`Thickness
`(T)
`and Type
`
`2j.IID
`
`4j.IID
`
`2.5 j.IID
`
`2.5 j.IID
`
`2.5 j.IID
`
`All
`
`Al2
`
`Cul
`
`Cu2
`
`Cu3
`
`Substrate
`Resistivity
`and Type
`
`100-cm
`
`100-cm
`
`100-cm
`
`HRS
`
`Sapphire
`
`Underpass/
`Substrate
`Spacing
`(HI)
`
`Coil/
`Substrate
`Spacing:
`(H2)
`
`3.6j.IID
`
`4.5 j.liD
`
`4.5 j.liD
`
`4.5 j.IID
`
`4.5 j.liD
`
`5.7 j.liD
`
`7.0 j.liD
`
`6.5 j.IID
`
`6.5 j.liD
`
`6.5 j.liD
`
`100-IEDM 96
`
`4.5.2
`
`Page 2 of 4
`
`

`

`in Fig. 7. In the model, an ideal inductance Ls, a coil
`resistance· Rs,
`an
`inter-wire
`capacitance Cp,
`oxide
`capacitances Cox, and bulk resistances Rs are considered (4).
`
`TABLE III
`ELECTRICAL CHARACTERISTICS OF THE INDUCTORS
`
`10
`
`-
`-
`
`:I:
`c
`Q)
`()
`
`c 5
`ftS
`t)
`::l
`"tJ
`c
`
`LB2
`
`50
`
`40
`
`LL
`
`LB2
`
`Rdc
`(Q)
`
`I LO
`I Qmax
`I (nH) I atf/
`_l GHz
`
`Rdc
`(Q)
`
`I
`I
`I
`
`LB5
`
`LO
`(nH)
`
`All
`
`1.7
`
`1.35
`
`Al2
`
`0.65
`
`1.45
`
`Cui
`
`0.75
`
`1.35
`
`Cu2
`
`1.05
`
`1.4
`
`10.6/
`3.7
`
`24/
`2.3
`
`18/
`3.7
`30/
`5.2
`
`2.35
`
`2.15
`
`1.04
`
`2.13
`
`0.93
`
`2.13
`
`1.15
`
`2.2
`
`LB8
`
`I Qmax
`I atf/
`GHz)
`
`Rdc
`(Q)
`
`I Qmax
`I LO
`I (nH) I atf/
`GHz
`
`8.8/
`3.8
`
`16/
`2.0
`
`14/
`3.5
`25/
`4.1
`
`4.46
`
`4.9
`
`2.05
`
`5.1
`
`1.76
`
`4.9
`
`2.38
`
`4.95
`
`7.2/
`2.3
`
`11.5/
`1.8
`ll/
`2.1
`16/
`4.3
`
`Cu3
`
`0.67
`
`1.39
`
`I
`
`...
`0 -
`30 g
`b
`20:;
`::l
`"
`
`10
`
`0
`15
`
`00
`
`10
`5
`Frequency (GHz)
`
`Fig. 4
`Inductances and quality factors as functions of frequency for
`LB2-structures fabricated by using processes CuI, Cu2, and Cu3.
`
`500.-------------------------,15
`LA2
`
`...
`10 ~ :.
`.~
`'ii
`::J a
`
`5
`
`0.5
`Frequency (GHz)
`
`Fig. 5
`Inductances and quality-factors as functions of frequency for
`LA2-structures fabricated by using the processes Cui Cu2, and Cu3.
`
`The element parameters describing the inductor LB2 are
`listed in Table IV for the processes Cul, Cu2, and Cu3. Their
`values reflect the process differences: the parameters Ls, Rs,
`and Cp depend mainly on the lateral dimensions. Since the
`lateral inductor layout was identical for the three cases, those
`values were very similar. The comparison of the values
`obtained for the processes Cul and Cu2 shows that the
`different bulk resistivities are properly reflected while the
`oxide capacitance remained the same. The oxide capacitance
`was significantly reduced for the sapphire substrate (Cu3)
`compared to the results with the silicon substrates (Cul and
`Cu2).
`
`40/
`5.8
`
`2.15
`
`33/
`5.6
`
`1.9
`
`4.95
`
`17/
`4.1
`
`LA2
`
`LA4
`
`Rdc
`(Q)
`
`I LO
`I Qmax
`I (nH) I at f/
`_L GHz
`1
`
`All
`
`32.1
`
`86
`
`Al2
`
`---
`
`--
`
`Cui
`
`13.9
`
`80
`
`Cu2
`
`16.8
`
`80
`
`Cu3
`
`14.9
`
`80
`
`3.0/
`0.3
`
`---
`
`8.0/
`0.3
`
`9.4/
`0.6
`
`13/
`0.6
`
`I Qmax
`Rdc I LO
`(Q) I (nH) I at f/
`I GHz
`I
`5.41
`1.0
`
`16.9
`
`4.8
`
`--
`
`---
`
`2.8
`
`16.3
`
`3.4
`
`16.3
`
`3
`
`16.2
`
`---
`
`10/
`0.5
`
`14/
`1.4
`
`17.5/
`1.9
`
`A similar degree of improvement with the low-loss substrate
`processes Cu2 and Cu3 was observed for the other two
`inductors of the same area size, LB5 and LB8, which had
`been discussed last year as well ((1), Table III). Greater
`increases were achieved for large-area structures (LA2 and
`LA4), as obvious from Table III. Even though the Qmax
`becomes typically smaller at large inductance values (1),(2) a
`Qmax of 13 at 600 MHz was measured for a 80 nH-inductor
`fabricated by using the process Cu3.
`
`Fig. 7 shows the Qmax values drawn versus the inductances
`for all inductors fabricated by using the processes Cu l-Cu3. It
`is first obvious from the results that the reduction in substrate
`losses translates into a higher Qmax over the entire range of
`inductances. For each
`inductor area size (LA-type or
`LB-type) there is an obvious trend that small inductances
`combine with a high Qmax and vice-versa. The slope of Qmax
`versus inductance, however, is larger for the small-area
`LB-type structures compared to the LA-type, so that beyond 5
`nH inductance the LA-inductor structures provide the higher
`Qmax. This indicates that, besides the process technology
`improvement discussed in the bulk of this paper, also the
`lateral inductor geometry must be carefully optimized to
`achieve the highest possible Qmax.
`
`4.5.3
`
`IEDM 96-101
`
`Page 3 of 4
`
`

`

`(.)
`
`0 40
`·• .•.•
`"LB" inductors
`-
`··..
`··.
`If
`· ...•
`~3o ···t .... ··-..· .. Cu3
`ca
`· ..... ·· ..•
`:::s
`•• •••
`•• ••
`Cuz· .. ~\.
`0 20
`
`! 10 -:;~.~:!:_=:=i:=_=::::~~
`
`"LA" inductors
`
`==
`
`Sub
`
`Fig. 6 Lumped-element model of the inductors
`
`OL---~-L~~~W----L_J~_L~~
`1
`2 3
`5
`1 0
`20 30 50
`1 00
`Inductance (nH)
`
`Fig. 7 Maximum quality-factors drawn versus the inductances of different
`spiral inductors. LB-type inductors have an area of 226x226 J.lm2
`; the area
`of LA-type devices is 500x500 J.lm2
`• (The figure includes the results from
`inductors which are not listed in Tables II and III.
`
`TABLE IV
`LUMPED-ELEMENT PARAMETERS OF INDUCTORS LB2
`
`Conclusions
`
`Rs
`(Q)
`
`0.75
`
`1.05
`
`0.8
`
`Ls
`(nH)
`
`1.25
`
`1.32
`
`1.32
`
`Cp
`(pF)
`
`0.02
`
`0.03
`
`0.03
`
`Cox
`(pF)
`
`0.25
`
`0.25
`
`O.o2
`
`Rs
`(Q)
`
`550
`
`1800
`
`1400
`
`25
`
`Cui
`
`Cu2
`
`Cu3
`
`5
`
`_4 Q
`J:
`
`s::: -(1)3
`
`(.)
`s:::
`Ctl
`tS2
`:::s
`"0
`s:::
`
`00
`
`LB2 (Cu1)
`
`L
`
`----
`
`Measurement
`Simulation
`5
`10
`Frequency (GHz)
`
`20 ...
`0 -15 g
`
`LL
`I
`~
`10~
`:::s
`0
`
`5
`
`0
`15
`
`Fig. 7 Measured inductance and Q-factor as a function of frequency in
`comparison
`to
`the
`simulated characteristics derived
`from
`the
`lumoed-element model in Fig. 6 with values from Table IV.
`
`Very high quality factors were achieved for inductors
`fabricated in silicon technology by using Cu-damascene
`interconnects and low-loss substrates. It should be noted that
`the best results were achieved with sapphire substrates that
`can be used in a silicon-on-sapphire (SOS) configuration for
`circuit fabrication. Similar results are likely achievable with
`the use of SOl substrates that have a very thick buried oxide.
`The use of HRS-substrates may be more transparent to
`main-stream VLSI fabrication processes, and also for this
`option a considerable increase of the inductor-Q compared to
`a standard silicon substrate was indicated by our experimental
`results.
`
`Acknowledgement
`
`The authors wish to acknowledge the Yorktown silicon facility, and in
`particular J. Stiebritz and C. D'Emic, for carrying out some of the
`processing. J. Harper, Y. Kwark, B. Gaucher, and F. Kaufman are
`acknowledged for helpful discussions. We further like to thank W. Pence, J.
`Ewen, J. Heidenreich, and M. Scheuermanu for their support.
`
`References
`
`(I) J.N.Burghartz et al.. Techn. Dig. IEDM, I 995, pp. 1015-1017.
`(2) K.B.Ashby et al., Proc. BCTM, 1994, pp. 179-182.
`(3) D.C.Edelstein, Proc. lOth Int. VLSI Multi-Level Interconn. Conf., 1995,
`pp. 301-307.
`
`(4) J.N.Burghartz et al., Proc. BCTM, 1996, to be published.
`
`102-IEDM 96
`
`4.5.4
`
`Page 4 of 4
`
`