(12) United States Patent
`Aoi
`
`111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US006197696Bl
`US 6,197,696 Bl
`Mar.6,2001
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) METHOD FOR FORMING
`INTERCONNECTION STRUCTURE
`
`(75)
`
`Inventor: Nobuo Aoi, Hyogo (JP)
`
`OTHER PUBLICATIONS
`
`European Search Report dated Jul. 1, 1999.
`* cited by examiner
`
`(73) Assignee: Matsushita Electric Industrial Co.,
`Ltd., Osaka (JP)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`Primary Examiner-Benjamin L. Utech
`Assistant Examiner-Lynette T. Umez-Eronini
`(74) Attorney, Agent, or Firm-Eric 1. Robinson;
`Peabody LLP
`
`Nixon
`
`(57)
`
`ABSTRACT
`
`(21) Appl. No.: 09/274,114
`
`(22) Filed:
`
`Mar. 23, 1999
`
`(30)
`
`Foreign Application Priority Data
`
`Mar. 26, 1998
`
`(JP) ................................................. 10-079371
`
`Int. Cl? ................................................... HOlL 21!311
`(51)
`(52) U.S. Cl. ............................................. 438/700; 438/706
`(58) Field of Search ...................................... 438/700, 706
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`Kessler et a!. ....................... 438/623
`5,110,712
`5/1992
`5,518,963 *
`Park ..................................... 438/624
`5/1996
`5,635,423 *
`Huang et a!. ........................ 438/638
`6/1997
`7/1997
`Dennison et a!.
`5,651,855
`................... 438/628
`5,702,982 * 12/1997 Lee et a!. ............................. 438/620
`
`FOREIGN PATENT DOCUMENTS
`
`0 425 787 A2
`0 680 085 A1
`6-291193
`7-153842
`9-64034
`9-153545
`
`5/1991 (EP) .............................. H01L/21!90
`11/1995 (EP) ............................ H01L/21!768
`10/1994 (JP) ............................... H01L/21!90
`6/1995 (JP) ............................. H01L/21!768
`3/1997 (JP) ........................... H01L/21!3205
`6/1997 (JP) ............................. H01L/21!768
`
`In a method for forming an interconnection structure, first,
`second and third insulating films and a thin film are sequen(cid:173)
`tially formed over lower-level metal interconnects. Then, the
`thin film is masked with a first resist pattern and etched to
`form a mask pattern with openings for interconnects. Next,
`the third insulating film is masked with a second resist
`pattern and dry-etched such that the third insulating film and
`the first and second resist patterns are etched at a high rate
`and that the second insulating film is etched at a low rate to
`form openings for contact holes in the third insulating film
`and remove the first and second resist patterns. Then, the
`second insulating film is masked with the third insulating
`film and dry-etched such that the second insulating film is
`etched at a high rate and that the first and third insulating
`films are etched at a low rate to form the openings for contact
`holes in the second insulating film. Then, the third and first
`insulating films are masked with the mask pattern and the
`second insulating film, respectively, and dry-etched such
`that the first and third insulating films are etched at a high
`rate and that the mask pattern and the second insulating film
`are etched at a low rate to form wiring grooves and contact
`holes in the third and first insulating films, respectively.
`Finally, upper-level metal interconnects and contacts are
`formed.
`
`15 Claims, 37 Drawing Sheets
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`113
`112
`108
`105A
`104A
`103A
`102A
`J-----.t--...L.......L-,,.a--~~---i --10 1
`100
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`TSMC Exhibit 1001
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`Page 1 of 56
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`Fig. 1 (a)
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`Fig. 1 (b)
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`Fig. 1 (c)
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`106
`105
`104
`103
`102
`101
`100
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`1 - - - - - - - - - f
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`107
`106
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`109
`107
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`105
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`Sheet 2 of 37
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`Fig. 2 (a)
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`Fig. 2 (b)
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`Fig. 2 (c)
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`108
`105A
`~~~~~~--104
`103
`102
`101
`100
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`108
`105A
`104A
`103
`102
`101
`100
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`108
`105A
`104A
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`Sheet 3 of 37
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`Fig. 3 (a)
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`Fig. 3 (b)
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`108
`105A
`~:::t--1 04A
`103A
`102A
`1-----::---L....-...L.~~~~ ~ 101
`100
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`113
`112
`108
`105A
`1--------""'""'r:::'.. [.f-"'-~ ,~::::::t--1 04A
`103A
`102A
`~-L...-.4.~~..::.........LI~-- 101
`100
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`Fig. 3 (c)
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`105A
`104A
`...----...____ 1 0 3 A
`~~;Y::;:=:::::;jk¥t;:::::::::t-- 1 0 2A
`~--L-.L~---1:,;-L-.....<:L..~------ 1 0 1
`100
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`Sheet 4 of 37
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`Fig. 4 (a)
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`Fig. 4 (b)
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`Fig. 4 (c)
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`106
`105
`~--------~~104
`------103
`1 0 2
`l==::;:::;::::;:::;::;::::;::;:::::;::=:::t-
`~-----..--~~~~~._ 101
`100
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`107
`106
`105
`~========~--104
`....--.___ 103
`!==::;::;::;;:::::;::;:::::;:::;:::;::::::::::t---.... 1 0 2
`~-----..--~~~~~---- 101
`100
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`107
`108
`105
`~========~--104
`....--.._-103
`~~~~~~ 102
`101
`100
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`Sheet 5 of 37
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`Fig. 5 (a)
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`Fig. 5 (b)
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`Fig. 5 (c)
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`109
`107
`108
`105
`104
`103
`102
`101
`100
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`108
`105A
`104
`103
`102
`101
`100
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`108
`105A
`104A
`103
`102
`101
`100
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`111 --r-----!----
`11 0 - t - - - - -+
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`Fig. 6 (a)
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`111 --r----...t.--
`110 - - t - - - - -+
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`Fig. 6 (b)
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`108
`105A
`104A
`103A
`102
`101
`100
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`108
`105A
`104A
`103A
`102A
`101
`100
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`Fig. 7 (a)
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`Fig. 7 (b)
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`Fig. 7 (c)
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`109
`107
`108
`105
`104
`103
`102
`101
`100
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`108
`105A
`104
`103
`102
`101
`100
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`108
`105A
`104A
`103
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`111 -r---..J.---
`110 -+----+-
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`Fig. 8 (a)
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`111 -t---+---
`110 -;-----+-
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`Fig. 8 (b)
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`112
`114
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`115
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`Fig. 8 (c)
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`108
`105A
`104A
`103A
`102
`101
`100
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`108
`105A
`104A
`103A
`102A
`101
`100
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`105A
`104A
`103A
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`101
`100
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`Fig. 9 (a)
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`Fig. 9 (b)
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`Fig. 9 (c)
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`206
`.....----___205
`204
`J . . . - - - - - - - - - - 1
`203
`202
`201
`200
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`207
`206
`,_______ - 2 0 5
`l==========::::::t---.... 204
`203
`202
`201
`200
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`209
`207
`208
`----205
`t:::=========:::::t---.... 2 04
`203
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`208
`205A
`~========~--204
`203
`202
`201
`200
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`208
`205A
`204A
`203
`202
`201
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`208
`205A
`204A
`203A
`202
`201
`200
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`Fig. 10 (a)
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`Fig. 10 (b)
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`211 ---r---..a,._-
`21 0 ---r---.J--
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`,--1--...J......,
`1------'1
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`Fig. 10 (c)
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`Fig.11(a)
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`212
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`Fig.11(b)
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`208
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`r:::==r-- 204A
`203A
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`201
`200
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`213
`208
`205A
`)---1"'---L......,, ~~- 204A
`203A
`202A
`201
`200
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`Fig. 11 (c)
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`215
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`205A
`204A
`.----......__203A
`I==~~~;.L;=::::t-- 202A
`~....J:::.....L~~:......d.......-----r-201
`200
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`Fig. 12 (a)
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`Fig. 12 (c)
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`306
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`Fig. 13 (a)
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`Fig. 13 (b)
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`311 ---r---.1-- ,..........__........,
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`Fig. 13 (c)
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`309
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`Fig. 14 (a)
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`Fig.l4(b)
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`Fig.l4(c)
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`311 --1--.j._-
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`308
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`313
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`304A
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`300
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`VI'-'L---"'-'a
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`c=J~::-rr::~~:::::::r- 30 5A
`304A
`314 --r--.ll..J....
`30 3A
`315 ---r---..!4-
`t==~~::::;:fk~:::::}- 30 2A
`~1L~~~~~--3Ql
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`Fig. 16 (a)
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`362 --r---l-- ,.........._...
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`359
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`362--r-~-
`361 --r--..1--
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`358
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`1-----T----L........L~~L...-...a.-~-- 3 51
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`364
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`1------T----L........L~~L...-...a-~-- 351
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`Fig. 17 (c)
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`363
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`'¥~---""'<(.~
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`l==l~~~~~-355A
`365 -r--rL..)...-
`3 54A
`3 66 ---r------u-"Ji
`3 5 3A
`352A
`~-----T-----L........L~~"'----"-L..~- 3 51
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`1 - - - - - - - - - - t
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`406
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`Fig. 18 (b)
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`1 - - - - - - - - - - - - i
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`407
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`1 - - - - - - - - - - 1
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`409
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`Fig. 19 (a)
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`Fig. 19 (b)
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`Fig. 19 (c)
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`1----1
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`409
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`410
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`408
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`l==~+=~~==t--404A
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`412 --r-....j.._-
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`408
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`400
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`414
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`408
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`~-----""'~ ~~,~==t--404A
`403A
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`Fig. 20 (c)
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`413
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`415 ----r---._n,_,
`404A
`416 __, __ .£1.--
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`~~~=;::tk¥t;===l--
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`507
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`... - ..
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`..
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`509
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`511 ---r----t-(cid:173)
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`r======h
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`Fig. 23 (c)
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`561 - t - - - - l - -
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`564 ---r---~
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`559
`556A
`555A
`554
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`553
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`559
`556B
`555A
`554A
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`553
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`U.S. Patent
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`Mar.6,2001
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`Sheet 29 of 37
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`US 6,197,696 Bl
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`Fig. 29 (a)
`
`Fig.29(b)
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`559
`556B
`555B
`554A
`553A
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`551
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`Mar. 6, 2001
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`Sheet 30 of 37
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`US 6,197,696 Bl
`
`- - - - - ......
`..... - .... - -
`.. - .. - - ....
`
`- . ..
`. .. - - .. - -
`.. - ...
`- ..
`.. - -
`..
`..
`...
`
`Fig. 30 (a)
`
`Fig. 30(b)
`
`Fig. 30 (c)
`
`606
`605
`604
`603
`602
`601
`600
`
`607
`606
`605
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`603
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`U.S. Patent
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`Mar. 6, 2001
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`Sheet 31 of 37
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`US 6,197,696 Bl
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`Fig. 31 (a)
`
`608
`....---~605
`1 - - - - - - - - - - l - 604
`603
`602
`601
`600
`
`.. . .. . . ..
`..
`..
`.. - .. - -
`..
`.. . ........... ..
`..
`..
`. .. ...... - - -
`...
`............. - ..
`.. . . .. ...... -
`.. - - - - - -
`..
`.. ...... - ..
`.... - - - - - -
`..
`..
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`- - - - - - - -
`.. . ..
`..
`- ..
`.. - - ..... ..
`
`......... - ..
`..
`- - .... - ..... .
`...... - ..... ..
`
`Fig. 31 (b)
`
`Fig. 31 (c)
`
`609
`608
`605
`604
`603
`602
`601
`600
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`608
`605A
`604
`603
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`Mar. 6, 2001
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`Sheet 32 of 37
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`US 6,197,696 Bl
`
`Fig. 32(a)
`
`610 ---r----1---
`
`,........L-----I_
`
`Fig. 32(b)
`
`612 --r------1
`
`613 -r-------l
`
`Fig. 32 (c)
`
`608
`605A
`604A
`603
`602
`601
`600
`
`608
`605B
`604A
`603A
`602
`601
`600
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`605B
`604B
`603A
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`601
`600
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`Page 33 of 56
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`Mar. 6, 2001
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`Sheet 33 of 37
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`US 6,197,696 Bl
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`Fig. 33 (a)
`
`Fig. 33 (b)
`
`Fig. 33 (c)
`
`656
`655
`654
`653
`652
`651
`650
`
`657
`656
`655
`654
`653
`652
`651
`650
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`657
`658
`655
`654
`653
`652
`651
`650
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`U.S. Patent
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`Mar. 6, 2001
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`Sheet 34 of 37
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`US 6,197,696 Bl
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`Fig. 34 (a)
`
`Fig.34(b)
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`Fig. 34 (c)
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`658
`655
`654
`653
`652
`651
`650
`
`659
`658
`655
`654
`653
`652
`651
`650
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`658
`655A
`654
`653
`652
`651
`650
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`Mar. 6, 2001
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`Sheet 35 of 37
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`US 6,197,696 Bl
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`Fig. 35 (a)
`
`660 ---r-----l--
`661 ---r----l--
`
`Fig.35(b)
`
`662--r----~
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`663 --r-----1
`
`Fig. 35 (c)
`
`658
`655A
`654A
`653
`652
`651
`650
`
`658
`655B
`654A
`653A
`652
`651
`650
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`655B
`654B
`653A
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`651
`650
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`U.S. Patent
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`Mar.6,2001
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`Sheet 36 of 37
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`US 6,197,696 Bl
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`Fig.36
`
`MASK PATTERN(559)
`
`SECOND RESIST PATTERN
`(560)
`
`OPENINGS FOR
`FORMING INTERCONNECTS
`
`OPENINGS FOR
`FORMING CONTACT HOLES
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`Page 37 of 56
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`U.S. Patent
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`Mar. 6, 2001
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`Sheet 37 of 37
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`US 6,197,696 Bl
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`Fig. 37 (a)
`
`560 559
`
`Fig. 37 (b)
`
`510 509
`
`B
`
`t_
`
`B
`
`510
`509
`~~~....L.....J;_ ........ 506A
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`506a
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`514
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`501
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`551
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`564
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`Page 38 of 56
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`US 6,197,696 Bl
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`1
`METHOD FOR FORMING
`INTERCONNECTION STRUCTURE
`
`BACKGROUND OF THE INVENTION
`
`5
`
`The present invention relates to a method for forming an
`interconnection structure in a semiconductor integrated cir(cid:173)
`cuit.
`As the number of devices, integrated within a single
`semiconductor integrated circuit, has been tremendously
`increasing these days, wiring delay has also been increasing
`noticeably. This is because the larger the number of devices
`integrated, the larger line-to-line capacitance (i.e., parasitic
`capacitance between metal interconnects), thus interfering
`with the performance improvement of a semiconductor 15
`integrated circuit. The wiring delay is so-called "RC delay",
`which is proportional to the product of the resistance of
`metal interconnection and the line-to-line capacitance.
`In other words, to reduce the wiring delay, either the
`resistance of metal interconnection or the line-to-line capaci(cid:173)
`tance should be reduced.
`In order to reduce the interconnection resistance, IBM
`Corp., Motorola, Inc., etc. have reported semiconductor
`integrated circuits using copper, not aluminum alloy, as a
`material for metal interconnects. A copper material has a 25
`specific resistance about two-thirds as high as that of an
`aluminum alloy material. Accordingly, in accordance with
`simple calculation, the wiring delay involved with the use of
`a copper material for metal interconnects can be about
`two-thirds of that involved with the use of an aluminum 30
`alloy material therefor. That is to say, the operating speed
`can be increased by about 1.5 times.
`However, the number of devices, integrated within a
`single semiconductor integrated circuit, is expected to fur(cid:173)
`ther increase by leaps and bounds from now on, thus
`increasing the wiring delay considerably. Therefore, it is
`concerned that even the use of copper as an alternate metal
`interconnection material would not be able to catch up with
`such drastic increase. Also, the specific resistance of copper
`as a metal interconnection material is just a little bit higher
`than, but almost equal to, that of gold or silver. Accordingly,
`even if gold or silver is used instead of copper as a metal
`interconnection material, the wiring delay can be reduced
`only slightly.
`Under these circumstances, not only reducing intercon(cid:173)
`nection resistance but also suppressing line-to-line capaci(cid:173)
`tance play a key role in further increasing the number of
`devices that can be integrated within a single semiconductor
`integrated circuit. And the relative dielectric constant of an
`interlevel insulating film should be reduced to suppress the
`line-to-line capacitance. A silicon dioxide film has hereto(cid:173)
`fore been used as a typical material for an interlevel insu(cid:173)
`lating film. The relative dielectric constant of a silicon
`dioxide film is, however, about 4 to about 4.5. Thus, it would 55
`be difficult to apply a silicon dioxide film to a semiconductor
`integrated circuit incorporating an even larger number of
`devices.
`In order to solve such a problem, fluorine-doped silicon
`dioxide film, low-dielectric-constant spin-on-glass (SOG) 60
`film, organic polymer film and so on have been proposed as
`alternate interlevel insulating films with respective relative
`dielectric constants smaller than that of a silicon dioxide
`film.
`The relative dielectric constant of a fluorine-doped silicon
`dioxide film is about 3.3 to about 3.7, which is about 20
`percent lower than that of a conventional silicon dioxide
`
`35
`
`40
`
`2
`film. Nevertheless, a fluorine-doped silicon dioxide film is
`highly hygroscopic, and easily absorbs water in the air,
`resulting in various problems in practice. For example, when
`the fluorine-doped silicon dioxide film absorbs water, SiOH
`groups, having a high relative dielectric constant, are intro(cid:173)
`duced into the film. As a result, the relative dielectric
`constant of the fluorine-doped silicon dioxide film adversely
`increases, or the SiOH groups react with the water during a
`heat treatment to release H2 0 gas. In addition, fluorine free
`10 radicals, contained in the fluorine-doped silicon dioxide
`film, segregate near the surface thereof during a heat treat(cid:173)
`ment and react with Ti, contained in a TiN layer formed
`thereon as an adhesion layer, to form a TiF film, which easily
`peels off.
`An HSQ (hydrogen silsesquioxane) film, composed of Si,
`0 and H atoms, is an exemplary low-dielectric-constant
`SOG film. In the HSQ film, the number of the H atoms is
`about two-thirds of that of the 0 atoms. However, the HSQ
`film releases a larger amount of water than a conventional
`20 silicon dioxide film. Accordingly, since it is difficult to form
`a buried interconnection line in the HSQ film, a patterned
`metal film should be formed as metal interconnects on the
`HSQ film.
`Also, since the HSQ film cannot adhere so strongly to
`metal interconnects, a CVD oxide film should be formed
`between the metal interconnects and the HSQ film to
`improve the adhesion therebetween. However, in such a
`case, if the CVD oxide film is formed on the metal
`interconnects, then the substantial line-to-line capacitance is
`equal to the serial capacitance formed by the HSQ and CVD
`films. This is because the CVD oxide film with a high
`dielectric constant exists between the metal interconnects.
`Accordingly, the resulting line-to-line capacitance is larger
`as compared with using the HSQ film alone.
`An organic polymer film, as well as the low-dielectric-
`constant SOG film, cannot adhere strongly to metal
`interconnects, either. Accordingly, a CVD oxide film should
`be formed as an adhesion layer between the metal intercon(cid:173)
`nects and the organic polymer film, too.
`Moreover, an etch rate, at which an organic polymer film
`is etched, is approximately equal to an ash rate, at which a
`resist pattern is ashed with oxygen plasma. Accordingly, a
`usual resist application process is not applicable in such a
`45 situation, because the organic polymer film is likely to be
`damaged during ashing and removing the resist pattern.
`Therefore, a proposed alternate process includes: forming a
`CVD oxide film on an organic polymer film; forming a resist
`film on the CVD oxide film; and then etching the resist film
`50 using the CVD oxide film as an etch stopper, or a protective
`film.
`However, during the step of forming the CVD oxide film
`on the organic polymer film, the surface of the organic
`polymer film is exposed to a reactive gas containing oxygen.
`Accordingly, the organic polymer film reacts with oxygen to
`take in polar groups such as carbonyl groups and ketone
`groups. As a result, the relative dielectric constant of the
`organic polymer film disadvantageously increases.
`Also, in forming inlaid copper interconnects in the
`organic polymer film, a TiN adhesion layer, for example,
`should be formed around wiring grooves formed in the
`organic polymer film, because the organic polymer film
`cannot adhere strongly to the metal interconnects. However,
`since the TiN film has a high resistance, the effective
`65 cross-sectional area of the metal interconnects decreases.
`Consequently, the intended effect attainable by the use of the
`copper lines, i.e., reduction in resistance, would be lost.
`
`Page 39 of 56
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`

`US 6,197,696 Bl
`
`3
`SUMMARY OF THE INVENTION
`
`5
`
`An object of the present invention is providing a method
`for forming an interconnection structure in which an insu(cid:173)
`lating film with a low dielectric constant can be formed by
`an ordinary resist application process.
`A first method for forming an interconnection structure
`according to the present invention includes the steps of: a)
`forming a first insulating film over lower-level metal inter(cid:173)
`connects; b) forming a second insulating film, having a 10
`different composition than that of the first insulating film,
`over the first insulating film; c) forming a third insulating
`film, having a different composition than that of the second
`insulating film, over the second insulating film; d) forming
`a thin film over the third insulating film; e) forming a first 15
`resist pattern, having a plurality of openings for forming
`wiring grooves, on the thin film; f) etching the thin film
`using the first resist pattern as a mask, thereby forming a
`mask pattern out of the thin film to have the openings for
`forming wiring grooves; g) forming a second resist pattern, 20
`having a plurality of openings for forming contact holes, on
`the third insulating film; h) dry-etching the third insulating
`film under such conditions that the third insulating film and
`the first and second resist patterns are etched at a relatively
`high rate and that the second insulating film is etched at a 25
`relatively low rate, thereby patterning the third insulating
`film to have the openings for forming contact holes and
`removing the first and second resist patterns either entirely
`or partially with respective lower parts thereof left; i)
`dry-etching the second insulating film using the patterned 30
`third insulating film as a mask under such conditions that the
`second insulating film is etched at a relatively high rate and
`that the first and third insulating films are etched at a
`relatively low rate, thereby patterning the second insulating
`film to have the openings for forming contact holes; j) 35
`dry-etching the third and first insulating films using the mask
`pattern and the patterned second insulating film as respective
`masks under such conditions that the first and third insulat(cid:173)
`ing films are etched at a relatively high rate and that the mask
`pattern and the second insulating film are etched at a 40
`relatively low rate, thereby forming wiring grooves and
`contact holes in the third and first insulating films, respec(cid:173)
`tively; and k) filling in the wiring grooves and the contact
`holes with a metal film, thereby forming upper-level metal
`interconnects and contacts connecting the lower- and upper- 45
`level metal interconnects together.
`In the first method of the present invention, the third
`insulating film is dry-etched under such conditions that the
`third insulating film and the first and second resist patterns
`are etched at a relatively high rate and that the second
`insulating film is etched at a relatively low rate, thereby
`patterning the third insulating film and removing the first
`and second resist patterns in the step h). Accordingly, it is
`not necessary to perform the step of ashing and removing the
`first and second resist patterns with oxygen plasma. In other 55
`words, since it is possible to prevent the third insulating film
`from being damaged during ashing and removing a resist
`pattern, a low-dielectric-constant insulating film, which
`would otherwise be damaged easily by oxygen plasma, may
`be used as the third insulating film. As a result, an interlevel 60
`insulating film with a low dielectric constant can be formed
`by an ordinary resist application process.
`In addition, the second insulating film can be used as an
`etch stopper while the wiring grooves are formed by dry(cid:173)
`etching the third insulating film using the mask pattern as a 65
`mask in the step j). Accordingly, the depth of each wiring
`groove can be equalized with the thickness of the third
`
`50
`
`4
`insulating film. That is to say, the depth of the wiring
`grooves can be defined by self-alignment.
`Moreover, the composition of the second insulating film
`is different from that of the third insulating film. Thus, the
`second insulating film can be used as an etch stopper while
`the wiring grooves are formed by dry-etching the third
`insulating film using the mask pattern as a mask in the step
`j).
`In one embodiment of the present invention, the first
`method preferably further includes the step of forming a
`metal adhesion layer over part of the third insulating film
`exposed inside the wiring grooves and part of the first
`insulating film exposed inside the contact holes between the
`steps j) and k).
`In such an embodiment, the adhesion between the upper(cid:173)
`level metal interconnects and the third insulating film and
`between the contacts and the first insulating film can be
`improved.
`In another embodiment of the present invention, the third
`insulating film is preferably mainly composed of an organic
`component.
`In such an embodiment, the conditions employed in the
`step h), i.e., that the third insulating film and the first and
`second resist patterns are etched at a relatively high rate and
`that the second insulating film is etched at a relatively low
`rate, are realized with much more certainty.
`In this embodiment, the step c) preferably includes form(cid:173)
`ing the third insulating film by a CVD process using a
`reactive gas containing perfiuorodecalin.
`Then, a film mainly composed of an organic component
`and having a low relative dielectric constant can be formed
`as the third insulating film with a lot more certainty.
`In another embodiment, the first insulating film is also
`preferably mainly composed of an organic component.
`Then, the conditions employed in the step i), i.e., that the
`second insulating film is etched at a relatively high rate and
`that the first and third insulating films are etched at a
`relatively low rate, are realized with much more certainty. At
`the same time, the conditions employed in the step j), i.e.,
`that the first and third insulating films are etched at a
`relatively high rate and that the mask pattern and the second
`insulating film are etched at a relatively low rate, are also
`realized with much more certainty.
`In an embodiment where the first and third insulating
`films are both mainly composed of organic components, the
`first method preferably further includes the step of forming
`an adhesion layer over part of the third insulating film
`exposed inside the wiring grooves and part of the first
`insulating film exposed inside the contact holes by a plasma
`process using a reactive gas containing nitrogen between the
`steps j) and k).
`In such a case, the adhesion between the upper-level metal
`interconnects and the third insulating film mainly composed
`of an organic component, and between the contacts and the
`first insulating film mainly composed of an organic compo(cid:173)
`nent can be improved substantially without fail.
`In the embodiment where the first insulating film is
`mainly composed of an organic component, the step a)
`preferably includes forming the first insulating film by a
`CVD process using a reactive gas containing perfiuorodeca(cid:173)
`lin.
`In such a case, a film mainly composed of an organic
`component and having a low relative dielectric constant can
`be formed as the first insulating film with a lot more
`certainty.
`
`Page 40 of 56
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`

`US 6,197,696 Bl
`
`10
`
`20
`
`5
`A second method for forming an interconnection structure
`according to the present invention includes the steps of: a)
`forming a first insulating film over lower-level metal inter(cid:173)
`connects; b) forming a second insulating film, having a
`different composition than that of the first insulating film, 5
`over the first insulating film; c) forming a third insulating
`film, having a different composition tha.n that of the sec~nd
`insulating film, over the second insulatmg film; d) formmg
`a thin film over the third insulating film; e) forming a first
`resist pattern, having a plurality of openings for forming
`wiring grooves, on the thin film; f) etching the thin film
`using the first resist pattern as a mask, thereby forming a
`mask pattern out of the thin film to have the openings for
`forming wiring grooves; g) forming a second resist pattern,
`having a plurality of openings for forming contact holes, on 15
`the third insulating film; h) dry-etching the third insulating
`film using the first and second resist patterns as a mask under
`such conditions that the third insulating film is etched at a
`relatively high rate and that the second insulating film and
`the first and second resist patterns are etched at a relatively
`low rate, thereby patterning the third insulating film to have
`the openings for forming contact holes; i) dry-etching the
`second insulating film using the first and second resist
`patterns as a mask under such conditions that the second
`insulating film is etched at a relatively high rate and that the 25
`first and third insulating films and the first and second resist
`patterns are etched at a relatively low rate, thereby pattern(cid:173)
`ing the second insulating film to have the openings f?r
`forming contact holes; j) removing the first and second resist
`patterns; k) dry-etching the third and first insula~ing fil.ms 30
`using the mask pattern and the patterned second msulatmg
`film as respective masks under such conditions that the first
`and third insulating films are etched at a relatively high rate
`and that the mask pattern and the second insulating film are
`etched at a relatively low rate, thereby forming wiring 35
`grooves and contact holes in the third and first insulating
`films, respective! y; and 1) filling in the wiring grooves and
`the contact holes with a metal film, thereby forming upper(cid:173)
`level metal interconnects and contacts connecting the lower(cid:173)
`and upper-level metal interconnects together.
`In the second method of the present invention, even if a
`damaged layer