`
`FILE HISTORY
`US 6,197,696
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`6,197,696
`PATENT:
`INVENTORS: Aoi, Nobuo
`
`TITLE:
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`Method for forming interconnection
`structure
`
`APPLICATION
`NO:
`FILED:
`ISSUED:
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`US1999274114A
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`23 MAR 1999
`06 MAR 2001
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`COMPILED:
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`12 MAY 2015
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`TSMC Exhibit 1012
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`Page 1 of 388
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`03/23/99
`puusd_ O.1,P.E. SCANNED
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`EXAMINER VErh. (ope Bem
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`FILED WITH: [_] DISK(CAF) (riche i
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`(Attached in pochat on right insideflap)
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`BEST COPY
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`PATENT NUMBER
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`The information disclosed herein may be restrietad. Unauthorized disclosure may be prohibited bythe United States Code Title 35, Sections 122, 181 and 368.
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`METHODFOR FORMING INTERCONNECTION STRUCTURE
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`6,197,696
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`SEARCHED
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`«2) United States Patent
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`
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`US 6,197,696 Bl
`
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`(10) Patent No.:
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`
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`
`
`Mar.6, 2001
`(45) Date of Patent:
`Aoi
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`
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`(54) METHOD FOR FORMING
`INTERCONNECTION STRUCTURE
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`
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`(75)
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`
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`
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`Inventor: Nobuo Aoi, Hyogo (JP)
`
`OTHER PUBLICATIONS
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`European Search Report dated Jul, 1, 1999,
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`* ciled by examiner
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`(73) Assignee: Matsushita Electric Industrial Co.,
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`Ltd., Osaka (JP)
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`(*) Notice:
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`Subject to any disclaimer, the termof this
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`is extended or adjusted under 35
`patent
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`U.S.C. 154(b) by 0 days.
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`Primary Examiner—Benjamin L. Utech
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`Assistant Examiner—Lynette ‘T. Umez-Eronini
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`(74) Attorney, Agent, ar Pirm—Eric J. Robinson; Nixon
`
`Peabody LLP
`
`
`(57)
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`ABSTRACT
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`
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`(21) Appl. No.: 09/274,114
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`(22)
`
`
`(30)
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`Filed:
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`Mar. 23, 1999
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`Foreign Application Priority Data
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`REACEG 0 LEP)
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`ac remposncasinimmanan, LO
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`SY TANS rececspcarceeerccepertis HOLL 21/311
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`
`RIN =a MLA scuessincdnetprveneesomvesevaevtatiaceecect’ 438/700; 438/706
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`
`
`(58)
`Field of Search... 458/700, 706
`
`(56)
`
`
`References Cited
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`
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`U.S. PATENT DOCUMENTS
`
`5,110,712
`Si(9G> ess leg tt alo. scar ceeae 438/623
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`
`
`SBIR, FSVGG) PRE occ ccicscceresnsesaceraes-coanesan 438/624
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`
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`
`
`6/1997 Huang et al.
`-......—.
`we 438/638
`5,635,423 *
`
`
`7/1997 Dennisonet al.
`....
`wee 458/628
`5,651,855
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`
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`S, fIZO82 * T2OOT Leciet ale cee sscicsasscessescostetiat 438/620
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`
`
`FOREIGN PATENT DOCUMENTS
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`In a method for forming an interconnection structure, first,
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`second and third insulating films and a thin film are sequen-
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`tially formed over lower-level metal interconnects. Then, the
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`thin film is masked with a first resisi pattern and etched lo
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`form a mask pattern with openings for interconnects. Next,
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`the third insulating film is masked with a second resist
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`pattern and dry-etched such that thethird insulating film and
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`the first and second resist patterns are etched at a high rate
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`and that the second insulating film is etched at a low rate to
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`form openings for contact holes in the third insulating film
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`and remove the first and second resist patlerns. Then, the
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`secondinsulating film is masked with the third insulating
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`film and dry-etched such that the second insulating film is
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`etched at a high rate and that the first and third insulating
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`films are etched at a low rate to form the openingsfor contact
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`holes in the second insulating film. ‘Then, the third and first
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`insulating films are masked with the mask pattern and the
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`second insulating film, respectively, and dry-etched such
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`that the first and (hird insulating films are etched at a high
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`rate and that the mask pattern and the second insulating film
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`are etched at a low rate to form wiring grooves and contact
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`SAOGL (EP) ction. HOLLZTSO
`0 425 787 A2
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`holes in the third and first
`insulating films, respectively.
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`(EPY ccccscss
`ae HOUL/21/768
`0 680 085 Al
`LV I995:
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`Finally, upper-level metal
`interconnects and contacts are
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`6-291193 VV T994) CTP)isecceesteenssscsstiesiennass HOLL/21/90
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`formed,
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`7-153842
`O/LGOS? CIP), Ginnsassinsemcae HOLL/21/768
`
`
`9-64034
`serceaeges
`wee HOIL/21/3205
`BALO97F TP).
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`6/1997 (IP) -..eececsesteeteeeeeees HOLL/21/768
`9-153545
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`15 Claims, 37 Drawing Sheets
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`oye;VNSk!
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`Fig. 8(b)
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`Fig. 15 (a)
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`p=te US 6,197,696 B1
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`Fig. 15 (b)
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`509
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`Fig. 22 (b)
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`Fig. 23 (a) a
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`Fig. 24 (b)
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`959
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`Fig. 25(c)
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`559
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`Fig. 26(d) ™
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`Fig. 33 (b)
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`MASK PATTERN (559)
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`film. Nevertheless, a Huorine-dopedsilicon dioxide film is
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`resulting in various problemsin practice, For example, when
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`groups, having a high relative dielectric constant, are intro-
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`constant of the fluorine-dopedsilicon dioxide film adversely
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`increases, or the SIOH groups react with the water during a
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`film, segregate near the surface thereof during a heat treat-
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`thereon as an adhesion layer, to form a TiFfilm, which easily
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`An HSQ (hydrogensilsesquioxane) film, composed ofSi,
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`is an exemplary low-diclectric-constant
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`SOG film. In the HSQ film, the number of the H atoms is
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`silicon dioxide film. Accordingly,sinceit is difficult to form
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`a buried interconnection line in the HSQ film, a patterned
`metal film should be formed as metal interconnects on the
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`HSQ film.
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`interconnects, a CVD oxide film should be formed
`metal
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`between the metal
`interconnects and the HSQ film to
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`improve the adhesion therebetween. However,
`in such a
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`if the CVD oxide film is
`formed on the metal
`case,
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`interconnects, then the substantial line-to-line capacitance is
`equal to the serial capacitance formed by the HSQ and CVD
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`films. This is because the CVD oxide film with a high
`dielectric constant exists between the metal interconnects.
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`Accordingly, the resulting line-to-line capacitance is larger
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`as compared with using the HSQfilm alone.
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`An organic polymer film, as well as the low-dielectric-
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`constant SOG film, cannot adhere strongly to metal
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`interconnects, either. Accordingly, a CVD oxide film should
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`be formed as an adhesion layer between the metal intercon-
`nects and the organic polymer film, loo.
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`Moreover, an etch rate, at which an organic polymer film
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`is etched, is approximately equal to an ash rate, at which a
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`resist pattern is ashed with oxygen plasma. Accordingly, a
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`usual resist application process is not applicable in such a
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`situation, because the organic polymerfilm is likely to be
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`damaged during ashing and removing the resist pattern.
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`Therefore, a proposed alternate process includes: forming a
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`CVDoxide film on an organic polymerfilm; forminga resist
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`film on the CVD oxide film; and then etching the resist film
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`using the CVD oxidefilm as an etch stopper, or a protective
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`film.
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`a
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`10
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`ee a
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`However, during the step of forming the CVD oxide film
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`on the organic polymer film,
`the surface of the organic
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`polymerfilm is exposed to a reactive gas containing oxygen.
`Accordingly, the organic polymerfilm reacts with oxygen to
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`take in polar groups such as carbonyl groups and ketone
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`groups. As a result, the relative dielectric constant of the
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`organic polymerfilm disadvantageously increases.
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`Also,
`in forming inlaid copper
`interconnects in the
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`organic polymer film, a TiN adhesion layer, for example,
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`should be formed around wiring grooves formedin the
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`organic polymer film, because the organic polymer film
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`cannot adhere strongly to the metal interconnects. However,
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`since the TiN film has a high resistance,
`the effective
`5 cross-sectional area of the metal
`interconnects decreases.
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`Consequently, the intendedeffect attainable by the use of the
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`copperlines, ie., reduction in resistance, would be lost.
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`oO)
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`1
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`METHOD FOR FORMING
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`INTERCONNECTION STRUCTURE
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`
`BACKGROUND OF THE INVENTION
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`The present invention relates to a method for forming an
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`interconnection structure in a semiconductor integrated cir-
`cuit.
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`integrated within a single
`As the number of devices,
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`semiconductor integrated circuil, has been tremendously
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`increasing these days, wiring delay has also been increasing
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`noticeably. This is because the larger the number of devices
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`integrated, the larger line-to-line capacitance (i.c., parasitic
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`capacitance between metal interconnects), thus interfering
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`with the performance improvement of a semiconductor
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`integrated circuit, The wiring delay is so-called “RC delay”,
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`which is proportional to the product of the resistance of
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`metal interconnection and the line-to-line capacitance,
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`In other words,
`to reduce the wiring delay, either the
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`resistance of metal interconnection or the line-to-line capaci-
`tance should be reduced.
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`In order to reduce the interconnection resistance, IBM
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`Corp., Motorola,
`Inc., etc. have reported semiconductor
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`integrated circuits using copper, not aluminum alloy, as a
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`material for metal interconnects. A copper material has a
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`specific resistance about two-thirds as high as that of an
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`aluminum alloy material. Accordingly, in accordance with
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`simple calculation, the wiring delay involved with the use of
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`a copper material
`for metal
`interconnects can be about
`two-thirds of that involved with the use of an aluminum
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`alloy material therefor. That is to say, the operating speed
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`can be increased by about 1.5 times.
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`integrated within a
`However,
`the number of devices,
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`single semiconductor integrated circuit, is expected to fur-
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`ther increase by leaps and bounds from now on,
`thus
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`increasing the wiring delay considerably. Therefore,
`it is
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`concerned that even the use of copper as an alternate metal
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`interconnection material would not be able to catch up with
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`such drastic increase. Also, the specific resistance of copper
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`as a metal interconnection materialis just a little bit higher
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`than, but almost equalto, that of gold or silver. Accordingly,
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`even if gold or silver is used instead of copper as a metal
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`interconnection material, the wiring delay can be reduced
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`only slightly.
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`Under these circumstances, not only reducing intercon-
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`nection resistance but also suppressing line-to-line capaci-
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`tance play a key role in further increasing the number of
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`devices that can be integrated within a single semiconductor
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`integrated circuit. And the relative dielectric constant ofan
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`interlevel insulating film should be reduced to suppress the
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`line-to-line capacitance. A silicon dioxide film has hereto-
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`fore been used as a typical material for an interlevel insu-
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`lating film. The relative dielectric constant of a silicon
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`dioxide film is, however, about 4 to about 4.5. Thus, it would
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`be difficult to apply a silicon dioxide film to a semiconductor
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`integrated circuit incorporating an even larger number of
`devices.
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`In order to solve such a problem, fluorine-doped silicon
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`dioxide film,
`low-dielectric-constant spin-on-glass (SOG)
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`film, organic polymerfilm and so on have been proposed as
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`alternate interlevel insulating films with respective relative
`dielectric constants smaller than that of a silicon dioxide
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`film.
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`The relative dielectric constant ofa fluorine-doped silicon
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`dioxide film is about 3.3 to about 3.7, which is about 20
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`percent lower than that of a conventional silicon dioxide
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`Page 45 of 388
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`Page 45 of 388
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`

`

`3
`SUMMARY OF THE INVENTION
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`US 6,197,696 B1
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`4
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`the depth of the wiring
`is to say,
`insulating film, That
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`grooves can be defined by self-alignment.
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`Moreover, the composition of the secondinsulating film
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`is different from that of the third insulating film. Thus, the
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`secondinsulating film can be used as an etch stopper while
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`the wiring grooves are formed by dry-etching the third
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`insulating film using the mask pattern as a mask in the step
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`})-
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`a
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`10
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`An object ofthe present invention is providing a method
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`for forming an interconnection structure in which an insu-
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`lating film with a low dielectric constant can be formed by
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`an ordinary resist application process.
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`A first method for forming an interconnection structure
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`according to the present invention includes the steps of: a)
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`forming a first insulating film over lower-level metal inter-
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`the first
`In one embodiment of the present invention,
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`connects; b) forming a second insulating film, having a
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`method preferably further includes the step of forming a
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`different composition than that of the first insulating film,
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`metal adhesion layer over part of the third insulating film
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`over the first insulating film; c) forming a third insulating
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`exposed inside the wiring grooves and part of the first
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`film, having a different composition than that of the second
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`insulating film exposed inside the contact holes between the
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`insulating film, over the second insulating film; d) forming
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`steps j) and k),
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`ee a
`a thin film over the third insulating film; e) formingafirst
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`In such an embodiment, the adhesion between the upper-
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`resist pattern, having a plurality of openings for forming
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`level metal interconnects and ihe third insulating film and
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`wiring grooves, on the thin film; f) etching the thin film
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`between the contacts and the first insulating film can be
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`using the first resist pattern as a mask, thercby forming a
`improved,
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`mask pattern out of the thin film to have the openings for
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`In another embodiment of the present invention, the third
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`forming wiring grooves; g) forming a secondresist pattern,
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`insulating film is preferably mainly composed ofan organic
`having a plurality of openings for forming contact holes, on
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`the third insulating film; h) dry-etching the third insulating
`component.
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`film under such conditionsthat the third insulating film and
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`In such an embodiment, the conditions employed in the
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`the first and secondresist patterns are etched at a relatively
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`step h), i.e,, that the third insulating film and the first and
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`high rate and that the second insulating film is etched at a
`secondresist patterns are etched at a relatively high rate and
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`relatively low rate, thereby patterning the third insulating
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`that the second insulating film is etched at a relatively low
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`film to have the openings for forming contact holes and
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`rate, are realized with much more certainty.
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`removing the first and second resist patterns either entirely
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`In this embodiment, the step c) preferably includes form-
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`or partially with respective lower parts thereof left;
`1)
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`ing the third insulating film by a CVD process using a
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`dry-etching the second insulating film using the patterned
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`reaclive gas containing perfluorodecalin.
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`thirdinsulating film as. a mask under such conditionsthat the
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`Then, a film mainly composed of an organic component
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`secondinsulating film is etched at a relatively high rate and
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`and having a low relative dielectric constant can be formed
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`the first and third insulating films are etched at a
`that
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`as the third insulating film with a lot more certainty.
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`relatively low rate, thereby patterning the second insulating
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`In another embodiment, the first insulating film is also
`film to have the openings for forming contact holes; j)
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`preferably mainly composed of an organic component.
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`dry-etching the third andfirst insulating films using the mask
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`Then, the conditions employedin the step i), i.e., that the
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`pattern and the patterned secondinsulating film as respective
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`second insulating film is etched at a relatively high rate and
`masks under such conditions that the first and third insulat-
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`the first and third insulating films are etched at a
`that
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`ing films are etched at a relatively high rate and that the mask
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`relatively low rate, are realized with much morecertainty. At
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`pattern and the second insulating film are etched at
`a
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`the same time, the conditions employed in the step j), Le.,
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`relatively low rate,
`thereby forming wiring grooves and
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`that
`the first and third insulating films are etched at a
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`contact holes in the third and first insulating films, respec-
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`relatively high rate and that the mask pattern and the second
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`tively; and k) filling in the wiring grooves and the contact
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`insulating film are etchedat a relatively low rate, are also
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`holes with a metal film, thereby forming upper-level metal
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`realized with much more certainty.
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`interconnects and contacts connecting the lower- and upper-
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`In an embodiment where the first and third insulating
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`level metal interconnects together.
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`films are both mainly composed of organic components, the
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`invention, the third
`In the first method of the present
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`first method preferably further includes the step of forming
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`insulating film is dry-etched under such conditions that the
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`an adhesion layer over part of the third insulating film
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`third insulating film and the first and second resist patterns
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`exposed inside the wiring grooves and part of the first
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`are etched at a relatively high rate and that
`the