US006100184A
`p15
`United States Patent
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`6,100,184
`[11] Patent Number:
`[45] Date of Patent:
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`Zhaoet al.
`Aug.8, 2000
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`[54] METHOD OF MAKING A DUAL
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`DAMASCENE INTERCONNECT
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`STRUCTURE USING LOW DIELECTRIC
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`CONSTANT MATERIAL FOR AN
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`INTER-LEVEL DIELECTRIC LAYER
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`[75]
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`Inventors: Bin Zhao,Irvine, Calif; Prahalad K.
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`Vasudey, Austin, Tex.; Ronald S.
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`Horwath, Santa Clara; Thomas E.
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`Seidel, Sunnyvale, both of Calif; Peter
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`M.Zeitzoff, Austin, ‘Icx.
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`[73] Assignees: Sematech, Inc., Austin, Tex.; Lucent
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`Technologies Inc., Murray Hill, N.J.
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`[21] Appl. No.: 08/914,995
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`Filed:
`Aug. 20, 1997
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`[22]
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`os
`[51]
`Int. Ch? oe.
`. HOLL 21/4763
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`_.438/638;“438/622; 438/623;
`[52] U.S. Chow...
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`438/627,438/643: 438/636; 438/637; 438/638;
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`438/648; 438/653; 438/656, 438/672; 438/685;
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`438/687; 438/902
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`costes
`[58] Field of Search .
`.. 438/622, 623,
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`438/627,637,638,"639,‘640, 666, 668.6,
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`672, 643, 678, 685, 902, 629, 636, 648,
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`653, 656, 687
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`[56]
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`4,789,648
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`5,635,423
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`5,695,810
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`5,731,245
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`5,739,579
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`5,753,967
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`References Cited
`
`
`U.S. PATENT DOCUMENTS
`
`
`
`12/1988 Chowet al. were 437/225
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`6/1997 Huang etal. ..
`w» 437/195
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`
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`12/1997 Dubin et al.
`...
`wee 427/96
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`
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`3/1998 Joshiet al.
`... 438/705
`
`
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`12/1997 Chianget al
`we 257/635
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`5/1998 LN vsscscsssssssssvssssseesessssssssessssee 257/635
`
`
`
`OTHER PUBLICATIONS
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`
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`“A Novel Sub-Half Micron Al-Cu Via Plug Interconnect
`
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`
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`
`
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`Using LowDielectric Constant Material as Inter—Level
`
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`Dielectric”, Zhao et al., IEEE Electron Device Letters, vol.
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`18, No. 2, I'eb. 1997, pp. 57-59.
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`“Low Capacitance Multilevel Interconnection Using Low-e
`Organic Spin-on Glass for Quarter—Micron High-Speed
`
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`ULSIs”, Furusawaet al., 1995 Symposium on VLSI Tech-
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`
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`nology Digest of Technical Papers, pp. 59-60.
`
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`“Low-k Organic Spin—-on Materials in a Non—Etchback
`
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`Interconnect Strategy”, J. Wacterloos ct al., DUMIC Con-
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`
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`ference, Feb. 20-21, 1996, pp. 52-59.
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`“Integration of BPDA-PDAPolyimide with Two levels of
`
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`Interconnects’, Wetzel
`al., 1995 Material
`AL(Ci)
`et
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`Research Society Symposium Proceedings, vol. 381, pp.
`217-229.
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`“A Novel 0.25 um Via Plug Process Using Low Temperature
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`CVD AT/TIN”, Dixit et al., Dec. 10-13, 1995, International
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`Electron Devices Meeting, pp. 10.7.1-10.7.3.
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`“Single Step PVD Planarized AluminumInterconnect with
`Low-e Organic ILD for High Performance and Low Cost
`
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`ULSI”, Zhao et al., 1996 Symposium on VLSI Technology
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`Digest of Technical Papers, pp. 72-73.
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`“A Highly Reliable Low Temperature Al-Cu Linve/Via
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`Metallization for Sub—Half Micrometer CMOS”,Joshiet al.,
`
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`IEEE Electron Device Letters, vol. 16, No. 6, Jun. 1995, pp.
`
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`233-235.
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`“A Planarized Multilevel Interconnect Scheme with Embed-
`
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`ded Low-Dieleciric—Constant Polymers for Sub—Quarter—
`Micron Applications’, Jeng et al., 1994 Symposium on
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`VLSI Technology Digest of Technical Papers, pp. 73-74.
`
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`“On Advanced Interconnect Using Low Dielectric] Constant
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`Materials as Inter-Level Diclectrics”, Zhao ct al., 1996,
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`Material Research Society Symposium Proceedings vol.
`427, pp. 415-427.
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`“Electromigration Reliability of Tungsten and Aluminum
`Vias and Improvements Under AC Current Stress”, Tao et
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`
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`al., IEEE Transactions on Electron Devices, vol. 40, No. 8,
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`Aug. 1993, pp. 1398-1405.
`
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`“Planar Copper—Polyimide Back End of the Line Intercon-
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`
`
`
`nections for ULSI Devices,” B. Luther ct al., 1993 VMIC
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`Convterence, Jun. 8-9, 1993, pp. 15-21.
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`Pending Patent Application titled, “Use of Cobalt Tungsten
`Phosphide as a Barrier Material for Copper Metallization”,
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`Serial No. 08/754,600,filed Nov. 20, 1996.
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`Primary Examiner—obnF. Niebling
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`Assistant Examiner—David A. Zarneke
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`[57]
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`ABSTRACT
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`A technique for fabricating a dual damascene interconnect
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`structure using a low diclectric constant matcrial as a
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`dielectric layer or layers. A lowdielectric constant (low-€)
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`dielectric material is used to form an inter-level dielectric
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`CLD) layer between metallization layers and in which via
`and trench openings are formed in the low-€
`ITD. The dual
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`damascene technique allows for both the via and trench
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`openings to be filled at the same time.
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`12 Claims, 6 Drawing Sheets
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`WWWw&
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`7WD\11
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`Page 1 of 13
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`TSMC Exhibit 1010
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`U.S. Patent
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`6,100,184
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`1
`METHOD OF MAKING A DUAL
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`DAMASCENE INTERCONNECT
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`STRUCTURE USING LOW DIELECTRIC
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`CONSTANT MATERIAL FOR AN INTER-
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`LEVEL DIELECTRIC LAYER
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
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`The present inventionrelates to the field of semiconductor
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`wafer processing and, more particularly, to a technique for
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`fabricating a dual damasceneinterconnect structure in which
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`low dielectric constant dielectric layers are used for the
`inter-level dielectric.
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`2. Background of the Related Art
`In the manufacture of devices on a semiconductor wafer,
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`it is now the practice to fabricate multiple levels of conduc-
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`tive (typically metal) layers above a substrate. The multiple
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`metallization layers are employed in order to accommodate
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`higher densities as device dimensions shrink well below one
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`micron design rules. Likewise,
`the size of interconnect
`structures will also need to shrink, in order to accommodate
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`the smaller dimensions. Thus, as integrated circuit technol-
`ogy advances into the sub-0.25 micron range, more
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`advanced interconnect architecture and new materials are
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`required.
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`One such architecture is a dual damascene integration
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`scheme in which a dual damascenestructure is employed.
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`The dual damascene process offers an advantage in process
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`simplification by reducing the process steps required to form
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`the vias and trenches for a given metallization level. The
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`openings, for the wiring of a metallization level and the
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`underlying via connecting the wiring to a lower metalliza-
`tion level, are formed at the same time. The procedure
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`provides an advantage in lithography and allows for
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`improvedcritical dimension control. Subsequently, both the
`via and the trench can befilled utilizing the same metal-
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`filling step, thereby reducing the numberof processing steps
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`required. Because of the simplicity of the dual damascene
`process, newer materials can now cost-effectively replace
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`the use of the existing aluminum/SiO, (silicon dioxide)
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`One such newer material is copper. The use of copper
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`metallization improves performance and reliability over
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`aluminum,but copperintroduces additional problems which
`are difficult to overcome when using known techniques for
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`aluminum. For example, in conventional aluminum inter-
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`connect structures, a barrier layer is usually not required
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`between the aluminum metal line and an SiO. inter-level
`dielectric (ILD). However, when copperis utilized, copper
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`must be encapsulated from the surrounding ILD, since
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`copper diffuses/drifts easily into the adjoining dielectric.
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`Once the copper reaches the silicon substrate, it will sig-
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`nificantly degrade the device’s performance.
`In order to encapsulate copper, a barrier layer of somesort
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`is required to separate the copper from the adjacent material
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`(s). Because copper encapsulation is a necessary step requir-
`ing a presence of a barrier material to separate the copper,
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`other materials can now besubstituted for the SiO, as the
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`material for ILD. Replacing the SiO, by a low-dielectric
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`constant (low-€) material reduces the interline capacitance,
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`thereby reducing the RC delay, cross-talk noise and power
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`dissipation in the interconnect. However,
`is generally
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`necessary to have a barrier (or liner) present between the
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`interconnect and the low-€
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`action between the interconnect and the low-E ILD and also
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`to provide adhesion between them. This barrier is desirable
`even when aluminum is utilized for the interconnect.
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`films for inte-
`There are generally two types of low-€
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`grated circuit applications. One group is comprised of the
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`modified SiO, materials, such as fluorinated oxide (add
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`limited F into SiO.) and silsesquioxane (add limited H or
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`C-based organic elements to SiO,). The other group is
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`comprised of the organic materials, such as polyimides and
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`polymers, having completely different molecular structures
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`in comparison to SiO,. One advantage of organic low-E
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`films is that they offer a lower dielectric constant than the
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`modified SiO, materials.
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`One knowntechnique of utilizing organic low-€ dielec-
`tric material for damascene interconnect
`is described in
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`“Planar Copper-Polyimide Back End Of The Line Intercon-
`nections For ULSI Devices;” B. Luther et al.; 1993 VMIC
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`Conference; Jun. 8-9, 1993; pp. 15-21. However, the tech-
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`nique described is for a single damascene process. The
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`present
`invention describes the use of low-€
`dielectric
`material in a dual damascene process for use as an ILD.
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`SUMMARYOF THE INVENTION
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`The present invention describes a technique for fabricat-
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`ing a dual damascene interconnect structure using a low
`dielectric constant material as a dielectric layer or layers. A
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`low dielectric constant (low-€) dielectric material is used to
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`form an inter-level dielectric ILD) layer between metalli-
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`zation layers and in which via and trench openings are
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`formed in the low-€
`ILD. The dual damascene technique
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`allowsfor both the via and trench openingsto befilled at the
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`same time. In the preferred embodiment, an organic low-E
`dielectric material is selected.
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`A dielectric separation layer is deposited over an under-
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`lying conductive region, which can be another interconnect
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`or a doped region. Next, a first low-€ dielectric ILD layeris
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`deposited followedbya first dielectric etch-stop layer. Then,
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`a via window is formed in the first etch-stop layer.
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`Subsequently, a second low-€
`dielectric ILD layer
`is
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`deposited, followed by a second dielectric etch-stop layer.
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`Next, a trench window is formed in the second etch-stop
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`layer.
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`layers are formed
`In the preferred embodiment, the low-€
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`from an organic material. The two etch-stop layers are
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`comprised of a different material from the dielectric sepa-
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`ration layer, in order to allow for high etch selectivity. The
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`dielectric ILD layers are anisotropically etched to
`low-€
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`removethe low-E material under the openings. The etching
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`step etches the low-€ material to form the via and trench
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`openings. Next, the exposed portion of the first dielectric
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`layer at the bottom of the via opening is etched to expose the
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`underlying conductive region.
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`Subsequently, the via and trench openingsare filled with
`a conductive material. With the preferred embodiment, a
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`conformal barrier or encapsulation layer is first deposited,
`followed by a metal fill, such as copper or aluminum.
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`Chemical-mechanical polishing is then utilized to polish
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`away the excess metal residing above the trench region.
`In an alternative embodiment, when copper is used for
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`metallization, a selective deposition process is employed on
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`the underlying interconnect. The selective deposition of a
`barrier material allows for a formation of a barrier cap only
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`over the exposed copper, so that the blanket deposition of the
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`dielectric separation layer is not needed.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIG. 1 is a cross-sectional view of a conductive region
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`formed within a dielectric layer and in which an interconnect
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`Page 8 of 13
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`6,100,184
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`3
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`structure of the preferred embodimentis subsequently fab-
`ricated thereon.
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`FIG. 2 is a cross-sectional view showing a deposition of
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`a dielectric separation layer onto the structure of FIG. 1.
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`FIG. 3 is a cross-sectional view showing a deposition of
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`a first low-€ dielectric ILD layer over the structure of FIG.
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`2 and a subsequent deposition of a first dielectric etch-stop
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`layer over the first ILD layer.
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`FIG. 4 is a cross-sectional view showing a deposition of
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`a patterned photoresist layer atop the structure of FIG. 3, in
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`which a widow opening is formed to exposea portion of the
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`underlying etch-stop layer.
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`FIG. 5 is a cross-sectional view showing the widow
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`opening pattern of FIG. 4 being transferred on to the first
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`etch-stop layer to define a via opening.
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`FIG. 6 is a cross-sectional view showing a deposition of
`a second low-€
`dielectric ILD layer over the structure of
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`FIG. 5 and a subsequent deposition of a second etch-stop
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`layer over the second ILD dielectric layer.
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`FIG. 7 is a cross-sectional view showing a deposition of
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`a patterned photoresist layer atop the structure of FIG. 6, in
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`which another window opening is formed to expose a
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`portion of the underlying second etch-stop layer.
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`FIG. 8 is a cross-sectional view showing the window
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`opening pattern of FIG. 7 being transferred on to the second
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`etch-stop layer to define a trench opening.
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`FIG. 9 is a cross-sectional view showing an anisotropic
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`etching of the first and second low-€ dielectric ILD layers
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`of FIG. 8 in which the etching is performed through the
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`trench and via openings.
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`FIG. 10 is a cross-sectional view showing an etching of
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`the exposed separation layer at the bottom of the via opening
`shownin FIG. 9.
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`FIG. 11 is a cross-sectional view of a deposition of a
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`conformal barrier layer on the structure shown in FIG. 10
`and a subsequent deposition of a conductive material to fill
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`in the via and trench openings.
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`FIG. 12 is across-sectional view showing the removal of
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`the excess barrier layer and conductive materials residing on
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`the surface for the structure of FIG. 11 by performing
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`chemical-mechanical polishing.
`FIG. 13 is a cross-sectional view of a structure of an
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`alternative embodiment that is equivalent to the structure
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`shown in FIG. 2, but in which a conductive barrier layer is
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`selectively deposited only onto the underlying conductive
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`region.
`FIG. 14 is a cross-sectional view of a structure that is
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`equivalent to the structure shown in FIG. 10, but in which
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`the selectively deposited conductive barrier layer of FIG. 13
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`is employed.
`FIG. 15 is a cross-sectional view of a structure that is
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`equivalent to the structure shown in FIG. 11, but in which
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`the selectively deposited conductive barrier layer of FIG. 13
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`is employed.
`is
`FIG. 16 a cross-sectional view of a structure that
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`equivalent to the structure shown in FIG. 12, but in which
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`the selectively deposited conductive barrier layer of FIG. 13
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`is employed.
`DETAILED DESCRIPTION OF THE
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`
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`PREFERRED EMBODIMENTS
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`Atechniquefor fabricating a dual damasceneinterconnect
`structure using a low dielectric constant material as a
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`dielectric layer or layers is described.
`In the following
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`5
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`Page9 of 13
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`4
`description, numerousspecific details are set forth, such as
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`specific structures, materials, processes, etc.,
`in order to
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`provide a thorough understanding of the present invention.
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`However,it will be appreciated by oneskilled in the art that
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`the present invention may be practiced without these specific
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`details.
`In other instances, well known techniques and
`structures have not been described in detail in order not to
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`obscure the present invention. It
`is to be noted that the
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`present invention is described in reference to a dual dama-
`scene interconnect structure in which aluminum or copperis
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`used as the metal for
`the interconnect. However,
`is
`it
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`appreciated that other structures and conductive materials
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`can be readily implemented without departing from the spirit
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`and scope of the present invention.
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`Referring to FIG. 1, it shows a formation of an intercon-
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`nect structure in which a conductive region 10 resides within
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`a dielectric layer 11. The conductive region 10 is comprised
`of a conductive material which can be of any of a variety of
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`materials used for forming interconnects on a semiconductor
`wafer, such as a silicon wafer. Typically, a metal, such as
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`aluminum (Al)orits alloy, is used for forming the conduc-
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`tive regions on a wafer. The dielectric layer 11 is formed
`from a dielectric material, whichis typically used to form an
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`inter-level dielectric (ILD) layer. An ILD layer is used to
`separate two metallization levels on a semiconductor wafer.
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`The conductive region 10 (hereinafter also referred to as
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`interconnect 10) formed in the dielectric layer 11 is shown
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`in the Figure as a wiring interconnect. Wiring interconnects
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`are conductive regions formed within trenches and provide
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`the wiring (or lines) for a given metallization layer on a
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`semiconductor wafer. It is appreciated that another type of
`interconnect is a plug interconnect, which is a conductive
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`region formed within a via and providesthe interconnection
`between the different metallization levels. Aluminum has
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`been used extensively for both trenches and vias. Other
`metals, such as tungsten, have been used as well for vias.
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`A more recent practice is the use of copper to replace
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`aluminum. Since copper has higher resistance to electromi-
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`gration and lowerelectrical resistivity than aluminum,it is
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`a more preferred material for interconnect wiring than
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`aluminum. In addition, copper has lowerresistivity than
`tungsten or aluminum, making copper a desirable metal for
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`use in forming plugs. However, because of its diffusion
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`property in the dielectric material and incompatibility with
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`silicon materials, copper requires encapsulation to isolate it
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`from most adjacent materials.
`Thus, when copper
`is employed as an interconnect
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`material, some form of barrier or encapsulation layer is
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`required to prevent the copper from interacting with the
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`surrounding material. This is a requirement, whether the
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`adjacent material is fabricated from a silicon-based dielec-
`tric or a low-E dielectric material. As for aluminum,a liner
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`layer 12 of somesort is desirable as well, when the adjacent
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`material is formed from a low-€ dielectric. The liner layer
`12 functions as an adhesion promoterlayer or a combination
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`of barrier/adhesion promoter layer between the aluminum
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`and the low-€ dielectric material. Accordingly, whether the
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`conductive region 10 is comprised of either aluminum or
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`copper, some form of intervening liner layer 12 is needed to
`function as an adhesion promoterlayeror a barrier layer that
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`also functions as an adhesion promoter layer (hereinafter,it
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`is understood that a barrier layer also provides adhesion
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`promotion as well). Copper requires a barrier layer. Alumi-
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`num only requires an adhesion promoter layer, if the alu-
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`minum does not interact with the surrounding material. In
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`the event aluminum does interact with the surrounding
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`material, a barrier layer is required.
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`Page 9 of 13
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`

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`6,100,184
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`5
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`Accordingly, the example shown in FIG. 1 is described
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`having either copper or aluminum as the material compris-
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`ing the conductive region (or interconnect) 10. It is appre-
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`ciated that the interconnect 10 can be comprised of other
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`materials as well and is not
`limited to just copper and
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`aluminum. As shown,region 10 is part of a lower metalli-
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`zation layer (wiring interconnect), however,it is appreciated
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`that the region 10 can be a plug interconnect or a doped
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`region for the practice of the present invention. The dielec-
`tric layer 11 can be comprised of an oxide (such assilicon
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`dioxide (SiO.,)), nitride or a low-€
`dielectric.
`In the
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`example, it is presumedthat the dielectric material of layer
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`11 will be a low-€
`dielectric, since that is the preferred
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`material for ILDs in the practice of the present invention.
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`Furthermore,
`in the preferred embodiment,
`the low-€
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`dielectric selected is an organic low-€ dielectric material.
`Since encapsulation of copper is necessary to prevent or
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`inhibit copper diffusion into the surrounding dielectric layer
`11, a barrier layer (also referred to as encapsulation or
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`isolation layer) is used for the liner layer 12, when copperis
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`used as the material comprising conductive region 10. The
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`liner layer 12 in the example structure can be formed from
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`a variety of knownbarrier materials, including TiN, Ta, TaN,
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`W, WN,SiN and WSIN.Again,it is appreciated that these
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`materials also operate as an adhesion promoter. Generally,
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`TIN or TaN is preferred when the interconnect 10 is com-
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`prised of copper.
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`If the conductive region 10 is comprised of aluminum,the
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`liner layer 12 can be a barrier layer or just an adhesion
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`promoterlayer (not having barrier properties), depending on
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`the interaction of the aluminum to the surrounding material.
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`A variety of known materials, including TiN, TiSiN, Ta,
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`TaN, TaSiN, WN, SiO., SiN, Al,O3, SiC and SiON, for
`example, can be used as a barrier/adhesion promoter mate-
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`rial. Titantum can also be used strictly as an adhesion
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`promoter material. It is also appreciated that the liner layer
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`12 can be comprised of multiple layers. For example, a
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`barrier material formed above an adhesion promoterlayer.
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`Avariety of known techniques can be usedto fabricate the
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`structure shown in FIG. 1. One such technique is a single-
`damascenestructure described in the earlier-mentionedref-
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`erence entitled “Planar Copper-Polyimide Back End Of The
`Line Interconnections For ULSI Devices;” B. Lutheret al.;
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`1993 VMIC Conference; Jun. 8-9, 1993; pp. 15-21.
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`Furthermore, it is appreciated that the region underlying the
`interconnect 10 (although not shown) can be a conductive,
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`dielectric or semiconductive region, which can be the wafer
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`substrate itself. It is also appreciated that the example shown
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`is that of a trench region of a lower metallization layer.
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`Accordingly, FIG. 1 illustrates the starting structure upon
`which the various layers are formed to fabricate an inter-
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`connect structure of the present invention.
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`Referring to FIG. 2, a dielectric separation layer 13 is
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`deposited over the interconnect 10 and dielectric layer 11
`(the dielectric layer 11 is henceforth referred to as an ILD
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`layer 11 in order to differentiate the various dielectric layers
`being described). A variety of dielectric materials can be
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`used to form the dielectric separation layer 13 to separate the
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`structure of FIG. 1 from the subsequently deposited over-
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`lying low-€ material. If the conductive region 10 is com-
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`prised of copper, then region 10 will need to be encapsu-
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`lated. Accordingly, a barrier material, from the list of barrier
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`materials described previously in reference to the liner layer
`12, is used to form a barrier as layer 13. If the conductive
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`region 10 is comprised of aluminum, then layer 13 can be a
`barrier or an adhesion promoter layer, or both.
`In the
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`preferred embodiment,silicon nitride (SiN) is deposited by
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`Page 10 of 13
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`6
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`chemical-vapor deposition (CVD) to an approximate thick-
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`ness of 300-1000 angstroms when copperis used. When the
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`conductor is aluminum, SiN or SiO, is deposited by CVD to
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`an approximate thickness of 300-1000 angstroms. A pri-
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`mary purposeof the separation layer 13 is to cap the exposed
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`conductive region 10 for the subsequent ILD deposition.
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`Functionally, the separation layer 13 functions equivalently
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`to the liner layer 12 in isolating or separating the conductive
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`material from the adjacent ILD.
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`Subsequently, as shown in FIG. 3, a first low-dielectric
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`constant (low-€)
`dielectric layer 14 (hereinafter also
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`referred to as the ILD layer 14) is deposited over the
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`dielectric separation layer 13. The low-€
`dielectric ILD
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`layer 14 of the preferred embodiment is comprised of an
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`organic low-€ material. Examples of such organic low-E
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`dielectric material are polyimide, fluorinated polyimide,
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`parylene, poly-arylethers, fluorinated poly-arylethers and
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`other polymers. However, this is not an inclusive list and
`other low-€ dielectric materials can be used as well. The
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`low-E layer 14 is preferably deposited by CVD or a spin-on
`process to an approximate thickness of 5000-10,000 ang-
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`stroms.
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`Next, another dielectric layer, referenced as an etch-stop
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`layer, 15 is deposited over the low-E ILD layer 14. In the
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`example, SiO. is deposited by a CVD process to an approxi-
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`mate thickness of 300-1000 angstroms.As explained below,
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`it is important that the material selected for the etch-stop
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`layer 15 is different from that comprising the separation
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`layer 13.
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`Then, as shown in FIG. 4, photoresistive material 16 is
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`deposited, exposed and developed by the use of known
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`techniques to form an opening to define a subsequent via
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`hole opening. Thus, the photolithography technique exposes
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`the location where portions of the dielectric layer 15 is to be
`etched. Next, a plasma etch step is utilized to remove the
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`exposed portion of the dielectric layer 15 to form an opening
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`17. Accordingly, the pattern in the photoresist layer 16 is
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`transferred to the dielectric layer 15 for forming the opening
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`17. Later, the opening 17 will define a location where the via
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`hole opening is to be formed in the underlying low-€
`layer
`14.
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`Subsequently, an anisotropic photoresist strip etch using
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`O., plasma is used to remove the remaining photoresistive
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`material 16. As an example, a high-density plasma etch
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`utilizing low pressure, typically less than 5 mTorr can be
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`used for this step. The resulting struct