`i!0
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`US005635423A
`es
`5,635,423
`(11) Patent Number:
`United States Patent 1
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`Huangetal.
`[45] Date of Patent:
`Jun. 3, 1997
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`a
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`0 435 187,
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`0 463 972
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`[75]
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`[54] SIMPLIFIED DUAL DAMASCENE PROCESS
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`FOR MULTI-LEVEL METALLIZATION AND
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`INTERCONNECTION STRUCTURE
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`Inventors: Richard J. Huang; Angela Hui, both
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`of Milpitas; Robin Cheung, Cupertino;
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`Mark Chang, Los Altos; Ming-Ren
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`Lin, Cupertino,all of Calif.
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`[73] Assignee: Advanced Micro Devices, Inc.,
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`Sunnyvale, Calif.
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`[56]
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`7/1991
`European Pat. Off. .
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`1/1992 European Pat. Off. .
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`OTHER PUBLICATIONS
`
`
`Kikuta et al., “Al-Gr Reflow Sputtering For Submicron-
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`
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`
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`—Contact—Hole Filling”, Microelectronics Research Labora-
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`tories, NEC Corporation, IEEE VMIC Conference, Jun.
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`11-12, 1991, pp. 5.2.1-5.2.4.
` -
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`IBM Technical Disclosure Bulletin, vol. 30, No. 8, Jan 1988,
`New York, US, pp. 252-253, XP 000097503 Anonymous
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`“Methods of forming small contact holes”.
`
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`Proceedings of the 8th International IEEE VLSI Multilevel
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`
`Interconnection Conference, Santa Clara, CA, USA, Jun.
`[21] Appl. No.: 320,516
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`11-12, 1991, pp. 144-152, Kaanta etal., “Dual damascene:
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`a ULSI wiring technology”.
`[22] Filed:
`Oct. 11, 1994
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`Joshi, “A New Damascene Structure for Submicrometer
`PSU]
`Tints C1o osceeeeteentnrnerenetntnnnsnne HOIL 21/44
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`Interconnect Wiring,” IEEE Electron Letters, vol. 14, No.3,
`[52] WLS. Cle creesersnsnnnesnsne 437/195; 437/190, 437/203,
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`156/652.1; 156/653.1
`Mar. openhe,
`- A
`ULSI Witine
`Technol
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`[58] Field of Search 2escscverscseeemeenes 437/195, 190, Damascene:AULSInta et al., “Dual Wiring Technol-
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`437/182, 203; 156/DIG. 652.1, DIG. 653.1
`98)"Jom U-12, 1981, VMIC Conference, THEE, pp.
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`Kenny et al., “A Buried-Plate Trench Cell for a 64—Mb
`References Cited
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`DRAM,” 1992 Symposium on VLSI Technology Digest of
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`Technical Papers, [EEE, pp. 14 and 15.
`U.S. PATENT DOCUMENTS
`
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`
`
`
`
`Primary Examiner—Chatles L. Bowers, Jr.
`ccccorsesssrscsoeseerensenee 437/195
`3,844,831 10/1974 Cass et Al.
`
`
`
`
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`
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`“Assistant Examiner—Lynne A. Gurley
`3,961,414
`6/1976 Humphreys ..eessssssnsensnenne 437/195
`
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`
`
`
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`
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`4,472,240
`9/1984 Kameyama.
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`
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`ABSTRACT
`csesccsssssesssrsesesserse 437/195
`8/1985 Rhodes et al.
`4,536,951
`[57]
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`
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`4,764,484
`8/1988 MO secscrsoresressecseessseenseeserserensanee 437/195
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`
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`A semiconductor device containing an interconnection
`4,801,350
`1/1989 Mattox etal. .
`
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`structure having a reduced interwiring spacing is produced
`6/1990 MO ssccssorecsessesssseserentecsoveeseenvees 437/190
`4,933,303
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`4,948,755—8/1990 MO ssscssssscsenccssnrscesscssosessecosscees 437/195 by a modified dual damascene process. In one embodiment,
`
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`4,996,167
`2/1991 Chen .
`an openingfor a viais initially formed in a secondinsulative
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`5,055,423 10/1991 Smith et al. n.scssssessssensorsenee 437/195
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`layer abovea first insulative layer with an etch stop layer
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`5,093,279
`3/1992 Andreshak et al. .
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`therebetween. A larger opening for a trench is then formed
`5,262,354 11/1993 Cote etal. .
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`a 437/182
`in the second insulative layer while simultaneously extend-
`5,354,711 10/1994 Heitzmann etal.
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`5,470,788
`11/1995 Biery et all. csessssssssssesseessore 437/190
`ing the via opening through the etch stop layer and first
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`insulative layer. The trench and via are then simultaneously
`filled with conductive material.
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`:
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`
`FOREIGN PATENT DOCUMENTS
`6/1987 European Pat. Off..
`0224013
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`5/1991 European Pat. Off. .
`0425 787
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`13 Claims, 8 Drawing Sheets
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`Page 1 of 14
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`TSMC Exhibit 1006
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`TSMC Exhibit 1006
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`Page 1 of 14
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`US. Patent
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`Jun. 3, 1997
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`Sheet 1 of 8
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`5,635,423
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`FIG.
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`(a) PRIOR ART
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`PLIES
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`NIONASS
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`FIG. 1(b)
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`PRIOR ART
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`USS. Patent
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`Jun. 3, 1997
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`Sheet 2 of 8
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`FIG. 2)=RNNANANAAN *
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`PRIOR ARTVLLILY 21
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`RIE
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`rt
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`i
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`reo act=[J | [+
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`FIG. 2b
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`DETLafg*
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`FIG. 2(c)
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`PRIOR ART
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`FIG. 2(d)
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`PRIOR ART
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`ELIE
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`FIG. 2(e)
`CDULLLLLDI LAT
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`PRIOR ART NANG 22
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`LAPLIfehs21
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`US. Patent
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`Sheet 3 of 8
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`* UVAG 33
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`Pa wr WMO :
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`LLLIL
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`prideART WS:
`PRIOR ART
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`FIG. 4(b)
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`FIG. 4(c)
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`PRIOR ART
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`U.S. Patent
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`Sheet 4 of 8
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`FIG. 5(a)
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`| yRe
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`FIG. 5(c)
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`FIG. 5(b)
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`US. Patent
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`Jun. 3, 1997
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`Sheet 5 of 8
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`FIG. 6(a) WN SS6A
`IAPLMALL
`WDA 2
`CLLLk 6
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`FIG. 6(b)
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`FIG. 6(c)
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`U.S. Patent
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`Jun. 3, 1997
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`Sheet 6 of 8
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`FIG. 7(a)
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`FIG. 7(b)
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`U.S. Patent
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`Jun.3, 1997
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`Sheet 7 of 8
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`82
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`FIG. 8(a) Wy:y,
`hiLiep
`<>
`83
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`AA}AQARNN
`FIG. 8(b)
`82
`81
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`CM PLELfellsR
`L784
`93
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`IQANSNASS— <2
`FIG. 8{c)
`PALALEEL BI
`“3
`N
`84
`FIG. 8@ [SSOYS::
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`RRNA
`PLDALP
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`FIG. 8(f)
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`FIG. 8(e)
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`DS
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`wAF
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`FIG. 8(g)
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`CLPLhotfotfos
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`Sheet 8 of 8
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`1
`SIMPLIFIED DUAL DAMASCENE PROCESS
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`FOR MULTI-LEVEL METALLIZATION AND
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`INTERCONNECTION STRUCTURE
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`TECHNICAL FIELD
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`The present invention relates to a semiconductor device
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`containing an interconnection structure comprising conduc-
`tive wiring and conductive vias on a substrate, and to a dual
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`damasceneprocess for forming an interconnectionstructure.
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`The invention has particular application in submicron circuit
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`manufacturing.
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`BACKGROUND ART
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`The escalating requirements for density and performance
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`associated with ultra large scale integration semiconductor
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`wiring require responsive changes in interconnection tech-
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`nology which is considered one of the most demanding
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`aspects of ultra large scale integration technology. High
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`density demandsfor ultra large scale integration semicon-
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`ductor wiring require planarized layers with minimal spac-
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`ing between conductive wiring lines.
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`A traditional method for forming interconnection struc-
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`step as the primary metal-patterning technique. One such
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`traditional techniqueis illustrated in part in FIGS. 1(a@)-1(8),
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`wherein insulative layer 12, such as an oxide layer, is formed
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`on semiconductor substrate 11, such as monocrystalline
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`silicon, with conductive contacts/vias 13 formed in insula-
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`tive layer 12. A metal layer 14, such as aluminum or
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`tungsten, is deposited on insulating layer 12 and a photore-
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`sist pattern 15 formed on metal layer 14 correspondingto the
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`wiring pattern. After etching, a dielectric layer 16 is applied
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`to the resulting wiring pattern 14. The interconnection
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`structure comprises conductive contacts/vias 13 and con-
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`ductive wiring 14.
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`In employing such a traditional method, it is extremely
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`difficult to form a planarized layer after filling in the spaces
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`between the conductive wiring 14, as by chemical-
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`mechanical polishing (CMP) planarization techniques. In
`addition, such a traditional technique often results in the
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`40
`formation of voids 17 as seen in FIG. 1(b) in the spacing
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`between interconnection wirings 14. Additional difficulties .
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`include trapping of impurities or volatile materials in the
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`interwiring spaces which may damagethe device. Moreover,
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`the traditional etch back approach leads to defects which,
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`even if cosmetic, impose a competitive disadvantage in the
`commercial environment.
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`Additional disadvantagesoftraditional etch back methods
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`include poor metal step coverage, residual metal shorts
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`leading to inconsistent manufacturability, low yields, uncer-
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`tain reliability and poor ultra large scale integration extend-
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`ability. Significantly, traditional etch back methods were
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`unable to yield sufficiently planarized layers having inter-
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`wiring spaces of less than 3.5 microns.
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`A prior attempt to address the disadvantages attendant
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`upontraditional etch back methods for providing intercon-
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`nection structures comprises a single damascene wiring
`technique. Damascene, an art which has been employed for
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`centuries for the fabrication of jewelry, has recently been
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`adapted for application in the semiconductor industry.
`Damascene basically involves the formation of a trench
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`which is filled in with a metal. Thus, damascenediffers from
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`the traditional etch back methods of providing an intercon-
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`nectionstructure by providing a trench whichisfilled in with
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`metal followed by planarization; whereas, the traditional
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`etch back technique involves building up a metal wiring
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`layer and filling in the interwiring spaces with a dielectric
`material.
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`2
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`A prior art single damascene technique is illustrated in
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`FIGS. 2(a)-2(e) wherein insulative layer 22 is deposited on
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`semiconductor substrate 21. A photoresist pattern 23 is
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`formed on insulative layer 22 and openings formed in
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`insulative layer 22 by reactive ion etching (RIE).
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`Subsequently, a metal 24, such as tungsten, is deposited
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`within the openings and on insulative layer 22, as by
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`chemical vapor deposition as shown in FIG. 2(d).
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`Alternatively, hot aluminum 25 can be formed in the open-
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`ings and on insulative layer 22 as shown in FIG. 2(e). Thus,
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`the prior art single damascene techniqueresults in a single
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`conductive opening, e.g., a conductive via. Upon planariza-
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`tion and repetition of the foregoing steps, as by depositing
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`a second insulative layer 33, metal 35 and planarization, an
`interconnection structure is obtained as shownin FIG.3. The
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`first layer comprises conductive vias 34 through first insu-
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`lative layer 32 on semiconductor substrate 31. The conduc-
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`tive wiring 35 in second insulative layer 33 electrically
`connected to conductive vias 34 at 36.
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`The single damascene technique offers the advantage of
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`improved planarization; however, it is time consuming in
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`requiring numerous processing steps. Undesirably, an inter-
`face exists between the conductive via and conductive
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`wiring. Moreover, adequate planarized layers containing an
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`interwiring spacing less than 0.35 @ cannot be obtained.
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`An improvementin the single damascene process, called
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`dual damascene, has recently been developed by IBM.See,
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`for example, Joshi, “A New Damascene Structure for Sub-
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`micrometer Interconnect Wiring,” IEEE Electron Letters,
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`vol. 14, No. 3, March 1993, pages 129-132; and Kaanta et
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`al., “Dual Damascene: A ULSI Wiring Technology,” Jun.
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`11-12, 1991, VMIC Conference, IEEE, pages 144-152. The
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`use of a damascene technique wherein the dielectric is
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`planarized by chemical-mechanical polish is discussed in
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`Kenny et al., “A Buried-Plate Trench Cell for a 64-Mb
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`DRAM,” 1992 Symposium on VLSI Technology Digest of
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`Technical Papers, IEEE, pages 14 and 15.
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`US. Pat. No. 5,262,354 discloses a three-step method of
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`forming electrically conductive vias and lines involving a
`damascene technique to create lines on a substrate. In
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`addition, this patent discloses the advantages of chemical-
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`mechanical polishing with an aluminum slurry in dilute
`nitric acid to planarize a dielectric surface. U.S. Pat. No.
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`5,093,279 discloses a laser ablation damascene process for
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`planarizing metal/polymer structures in the fabrication of
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`both interlevel via metallization and circuitization layers in
`integrated circuit interconnects.
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`The dual damascene technique involves the simultaneous
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`formation of a conductive via and conductive wiring,
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`thereby requiring fewer manipulative steps than the single
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`damascene technique and eliminating the interface between
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`the conductive via and conductive wiring which is neces-
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`sarily formed by the single damascene technique. The dual
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`damascene technique is illustrated in FIGS. 4(a)-4(c),
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`wherein insulative layer 42 is deposited on semiconductor
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`substrate 41 and then patterned by conventional photolitho-
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`graphic techniques to form a first opening 43 which is about
`the size of the ultimate via. Subsequently, as shown in FIG.
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`4(b), photoresist layer 44 is deposited and patterned to form
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`a second opening 45 about the size of the ultimate trench.
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`Anisotropic reactive ion etching (RIE) is then conducted
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`which,in effect, duplicates the first and second openings in
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`insulative layer 42,
`thereby forming a via and trench.
`Subsequently, a conductive material such as aluminum,
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`tungsten, copper or alloys thereof, with or without an
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`adhesion/barrier layer, e.g., titanium nitride or a titanium-
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`tungsten alloy, under the conductive material, is provided to
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`Page 10 of 14
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`5,635,423
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`form conductive via 46 and conductive wiring 47 as shown
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`in FIG. 4(c). This process is repeated to form a plurality of
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`layers such as second conductive via 48 and second con-
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`ductive interconnect wiring 49 also shown in FIG. 4(c). The
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`resulting structure is characterized by an interface between
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`the separately formed conductive patterns, i.e., between the
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`first conductive wiring and second conductive via; however,
`no interface is formed between the conductive via and
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`conductive wiring of each separately formed pattern.
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`Although the dual damascene technique offers advantages
`vis-a-vis the traditional etch back technique and the single
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`damascenetechnique, we have foundthatit also suffers from
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`several disadvantages. We have found thatit is extremely
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`difficult
`to control the profile of the vias and trenches
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`employing the dual damascene technique and, hence, diffi-
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`cult to control the depth and resistivity of the conductive
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`wiring. Moreover, satisfactory planarized layers having an
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`interwiting spacing of less than 0.35 micron cannot be
`attained with the above-described dual damascene tech-
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`nique.
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`DISCLOSURE OF THE INVENTION
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`An object of the present invention is a highly integrated
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`semiconductor device containing an interconnection struc-
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`ture of planarized layers having minimal interwiring spac-
`ing.
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`Another object is an improved dual damascene method
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`for forming an interconnection structure having improved
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`control of the profile of conductive vias and conductive
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`wiring.
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`A further object of the invention is an improved dual
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`damascene process having a reduced number of manipula-
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`tive steps.
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`Additional objects, advantages and other features of the
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`invention will be set forth in part in the description which
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`follows and in part will become apparent to those having
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`ordinary skill in the art upon examination of the following
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`or maybe learned from practice of the invention. The objects
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`and advantages of the invention may be realized and
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`obtainedas particularly pointed out in the appended claims.
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`According to the present invention, the foregoing and
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`other objects are achieved in part by a highly integrated
`semiconductor device having an interconnection structure
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`comprising a plurality of planarized layers with conductive
`wiring, wherein the distance between conductive wires or
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`interwiring spacing is less than about 0.35 p.
`A further aspect of the invention is a method of forming
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`a conductive wiring and conductive via on a substrate, which
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`method comprises forming a first insulative layer on the
`substrate and an etch stop layeron the first insulative layer.
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`A second insulative layer is formed on the etch stop layer
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`and a first opening of about the size of the ultimate via is
`formedin the second insulative layer. Using a mask, a trench
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`is formed in the second insulative layer while simulta-
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`neously forming a via in the etch stop and in the first
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`insulative layer. Subsequently, a conductive material
`is
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`simultaneously deposited in and completely fills the via and
`trench, with the conductive via providing electrical connec-
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`tion between the conductive wiring and substrate:
`Another aspectof the invention is a method of forming a
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`conductive wiring and a conductive via on a substrate, which
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`method comprises forming a first insulative layer on a
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`substrate and forming an etch stop layer on the first insula-
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`tive layer. A second insulative layer is formed in the etch
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`stop layer and a trench formedin the secondinsulative layer
`at a first location where the wiring is desired. A first opening
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`Page 11 of 14
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`4
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`is then formedin the etch stop layer andin thefirst insulative
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`layer at a second location where the via is desired, with the
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`first opening penetrating through the etch stop layer and the
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`first insulative layer. Subsequently, a conductive material is
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`simultaneously deposited in the first opening and in the
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`trench completely filling the first opening andthetrench, the
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`trench forming the conductive wiring. the first opening
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`forming the conductive via, the conductive via providing
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`electrical connection between the conductive wiring and the
`substrate.
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`Another aspect of the invention is a method of forming a
`conductive wiring and conductive via on a substrate, which
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`method comprises forming an insulating layer on the sub-
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`strate and forming a trench in the insulative layer at a first
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`location where the wiring is desired. An etch stop layer is
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`then formed in the insulative layer and a first opening
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`formed inside the trench in the etch stop layer at a second
`location where the via is desired, but not in the insulative
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`layer. A second opening of about the sizeofthe first opening
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`is formed underthe first opening in the insulative layer at the
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`second location where the via is desired using the etch stop
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`layer as a hard mask. The etch stop layer is then removed
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`and a conductive material is simultaneously deposited in the
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`openings and in the trench so that the conductive material
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`completely fills the openings and the trench, the trench
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`forming the conductive wiring, the openings forming the
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`conductive via, and the conductive via providing electrical
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`connection between the conductive wiring and the substrate.
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`Stili another object of the invention is a method of
`forming a conductive wiring and a conductive via on a
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`substrate, which method comprises forminga first insulative
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`layer on the substrate and forming an etch stop layer on the
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`first insulative layer. A first opening is formed in the etch
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`stop layer at a first location where the via is desired, thefirst
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`opening penetrating through the etch stop layer. A second
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`insulative layer is formed on the etch stop layer.
`Subsequently, a trench is formed in the second insulative
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`layer at a second location where the wiring is desired and,
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`simultaneously, a second opening is formed through thefirst
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`opening and the first insulative layer. The trench and the
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`second opening penetrates through the second insulative
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`layer and thefirst insulative layer, respectively. A conductive
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`material is then simultaneously deposited in the second
`opening and in the trench so that the conductive material
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`completely fills the second opening and the trench, the
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`trench forming the conductive wiring. the second opening
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`forming the conductive via and the conductive via providing
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`electrical connection between the conductive wiring and the
`substrate.
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`BRIEF DESCRIPTION OF DRAWINGS
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`FIGS. 1(a) and 1(6) are sequential cross-sectional views
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`of a prior art semiconductor substrate showing formation of
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`a conductive via and conductive wiring.
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`FIGS. 2(a) through 2(e) depict sequential cross-sectional
`viewsof a prior art structure formed by a single damascene
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`technique.
`FIG. 3 depicts a prior art semiconductor substrate pro-
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`duced by repetition of a single damascene technique.
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`FIGS. 4(a) through 4(c) depict sequential cross-sectional
`views of a prior art structure formed by a dual damascene
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`technique.
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`FIGS. 5(@) through 5(c) are sequential cross-sectional
`views of a semiconductor device having a conductive via
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`and conductive wiring formed in accordance with one
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`embodimentof the present invention.
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`Page 11 of 14
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`FIGS. 6(a) through 6(c) are sequential cross-sectional
`The various embodiments of the present invention involve
`a conventional semiconductor substrate, such as monocrys-
`views of a semiconductor device having a conductive via
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`talline silicon, and conventional insulative layers, such as
`and conductive wiring formed in accordance with another
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`oxide layers, e.g., layers of a silicon oxide, formed in a
`aspect of the present invention.
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`conventional manner, as by thermal oxidation of a deposited
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`FIGS. 7(a) and 7(6) are sequential cross-sectional views
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`silicon layer, plasma enhanced CVD,
`thermal enhanced
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`of a semiconductor device having a conductive via and
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`CVD and spin on techniques.
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`conductive wiring formed in accordance with another
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`A first embodiment of the present invention is sequen-
`embodiment of the present invention.
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`tially schematically depicted in FIGS. 5(a@) through 5(c),
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`FIGS. 8(a) through 8(g) are sequential cross-sectional
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`whereinafirst insulative layer 52 is deposited on a semi-
`views of a semiconductor device having a conductive via
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`conductor substrate 51, and an etch stop layer 53 deposited
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`and conductive wiring formed in accordance with another
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`on the first insulative layer 52. The etch stop layer can be any
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`embodiment of the present invention.
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`suitable conventional stop material selected consistent with
`FIG.9 is a cross-sectional view of a semiconductor device
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`the insulative layers. For example,if the insulative layers are
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`produced in accordance with the present invention.
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`made ofsilicon oxide, the etch stop layer can be made of
`DESCRIPTION OF THE INVENTION
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`silicon nitride, silicon oxynitride or undoped polysilicon. A
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`secondinsulative layer 54 is deposited on the etch stop layer
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`The present invention is directed to a semiconductor
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`53 and a first photoresist mask 55 formed on the second
`device comprising a substrate and a plurality of planarized
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`insulative layer. A first opening is formed in second insula-
`layers vertically formed thereon, and an interconnection
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`tive layer 54 but not penetrating etch stop layer 53 byafirst
`structure comprising conductive vias and conductive wiring,
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`etching process as shown in FIG. 5(a), preferably anisotro-
`wherein the profiles of the conductive vias and conductive
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`pic etching, most preferably reactive ion etching. The size of
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`wiring are controlled with great accuracy to achieve minimal
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`the first opening is about the size of the ultimate via. As
`interwiring spacing as required by high density design rule.
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`shownin FIG.5(b), after removingthefirst photoresist mask
`Preferably, the interwiring spacing is less than about 0.35 pL.
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`55, a second photoresist mask 56 is formed on second
`It is particularly preferred to provide an interwiring spacing
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`insulative layer 54, a trench is formed in second insulative
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`of from about 0.05 p to about 0.18 p, most preferably from
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`layer 54 to include the first opening by a second etching
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`about 0.05 p1 to about 0.10 p. A semiconductor device having
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`process while extending the first opening as shown in
`such improved conductive via and conductive wiring pro-
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`phantom lines. As shown in FIG. 5(c), the trench is formed
`files and minimal interwiring spacing is achieved by a
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`in second insulative layer 54 while simultaneously extend-
`process comprising a sequence of manipulative steps which
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`ing the first opening through etch stop layer 53 and first
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`include a dual damascene technique wherein vias and
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`insulative layer 52. The dual damascene metallization tech-
`trenches are simultaneously filled with a conductive mate-
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`tial.
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`nique is then employed to simultaneously fill the via and
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`trench with conductive material to form an interconnection
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`The various embodiments of the present invention com-
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`wherein the conductive via provides electrical connection
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`prises a dual damascene technique wherein the vias and
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`between the conductive wiring and substrate.
`trenches are simultaneously filled with conductive material
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`In the first embodiment, the first etching process has a
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`conventionally employed in fabricating interconnection
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`greater selectivity with respectto the etch stop layer than the
`structures, such as aluminum, tungsten copper and alloys,
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`second etching process. As known in the art, by a greater
`with or without an adhesion/barrier layer. The conductive
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`selectivity with respect to the etch stop layer is meant that
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`material is simultaneously deposited in the vias and trenches
`the insulative layer is etched at a greater rate than the etch
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`by techniques which are known in the art. For example,
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`stop layer. After simultaneously filling the via and trench
`metallization techniques such as various types of chemical
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`with a conductive material, the second insulative layer 54 is
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`vapor deposition (CVD) processes, including low pressure
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`planarized, preferably by chemical-mechanical polishing.
`chemical vapor deposition (LPCVD), and plasma enhanced.
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`This first embodiment provides improved control over the
`chemical vapor deposition (PECVD) may be employed.
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`profiles of the via and trench by providing better control of
`Normally, when high melting point metals such as tungsten
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`their depth.
`are deposited, CVD techniques are used. Low melting point
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`metals, such as aluminum and aluminum-based alloys
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`A second embodiment of the present invention is illus-
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`including aluminum-copper alloys, may be deposited by
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`trated in FIGS. 6(a) through 6(c) wherein first insulative
`melting or sputtering. Polysilicon can also be employed as
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`layer 62 is deposited on semiconductor substrate 61, and an
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`a conductive material in the interconnection pattern.
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`etch stop layer 63, preferably Si,N,, deposited on first
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`insulative layer 62. A second insulative layer 64 is deposited
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`Thevarious embodiments of the present invention involve
`on etch stop layer 63 and a trench formed in second
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`the use of knownpianarization techniques, such as conven-
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`insulative layer 64 at a first location where the wiring is
`tional chemical-mechanical planarization techniques. See,
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`desired. As shown in FIGS. 6(b) (in phantom) and 6(c), a
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`for example, U.S. Pat. Nos. 5,262,354 and 4,944,836, which
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`first opening is formed in etch stop layer 63 and in first
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`are incorporated by reference herein in their entirety.
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