`
`TSMC Exhibit 1021
`
`REDACTED
`
`RE
`DA
`
`Page 1 of 18
`
`TSMC Exhibit 1021
`
`
`
`AS/WE f’roce€<{’_‘_’j-5Q /1”/"‘l”*"—‘°°(i
`" mo\mJ.(q¢TJ,/if Co~-{swore oi/old, puoutséa/»‘
`Advanced Semiconductor
`Manufacturing conlerence and workshop
`
`5‘9m’(°"‘/“f-74°"
`
`IEEE/SEMI®
`
`1998
`
`IEEE/ SEMI
`
`Advanced
`
`Semiconductor
`
`Manufacturing
`Conference
`
`And Workshop
`
`
`
`The-me— Semiconductor Manufacturing: Meeting the Challenges of
`the Global Marketplace
`
`ASMC 98 PROCEEDINGS
`
`The IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop is an
`annual forum that provides a venue for the presentation of methodologies, approaches and
`techniques required to achieve world class semiconductor manufacturing.
`A key role this
`conference plays is in promoting interaction among semiconductor professionals at all levels. The
`goal and objective of the conference are to assist in making the participating companies more
`knowledgeable of semiconductor production methods, encourage open communication between
`participants, and develop the strategic relationship between users and suppliers needed to achieve
`manufacturing excellence and improve global competitiveness.
`
`September 23 -— 25, 1998
`Boston, Massachusetts, USA
`
`Page 2 of 18
`
`Page 2 of 18
`
`
`
`1993 PROCEEDINGS
`IEEE/SEMI ADVANCED SEMICONDUCTOR
`MANUFACTURING CONFERENCE AND
`WORKSHOP (ASMC) Egg‘? 8 7/
`
`PERMISSION TO REPRINT OR COPY:
`
`':l:Q5o.
`l 7 C7 8
`
`Abstracting is permitted with credit to the source. Libraries are permitted to photocopy
`beyond the limit of U.S. copyright law for private use of patrons those articles in this volume that
`carry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid
`through the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 09123 USA.
`Instructors are permitted to photocopy isolated articles for non-commercial classroom use without
`fee. For other copying, reprint or re-publication permission, write to IEEE Copyright Manager,
`IEEE Service Center, 445 Hoes Lane, Piscataway, NJ 08855 USA; or SEMI, 805 East Middlefield
`Road, Mountain View, CA 94043 USA. All rights reserved.
`
`Copyright © 1998 by Institute of Electrical & Electronics Engineering, Inc. (IEEE) and
`Semiconductor Equipment and Materials International, Inc. (SEMI)
`
`PRINTED AND BOUND IN THE UNITED STATES OF AMERICA
`
`Additional copies of these Proceedings may be purchased from:
`
`SEMI
`
`805 East Middlefield Road
`
`Mountain View, CA 94043 USA
`Phone:
`(650) 940-6971
`http=//www.semi.org
`
`IEEE Service Center
`
`445 Hoes Lane
`
`Piscataway, NJ 08855-0060 USA
`Phone:
`(732) 981-0060
`In the US 1-800-678-IEEE
`httgpz//www.ieee.org
`
`Refer to the IEEE Catalog Number, printed below:
`
`IEEE Catalog Number;
`
`98CH35163
`
`ISBN Number:
`
`ISSN:
`
`0-7803-4380-8
`0-7803-4381-6
`
`0-7803-4382-4
`
`1078-8743
`
`Softbound Edition
`Casebound Edition
`
`Microfiche Edition
`
`L3Y°_Ul’a Composition and compilation by
`Sermconductor Equipment and Materials International (SEMI)
`
`Page 3 of 18
`
`Page 3 of 18
`
`
`
`REDA
`CTED
`
`REDAC
`TED
`
`REDAC
`TED
`
`REDACTED
`
`Page 4 of 18
`
`
`
`RED
`ACT
`ED
`
`RED
`ACT
`ED
`
`RED
`ACT
`ED
`
`Page 5 of 18
`
`
`
`Keynote Address: Foundry Industry Update, Don Brooks, UMC
`
`International Session
`
`Yield Management for Development and Manufacture of Integrated Circuits
`Hiroshi Koyama and Masayuki lnokuchi, JEOL Ltd.
`
`Statistical Methods for Measurement Reduction in Semiconductor Manufacturing
`Richard Babikian, Intel Ireland Limited; Curt Engelhard, Intel Corp.
`
`America, Japan and Europe - Which Areas Have the Edge in Customer Satisfaction and Why
`Christine D. Burgeson, VLSI Research Inc.
`
`Contamination Free Manufacturing
`
`Effects of Process Parameters on Particle Formation in Sill,/N10 PECVD and WP, CVD Processes
`Z. Wu, S. Nijhawan, S. A. Campbell, N. Rao and P.H. MeMuny, University ofMinnesota
`
`Overcoming the Barriers to Cleaning with Bubble-Free Ozonated De-Ionized Water
`Timothy Bush, Steven Hardwick and Michael Wikol, W.L. Gore and Associates. Inc.
`
`ln-Situ Particle Monitoring in a Vertical Poly Furnace
`Peter Glass and Joe Kudlacik, IBM Microelectronics Division; Ray Burghard, Pacific Scientific Instruments Group
`
`Advanced Aqueous Wafer Cleaning in Power Semiconductor Device Manufacturing
`RS. Ridley, Sr., T. Grebs, J. Trost, R. Webb, M. Schuler, R.F. Longenberger, T. Fenstemacher and M. Caravaggio, Harris Semiconductor
`
`Residual Gasses Investigation for Elimnating Contamination In LPCVD Si,N4 Process
`N. Zhang, G. Magloczki, S. Aumick. G. Chiusano. S. Beckett, G. Nicholls and L. Stearns, MiCRUS
`
`Advantages to Point of Use Filtration of Photoresists in Reducing Contamination on the Wafer Surface
`Dennis Capitanio, Ph.D., Pall Corp.
`
`Advanced Metrology
`
`Matching Automated CD SEMs in Multiple Manufacturing Environments
`John Allgair and Dustin Ruehle, Motorola, Inc.; John Miller and Richard Elliott, KLA-Tencor Corp.
`
`Sidewall Angle Measurements Using CD SEM
`Bo Su, Tony Pan, Ping Li, Jeff Chinn, Applied Materials Inc. ; Xuelong Shi and Mircea Dusa, National Semiconductor Corp.
`
`Uses of Corona Oxide Silicon (COS) Measurements for Diffusion Process Monitoring and Troublshooting
`Richard G. Cosway, Kelvin B. Catmull, Janie Shray, Robert Naujokaitis, Meagan Peters and Don Grant, Motorola, Inc.;
`Gregory Homer and Brian Letherer, Keithley Instruments Inc.
`
`Effective Defect Detection and Classification Methodology Based on Integrated Laser Scanning Inspection and
`Automatic Defect Classification
`Yong-Hui Fan, Ph.D. and Yoel Moalem, KIA-Tencor Corp.
`
`The Quantitation of Surface Modifications in 200 and 300 mm Wafer Processing with an Automated Contact Angle System
`Ronald Carpio, SEMA TECH; David Hudson, AST Products, Inc.
`
`Correlation of Ellipsonometric Modeling Results To Observed Grain Structure for OPO Film Stacks
`Tod E. Robinson, KLA-Tencor Carp.
`
`Cost Reduction
`
`Beyond Cost-of-Ownership: A Casual Methodology for Costing Wafer Processing
`Stephanie Miraglia, Peter Miller, Thomas Richardson, Gregory Blunt and Cathy Blouin. IBM Microelectronics Division
`
`A Study in the Continuous Improvement Process: Implementation of an Optimized Scrubber to Replace TEOS Backside
`Etch Post SOG Etchback
`W. Au, D. Parks and P. Esquivel, VLSI Technology, Inc.
`
`Simulation of Test Wafer Consumption in a Semiconductor Facility
`Bryce Foster, Doron Meyersdorf, José Padillo and Raft Brenner, TEFEN Ltd.
`
`T Not available at time of printing
`
`208
`
`212
`
`216
`
`221
`
`226
`
`230
`
`235
`
`243
`
`247
`
`252
`
`259
`
`262
`
`266
`
`272
`
`278
`
`289
`
`294
`
`298
`
`IEEEISEMI Advanced Semiconductor Manufacturing Conference & Workshop 98
`
`Boston, MA
`
`Page 6 of 18
`
`RED
`ACT
`ED
`
`REDA
`CTED
`
`Page 6 of 18
`
`
`
`Improvement of Silicon Wafer Minority Carrier Lifetime Through the Implementation of a Pre-Thermal Donor Anneal
`_
`Cleaning Process
`_
`_
`_
`_
`Larry Martines, Charley Wang and Tom Hardenburger, UniSil Corporation; Nancie Barker and Brian Sohmers, Siliconix Corporation
`
`Design for Manufacturability: A Key to Semiconductor Manufacturing Excellence
`R. Wilcox, T. Forhan, G. Starkey and D. Turner, IBM Microelectronics Division
`
`Advanced Processing/Photo & Etch
`
`.
`Highly Selective Oxide to Nitride Etch Processes on BPSG/Nitride/Oxide Structures in a MERIE Etcher
`W. Graf and G. Skinner, SIEMENS, D. Basso, J.M. Martin and E. Sabouret, IBM France; F. Gautier, Applied Materials
`
`Overview of Plasma Induced Damage After Dry Etch Processing
`Yuri Karzhavin and Wei Wu, Motorola. Inc.
`
`Wet Chemical Cleaning for Damaaged Layer Removal Inside the Deep Sub-Micron Contact Hole
`Mitsuo Miyamoto, Morita Chemical Industries Co., Ltd.; Hideto Gotoh, Texas Instruments, Japan
`
`Effects of Photoresist Foreshortening on an Advanced Ti/AICu/I‘i Metallurgy and W Interconnect Technology (Abstract)
`C. Whiteside, M. Rutten, H. Trombley, H. Landis and M. Boltz, IBM Microelectronics Division
`
`I-‘C2: OIT-Axis Focus Control For Critical Level I-Line Photolithography
`Christopher H. Putnam, Jacek K. Tyminski, Sean J. McNamara, Nikon Precision Inc.
`
`Keynote Address: Sub-0.25 micron Interconnection Scaling: Damascene Copper versus Subtraetive Aluminum
`Anthony K. Stamper, Sr. T.L. McDevitt and S. L. Luce, IBM Mi‘croelectronicsDivision
`
`Advanced Processing/A New Era of Interconnect Technology
`
`Copper Interconnect - Technology New Paradigms for BEOL Manufacturing
`Kenneth Rose and Ramon Mangaser, Rensselaer Polytechnic Institute
`
`Development of a Production Worthy Copper CMP Process
`K. Wijekoon, S. Mishra, S. Tsai, K. Puntambekar, M. Chandrachood, F. Redeker, R. Tolles, B. Sun, L. Chen, T. Pan, P. Li, S. Nanjangud,
`G.Amico, Applied Materials, Ine.; J. Hawkins, '1‘. Myers, R. Kistler, V. Brusic, S. Wang, 1. Cherian, L. Knowles, C. Schmidt,
`C. Baker, Cabot Corporation
`
`Cu CMP with Orbital Technology. Summary of the Experience
`Y. Gotkis, D. Schey. S. Alamgir, J. Yang, K. Holland, Integrated Process Equipment Corporation (IPEC)
`
`A Study of Post-Chemical-Mechanical Polish Cleaning Strategies
`C. Huynh, M. Rutten, R. Cheek and H. Linde. IBM Microelectronics Division
`
`Process Control and Monitoring with Laser Interferometry Based Endpoint Detection in Chemical Mechanical Planarization
`
`Factory Automation — WIP Management
`
`A Layer Based Layout Approach for Semiconductor Fabrication Facilities
`Chao-Fan Chang and Shao~Kung Chang, Industrial Technology Research Institute
`
`Quantifying Impact of WIP Delivery on Operator Schedule in Semiconductor Manufacturing Line
`Allen L. Findley, IBM Microelectronics Division
`
`Better Dispatch Application — A Success Story
`Anke Giegandt and Gary Nicholson, SIEMENS Microelectronics
`
`Development and Implementation of an Automated Wafer Transport System
`Joe Sikich, Hewlett Packard
`
`A Focus on Cycle Time vs. Tool Utilization “Paradox” with Material Handling Methodology
`George W. Hom and William A. Podgurski, Middlesex General Industries, Inc.
`
`303
`
`303
`
`314
`
`320
`
`327
`
`332
`
`333
`
`337
`
`347
`
`354
`
`364
`
`372
`
`377
`
`335
`
`391
`
`396
`
`400
`
`405
`
`IEEE/SEMI Advanced Semiconductor Manufacturing Conference & Workshop 98
`
`Boston. MA
`
`Page 7 of 18
`
`RE
`DA
`CT
`ED
`
`RE
`DA
`
`RE
`DA
`
`Page 7 of 18
`
`
`
`Advanced Processing — Isolation and Dielectric Issue at 0.18pm
`
`A Manufacturable Shallow Trench Isolation Process for 0.18pm and Beyond-Optimization, Stress Reduction
`and Electrical Performance
`F. Nouri, O. Laparra. H. Sur, G.C. Tai, D. Pramanik and M. Manley, VLSI Technology, Inc.
`
`Performance and Productivity Improvements in an Advanced Dielectric Etch Reactor for sub 0.3um Applications
`M. Srinivasan, R. Caple. G. Hills, G. Mueller, T. Nguyen, and E. Wagganer, Lam Research Corp.
`
`A Study of Boron Doping Profile Control for a Low Vt Device Used in the Advanced Low Power, High Speed Mixed Signal IC
`Alec Chen. Kyle Flessner and Farris Malone, Peyman Sana, Robert Dixon, Peter Ying and Lou Hutter, Texas Instruments, Inc.
`
`Silicon Nanoelectronics: 100nm Barriers and Potential Solutions
`Vijay Parihar, R. Singh, K.F. Poole, Clemson University
`
`On the Integration of Ta,0, as a Gate Dielectric in sub-0.18pm, CMOS Processes
`T. Devoivre and C. Papadw, ST Microelectronics; M. Setton, LAM Research; N. Sandler, Formerly with LAM Research;
`L. Vallier, CNET Grenoble; l. Bouras, Integrated System Development
`
`Factory Modeling/Simulation
`
`Batch Size Optimization of a Furnace and Pre—Clean Area By Using Dynamic Simulations
`H..l.A. Rulkens, E.J.J. van Campen and J. van Herk, Philips Semiconductor,‘ .l.E. Rooda, Eindhoven University of Technology
`
`Simulation Analysis of 300mm lntrabay Automation Vehicle Capacity Alternatives
`Gerald T. Mackulak, Ph.D., Arizona State University; Frederick P. Lawrence and John Rayter, PR] Automation, Inc.
`
`Management of Multiple-Pass Constraints
`J. Bonal, A. Sadai, C. Ortega, S. Aparicio, M. Fernandez, R. Oliva, L. Rodriguez, M. Rosendo, A. Sanchez,
`E. Paule and D. Ojeda, Lucent Technologies
`
`MOSAIC I Product Transfer Using Virtual Flow Concept
`Ping Wang, Steve Spivey, Edward Warda, Mark Bowser, Bridgette Cosentino, Ed Zabasajja, Piyush Shah, Salma imam,
`John Keller and Joe Fulton, Motorola, Inc.
`
`Dynamic Dispatch and Graphical Monitoring System
`Neal Pierce and Tanju Yurtscvcr, Motorola, Inc.
`
`BIOGRAPHIES OF SPEAKERS
`
`SEMI Publications, Standards. Videos, Network
`
`413
`
`419
`
`423
`
`427
`
`434
`
`439
`
`445
`
`451
`
`455
`
`464
`
`469
`
`IEEE/SEMI Advanced Semiconductor Manufacturing Conference & Workshop 98
`
`Boston, MA
`
`Page 8 of 18
`
`Page 8 of 18
`
`
`
`Development of a Production Worthy Copper CMP Process
`.
`Kapila Wijekoon“, Sourabh Mishra”, Stan Tsaia, Kurnaar Puntambelgar“, Madhavi
`Chandrachood“, Fritz Redeker°, Robert Tolles“, Bingxi Sun , Liang Chen , Tony Pan , Pmg
`Li°, Savitha Nanjangud“, Gregory Amico”
`Applied Materials, 3050 Bowers Avenue, Santa Clara, CA 95054
`and
`
`Joe Hawkins, Theodore Myers, Rod Kistler, Vlasta Brusic, Shumin Wang, Isaac Cherian, Lisa
`Knowles, Colin Schmidt and Chris Baker
`Cabot Corporation, MMD Division, 500 Commons Drive, Aurora, IL 60504
`
`
`
`‘ CMP Division;
`
`" Metal Deposition Products Division;
`
`° Equipment Set Solution Division
`
`Abstract
`
`A chemical mechanical polishing (CMP)
`process for copper damascene has been developed
`and characterized
`on
`a
`second generation,
`multiple
`platen
`polishing
`tool.
`Several
`formulations of experimental
`copper
`slurries
`containing alumina
`abrasive
`particles were
`evaluated for their selectivity of copper to Ta,
`TaN and PETEOS film. The extent of copper
`dishing and oxide erosion of these slurn'es is
`investigated with various process parameters
`such as slurry flow rate, platen speed and water
`pressure. The amount of dishing and erosion is
`found to be
`largely dependent on process
`parameters as well as the slurry composition.
`It
`is shown that the extent of oxide erosion and
`copper dishing can be significantly reduced by
`using a two slurry copper polish process (one
`slurry to polish copper and another to polish
`barrier layers) in conjunction with an optical end-
`point detection system.
`
`Introduction
`
`industry
`semiconductor
`trend in
`The
`continues to move towards faster miniaturized
`integrated circuits
`for ever
`increasing device
`packing densities.” As device architectures are
`scaled down to submicrometer dimensions, RC
`delay of metal interconnects plays an important
`role on the device performance.
`In order to
`increase the switching speed, RC delay of metal
`interconnects must be
`reduced. Aluminum,
`interconnects widely used in present VLSI
`devices,
`raises
`reliability concerns with the
`shrinking device dimensions which rules out the
`possibility of using Al
`in future submicron
`devices. Because of the superior conductivity
`(resistivity of copper
`is about
`1.7 HQ-Cm
`compared to 3.0 ufl-cm for aluminum), higher
`resistance to electromigration (electromigration
`limit
`for copper
`is
`107 A/cmz and that
`fcr
`aluminum is
`10‘ A/cm’)
`and
`reduced
`susceptibility to joule heating, copper is being
`
`the
`for
`considered as a potential candidate
`replacement of aluminum in
`future metal
`interconnects? However, patteming copper via
`traditional dry etch techniques is problematic
`mainly due to lack of volatile copper compound
`formation at low temperatures. This difficulty can
`be overcome by following an alternative approach
`using metal inlay structures such as single and
`dual damascene in conjunction with chemical
`mechanical polishing (CMP). M
`
`the dielectric
`In a Damascene approach,
`is patterned and etched using standard
`layer
`procedures. Barrier and copper films are then
`deposited on the patterned surface. Next,
`the
`copper surface topography is removed by C MP.
`Another challenge
`in
`copper
`technology is
`developing a good deposition technique for
`copper.
`A good barrier
`layer material
`is
`necessary to prevent diffusion of copper
`into
`silicon. The barrier
`layer must be thin to
`minimize the resistance of contact holes, vias and
`metal lines.
`In addition, the barrier layer must
`be able to be planarized with a CMP process.
`Materials such as Ta, TaN, and TiN are the
`most commonly studied barrier layers for copper
`and
`are
`planarized
`using CMP
`process.
`Although many techniques such as sputtering
`(PVD), chemical vapor deposition (CVD) and
`electro-chemical deposition (ECD) are currently
`being considered as film deposition options,
`further refinements of deposition parameters are
`necessary in order to obtain more uniform copper
`films.
`
`Although CMP offers an attractive solution
`for implementing copper technology in integrated
`circuits, many challenges exist in developing a
`manufacturable copper CMP process. The key
`process issues which must be taken into account
`in developing a production worthy copper CMP
`process
`include
`control
`of within-wafer
`unifonnity, wafer-to-wafer uniformity,
`copper
`dishing, oxide erosion, corrosion and post CMP
`
`0-7903-4380-8190/510.00
`
`1998 IEEE
`
`354
`
`1993 IEEEISEMI Advlncod Semiconductor Ilanufacturlna conference
`
`Page 9 of 18
`
`RE
`DA
`CT
`ED
`
`RED
`ACT
`ED
`
`RE
`DA
`CT
`ED
`
`RED
`ACT
`ED
`
`Page 9 of 18
`
`
`
`velocity, down force, slurry flow rate or pad
`hardness.
`
`The wafers used in this study contained test
`str'uctures with different line widths and spacings.
`Copper deposition was carried out with either
`PVD, CVD and/or ECD techniques. The barrier
`layers were either Ta or TaN.
`In the case of a
`single slurry process the same slurry was used to
`polish copper and barrier layers.
`In the case (f
`two-step copper polish process, one slurry was
`used to polish .copper and the other slurry was
`used to polish the remaining barrier
`layers.
`Copper polishing was carried out on the first
`platen and the barrier layer was polished on the
`second platen.
`The bufl° and rinse step was
`accomplished on the third platen.
`In both cases,
`multiple polishing steps were used.
`During
`some of the single slurry processes, one or more
`polishing steps were carried out on the first
`platen and the rest of the steps were carried out
`on the second platen. Again one but? and rinse
`step was done on the third platen. All
`the
`erosion
`and
`dishing measurements were
`performed with
`a Tencor HRP200
`high
`resolution profilometer.
`
`Results and Discussion
`
`The main contribution to copper dishing
`and oxide erosion comes from over-polishing,
`which is often necessary to assure complete
`removal of copper and barrier residues across the
`entire wafer. The uniformity variations of the
`copper thickness of the as deposited wafers can
`make the CMP step problematic.
`In the ideal
`case, one would like to fully planarize the copper
`layer
`before
`reaching
`the
`barrier
`layers.
`Depending on the sluny chemistry,
`the same
`slurry or a diflerent slurry can be used to polish
`residual copper and the barrier
`layers
`thus
`creating a
`structure with metal
`inlaid
`in
`dielectric. Large differences in chemical reactivity
`of copper and tantalum result
`in dissimilar
`polishing rates of the two layers.
`In the case cf
`single slurry processing, the barrier removal rate
`is significantly lower than that of copper. Hence,
`during barrier polishing,
`the exposed copper
`feature dishes due to continued chemical and
`mechanical action. Table I shows the copper
`removal rates and selectivities of copper to barrier
`layers for the slurries used in this study.
`
`this
`cleaning.” In view of space limitations,
`paper focuses only on the characterization of two
`key CMP process issues namely copper dishing
`and oxide erosion. In general, copper dishing is
`defined as the difference in height between the
`lowest point of a single copper line/bond pad
`(usually at the center of the structure) and the
`surrounding oxide film. Oxide erosion is defined
`as the difference in the oxide layer thickness
`within an array of line structures before and after
`CMP processing (Therefore, the total copper loss
`of a given feature during CMP is the sum cf
`erosion and dishing).
`
`Both copper dishing and oxide erosion can
`generate a significant amount of surface non-
`planarity which cause various process integration
`problems. They reduce the dielectric spacing and
`amount of copper
`in the interconnects,
`thus
`leading to increased interconnect resistance and
`deterioration of device performance. Hence, it is
`vital to develop a CMP process with minimum
`copper dishing and oxide erosion. The extent <f
`copper dishing and oxide erosion is found to be
`heavily dependent on CMP consumables (slurry,
`pad), process parameters (wafer pressure, platen
`speed) as well as device features (line width,
`spacing).
`In this paper, we describe the
`reduction of dishing with the use of multiple
`polishing steps and multiple polishing slurries
`in conjunction with an optical end-point system.
`
`Experimental Procedures
`Copper CMP was carried out on Applied
`Materials Mirra“
`polisher
`using
`Titanm
`polishing
`heads.
`The
`experiments were
`performed by using polyurethane pads
`and
`several experimental copper CMP slurries which
`use alumina abrasive particles. All slurries were
`provided by Cabot Corporation. Hydrogen
`peroxide oxidizer was added to each slurry and
`mixed well prior to polishing.
`Slurry was
`continuously agitated during the experiments.
`Wafer pressure was varied between 1.0 psi and
`6.0 psi, platen speed was varied between 33 rpm
`to I43 rpm and slurry flow rate was varied
`between 75 ml/min and 220 ml/min.
`In evelrlu
`case the end-point was detected with the ISRM
`system.
`The Laser based ISRM module is
`embedded in the polishing platen. When the
`laser beam is incident on the film surface during
`polishing,
`the ISRM system probes the film
`surface, collects and processes data, and displays
`a real time signal. This process continues until
`a pre-set end point is reached. Data are collected
`only when the laser beam is incident on the film
`surface,
`therefore,
`the ISRM signal does not
`depend on process parameters such as platen
`
`Page 10 of 18
`
`356
`
`1998 IEEEISEMI Advanced Semiconductor Manufacturing °°n*°N"°°
`
`RE
`
`REDA
`CTED
`
`REDACTED
`
`Page 10 of 18
`
`
`
`
`
`
`
`
`
`
`(DE
`IIIIIIIII
`Slurry A
`EMMMMMMMIIHWIII
`
`Slurry C
`169
`
`
`
`IHE%w
`
`137:1
`207:1
`~ 3:1
`
`
`Table 1. Copper removal rate and selectivity to barrier films for various copper CMP slurries at a platen speed of
`43 rpm and a wafer pressure of 4.0 psi.
`
`As shown in Table I, either slurry A or B can be
`used in the single slurry process since they have
`a high copper removal rate. Slurry C is well
`suited for clearing barrier layers since the copper
`removal rate in this slurry is comparable to
`barrier removal rates. An ideal single step slurry
`would polish Cu and the barrier film at similar
`removal rates (low selectivity to ban'ier) and
`would also have a very low removal rate for the
`field
`oxide
`(high
`selectivity
`to
`Si02).
`Additionally, such an ideal slurry would remove
`
`residual Cu and barrier without dishing Cu
`interconnects and eroding the dielectric layer.
`
`The majority of the single slurry process
`discussed in the present work was carried out
`with slurry A. The dependence of the copper
`dishing and oxide
`erosion on the process
`parameters such as slurry flow rate, platen speed
`and wafer pressure was investigated with this
`slurry. In every case, end-point was detected with
`the ISRM system. All wafers were 10% over-
`polished after the end-point was detected. Figure
`1 shows a end-point trace of a blanket copper
`film containing Ta barrier film.
`
`
`
`RefledanceIntensitycm98§E
`
`
`
`Time (a)
`
`Figure 1.
`
`ISRM trace of a blanket copper film containing Ta barrier. End-point is shown by the dotted line.
`
`Page 11 of 18
`
`1998 IEEEISEMI Advanced Semiconductor Manufacturing confonnce
`
`Page 11 of 18
`
`
`
`andErosion
`NormalizedDishing
`
`
`so
`
`70
`
`7
`
`so‘
`
`13.0
`- no
`2150
`51"“? F1°W(ml/min)
`'
`'
`‘
`Figure 2. Dependence of copper dishing and oxide erosion on slurry (slurry A) flow rate. Platen speed and wafer
`pressure were held constant. Dishing was measured on a 50mm thick- line (pitch 15.0mm) while erosion was
`measured at a 0.5mm thick line (pitch 1.0mm).
`
`170
`
`190
`
`difiérent
`1,
`shown in Figure
`As
`interfaces of the film stock can be accurately
`detected with the end-point system. The amount
`of over-polish in a single slurry process
`is
`defined as the percent polish time afler the end-
`1 .
`
`point is reached. Figures 2-4 show the extent cf
`copper dishing observed in a 50pm copper line
`and extent of oxide erosion observed in a 0,5|.lm
`feature as process parameters such as slurry flow
`rate, wafer pressure and platen speed are varied.
`‘.-'3
`.
`-
`
`
`
`€03‘U
`
`505
`
` M
`%n2
`
`'2
`
`0
`
`oa;
`
`.‘
`.19!
`”'
`
`2‘
`-2o--so-'
`~
`
`.. vv .
`‘"7 _‘ i.
`_w 390'
`40‘
`to
`-Plntenufipeedirpm)
`‘
`
`7
`
`’_
`
`t
`
`90
`
`Imp‘
`e'“‘
`
`L,
`
`'shjng 'd ‘xid "’ei‘o '
`laten s
`§i¢§.;Iuere3.wfipicle‘:n:J1i)stizi:|f)tI:pe‘li)‘i;hmgV §vnasomea:meE“:i1o:g0um
`
`measured at 0.5mm line,.(pitch 1.0mm)-
`
`(slurry A). Slurry flow rate and wafer
`(pitch 150mm) while erosion was
`
`€='\
`
`:im-.'‘' so‘.
`
`.1»-1.:».tlhr~-3 '-~.-- fir tl.;‘..~‘uT:‘. “ "":<‘
`
`Page 12 of 18
`
`qgulsgasmnmusmkamuehrflultliwmmcummlfl
`
`REDAC
`TED
`
`Page 12 of 18
`
`
`
`3 4
`
`0
`
`1
`
`2
`
`5
`
`6 r
`
`7
`
`8
`
`R
`
`
`
`2NormalizedDishingandErosion B
`
`o
`
`Waferhesoure (poi)
`Figure 4. Dependence of copper dishing oxide erosion on wafer pressure (slurry A). Platcn speed and slurry
`flow rate were held constant. Dishing
`was measured on 50mm feature (pitch .150mm) while erosion was measured
`at 0.5mm line ‘(pitch 1.0mm).
`
`Data in Figure 2 show that copper dishing
`is somewhat higher at high slurry flow rates.
`This may be caused by continued chemical
`etching of copper. Also, the copper dishing is
`relatively high at higher platen speeds and higher
`
`wafier pressures. Both the oxide erosion and
`copper dishing appear to linearly increase with
`platen speed as well as
`the wafer pressure
`(Figures 3 and 4).
`
`a "A
`---A-.--SlunyB
`-—-O_%_S_lunyA
`---I-- SlurryB
`
`'
`
` 9 \
`
`5
`
`5
`
`To
`
`I-ineWidth_(u).
`2
`
`'
`
`_w
`
`Figure 5. Comparison of copper dishing and oxide erosion of single slurry process under identical experimental
`conditions (slurry A and slurry B). Copper dishing on slurry B is relatively smaller compared to that of slurry A.
`Both slurries have similar oxide erosion perfonnance.
`
`an ~
`
`.
`
`Page 13 of 18
`
`
`Page 13 of 18
`
`
`
`
`
`5 S
`
`EE
`
`MID
`
`(Normalized)
`AmountEtched
`
`
`0
`
`p
`
`Q
`
`11)
`
`1” ,
`
`113318)
`
`II)
`
`Figure 6. Static copper etch rate at room temperature (slurry. A and Slurry B).
`
`In order to improvethe dishing in‘ a.
`single slurry process, another slurry formulation
`(slurry B) was evaluated.
`5 the
`extent of dishing and erosion observed, with
`single slurry processes (slur’ry——A,,and slurry»-B).
`under identical polishing cendifions.
`.It is seen
`that dishing and erosion
`'of's‘_lurry “B
`is somewhat improved "as to sliii3){~A.,_*’.
`Improved dishing in- s4lurry‘Bnfayberel;tiéd5to=a’ ~.
`.:(Fi‘“‘%5)" i*“,“°fi
`low static etchmte<ofslurry=ZB
`
`.4< ,
`
`.'
`
`r etch rate cf
`shown in Figure 6, static co
`that ofslurry
`‘.7 ~.s1ufryAis.considerably'hi_gl1er’
`Therefore, slurry B reduces static etching
`the barrier ‘removal and over-polish,
`'leadirig»_to lower copper dishing“ levels. _Because
`_
`_
`_
`_
`.j0ftI_1e<impr:oved dishing performance of_3slun-y B
`(comparedto slurry A), slurry B ‘was selected as
`— _fl1e first step slurry for the tvvoaislurry process
`,
`
`,
`
`._.
`
`g
`
`
`
`Ep 4- :1
`
`E21’ + :2
`
`Polish Time (3)
`
`d ad for one slurry (slurry A) process and two slurry
`b
`f 100
`‘
`'
`mung ° m “I P
`yh end-point and :1, :2, :3
`Figure 7. Comparison of copper
`In the case of one slurry process, EP is the time to re
`t2,_ and B are the over polish times with slurry
`(slurry B and slurry C) processes.
`are the over polish times.
`In the case of the two slurry process, tl,
`C.
`
`.a‘I
`
`_-v-
`
`‘e.
`
`V. M! ..—
`
`:3:
`
`" v" ‘W
`‘P
`
`age,14 of
`
`RE
`DA
`CT
`ED
`
`Page 14 of 18
`
`
`
`In the two slurry polish process, copper
`was polished to the barrier layer with slurry B
`followed by removal of the barrier layer with
`slurry C.
`It is very important to remove all the
`copper with slurry B before using slurry C since
`slurry C has a very low copper removal rate.
`Figure 7 compares the copper dishing observed
`in a 100p.m copper line with one slurry process
`as well as the two slurry process. Slurry A was
`used only in the one slurry process to clear the
`film stack all the way down to the oxide layer.
`In the case of the two slurry process approach,
`slurry B was used to polish copper. With the
`use of ISRM, polishing was
`stopped when
`copper was cleared to the Ta layer. Slurry C was
`used to polish the Ta layer and for evaluation (f
`overpolish effects after reaching oxide. As shown
`
`in Figure 7, although the extent of dishing
`increases as a function of the amount of over
`polish for both processes, the two slurry process
`considerably reduces
`the
`amount of copper
`dishing. In the case of the single slurry process,
`the extent of dishing significantly increases with
`the amount of over-polish.
`
`uniformity
`significant
`the
`Because of
`variation of the incoming wafers, in some copper
`wafers, copper dishing was observed even at a
`20% under-polish (Figure 8).
`As shown in
`Figure 8 the amount of copper dishing linearly
`increases with the
`extent of over polish.
`Therefore, unnecessary over-polishing should be
`avoided and could be greatly reduced by using a
`reliable end-point detection system.
`
`05
`
`E
`
`NormalizedDishingB8
`
`
`
`Figure 8. Effect of over polish on the extent of dishing
`were buffed with oxide slurry.
`
`in 100 in bond pads (slurry A). After polishing the wafers
`
`(%) Over Polish
`
`Furthermore, it was found that many ofthe
`irregularities observed in the single slurry
`process could be significantly reduced with the
`two slurry process. Figures 9 and 10 show the
`dependence of copper dishing and oxide erosion
`on various copper features for one slurry process
`
`as well as for two slurry process. As shown in
`these figures it is very clear that two slurry
`process results in significantly improved copper
`dishing and oxide erosion performances. Figure
`11 compares the total copper loss in various
`copper lines for single and two slurry processes.
`
`Page 15 of 18
`l
`
`1998 IEEISEMI Advanced semiconductor flnnufaeturlng conference
`
`REDACT
`ED
`
`REDACTED
`
`Page 15 of 18
`
`
`
`REDAC
`TED
`
`REDAC
`TED
`
`REDAC
`TED
`
`REDACT
`ED
`
`REDACT
`ED
`
`REDACT
`ED
`
`REDAC
`TED
`
`REDACT
`ED
`
`Page 16 of 18
`
`
`
`Loss
`NormalizedTotalCopper
`
`
`25].!
`
`35p
`
`751.1
`
`Line Width
`
`Figure 11. Comparison of total copper loss (dishing + erosion) for one slurry (slurry A) and two slurry (slurry B
`+ slurry C) processes in a variety of copper line sizes.
`
`the two slun'y process
`As seen in Figure 11,
`significantly reduces the amount of total copper
`loss
`(dishing + erosion)
`in
`copper
`lines
`compared to the single slurry process. The data
`presented in Figure 11 were derived from the
`
`resolution
`measurements made with a high
`profilometer. These data are in good agreement
`with the electrically measured copper thickness
`for single and two slurry processes (Figure 12)
`measured with a short loop test pattern.
`
`33
`
`E l
`
`0n
`
`_E_ new
`.
`n.
`
` ,, 0&1]
`
`(1400
`
`eU E
`
`2 0.200
`
`(mm
`
`Slurry A, 20%
`overpolish
`
`Slurry A, End-
`pointed
`
`Slurry B + C, End.
`pointed
`
`Figure 12. Comparison of electrically measured copper thickness for one slurry (slurry A) and two slurry (slurry
`B + slurry C) processes. Measurements were performed on a 10 m xl0m Van der Pauw structure.
`
`The data displayed in Figure 12 were measured
`on l0uxl0u Van der Pauw structures.
`As
`expected,
`the wafers processed with slurry A
`show heavy copper loss in the line structures.
`It
`can be seen that about 40% of additional copper
`is lost by performing 20% over-polish after end-
`point detection. However,
`in the case of two
`slurry process, only 10% copper is
`lost when
`polishing was stopped at end-point.
`
`ll
`
`Page 17 of 18
`
`362
`
`1998 IEEEISEMI Advanced semiconductor Manufacturing Conference
`
`REDACTED
`
`Page 17 of 18
`
`
`
`REDACTED
`
`REDACTED
`
`REDACTED
`
`RED
`ACT
`ED
`
`RED
`ACT
`ED
`
`REDAC
`TED
`
`REDAC
`TED
`
`REDAC
`TED
`
`REDAC
`TED
`
`REDAC
`TED
`
`RED
`
`Page 18 of 18
`
`