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`[111
`1191
`3,838,442
`United States Patent
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`Humphreys [45] Sept. 24, 1974
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`1 3,584,264
`3,597,834
`3,622,384
`3,649,888
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`6/1971 McLouski et al................. .. 317/234
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`Lathrop et al .
`. . . . ..
`. . . .. 29/576
`8/1971
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`Davey et al . . . . . .
`. . . . . .. 117/212
`11/1971
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`3/1972
`Pitzer et al.......................... 317/235
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`OTHER PUBLICATIONS
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`IEEE Transactions on Elec. Devices, Oct. 1969, pp.
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`876-877.
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`IBM (TDB), Vol. 8, No. 11, April 1966, p. 1687.
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`Primary Examiner-—Rudolph V. Rolinec
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`Assistant Examiner—E. Wojciechowicz
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`‘Attorney, Agent, or Firm—Thomas F. Galvin
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`[57]
`ABSTRACT
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`In a semiconductor structure with multiple levels of
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`metallization on the surface, each metallization pat-
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`tem is inlaid in trenches formed in an insulating layer-
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`The surface of the metallizatien is flush with or some-
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`What l°Wet than the Surface Oilts associated insulating
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`layer. In a preferred embodiment, the different etch-
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`ing characteristics of glass and silicon nitride are uti-
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`lized to form the trenches in the glass layer. ‘The glass
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`comprises the insulating layer and the nitride forms
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`th
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`th b t
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`e 0 tom of
`e trench
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`5 Claims, 12 Drawing Figures
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`[54] SEMICONDUCTOR STRUCTURE HAVING
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`METALLIZATIQN INLAID IN ]NsULATING
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`é‘:flERS AND METHOD FOR MAKING
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`Inventor: Charles B. Humphreys, Pleasant
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`Valley, NY_
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`Assignee:
`International Business Machines
`Corporation, Armonk, N.Y.
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`-
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`June 9’ 1972
`Flledi
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`APPl- N05 251,343
`Related U.S. Application Data
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`[63] Continuation of Ser. No. 28,891, April 15, 1970,
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`aba,,doned_
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`[52] U.S. Cl....................... .. 357/54, 357/68, 357/71
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`Int. Cl. .......................................... .. H011 29/34
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`[58] Field of Search ........................... .. 317/234, 235
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`References Cited
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`UNITED STATES PATENTS
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`Lemelson .......................... .. 317/101
`8/1969
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`8/1969 Mutter et a1..
`317/234
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`Bergh et al. ........................ .. 156/11
`11/1969
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`[56]
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`3,461,347
`3,461,357
`3,479,237
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`57
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`wvnar 1705!. Av"o.irnran%‘ar1‘irn“‘
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`'27‘meA
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`TSMC Exhibit 1004
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`Page 1 of 9
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`PAIENIEDSEF24-I974
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`’§HEEI 1 OF 2
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`78 FIG. 4A
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`INVENTOR
`é
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`HUMPHREYS
`CHARLES
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` av7r2awu,ox/-
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`moan»
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`PATENI£DSEP24i9?4
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`Page 3 of 9
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`Page 3 of 9
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`1
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`SEMICONDUCTOR STRUCTURE HAVING
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`METALLIZATION INLAID IN INSULATING
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`LAYERS AND METHOD FOR MAKING SAME
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`3,838,442
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`2
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`depositing a second pattern of metallization atop the
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`insulation; (5) simultaneously connecting selectively
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`the first level of metallization with the second level
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`through the via holes; and reproducing steps 2, 3, 4,
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`and 5 to form a third level. This technique, and the
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`many variations of it which have been suggested in the
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`prior art, has resulted in a commercially acceptable
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`transistor structure. However, in production the ratio
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`of acceptable finished circuits to the total number of
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`circuits started initially, i.e., the yield, has remained
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`lower than desired. The basic problem lies in the bumps
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`formed by the conductive lands at the locations where
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`an insulation layer passes over or under the conductive
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`lands which form the metallization pattern. These
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`humps are present in all techniques which appear in pa-
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`tents and technical publications directed to insulating
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`the multilevel metallization patterns printed on top of
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`the chip. They are not evident in many drawings, prob-
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`ably for reasons of clarity and because they had not
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`caused noticeable problems in the particular processes
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`or structures involved. However,
`these humps have
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`been found to be a principal cause of the fonnation of
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`pinholes and stress cracks in the insulation layer and
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`pinholes in the metallization. One reason for this lies in
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`the discontinuity present in the otherwise smooth insu-
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`lation layer where it passes over the conductive metalli-
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`zation pattern. The stress on the insulation layer is
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`greatest at that location. In addition, there are locations
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`in a non-planar insulation layer where its thickness is
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`less than the average thickness. These locations will
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`have more pinholes than average. These pinholes and
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`stress cracks may cause one portion of a metallization
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`pattern to “short” with another; or cause one portion
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`of one level of metallization to short with another level.
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`Pinholes and stress cracks in the insulation layer may
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`also cause pinholes in the metallization. During an
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`etching process on the metallization, the etchant may
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`seep through the insulation and attack the metal at an
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`undesired location, resulting in the pinhole. Pinholes in
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`the metal may, in turn, cause pinholes in the insulation
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`layer if an insulation etchant seeps through the metal.
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`Any of these occurrences can cause a defective chip.
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`This is a continuation of application Ser. No. 28,891
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`filed Apr. 15, 1970 and now abandoned.
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
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`This invention relates to semiconductor structures
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`wherein crossover connections between active devices
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`within the structure, external leads and power buses are
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`formed on the surface of the semiconductor body.
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`2. Description of the Prior Art
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`Recent technological advances have enabled transis-
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`tor manufacturers to place more and more active and
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`passive elements into the body of a semiconductor
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`chip. For example, it is possible to form more than 500
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`such elements into a chip having an area of less than
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`100 by 100 mils. This has presented a serious problem
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`in interconnecting the devices within the chip to form
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`circuits and in providing external connections from the V
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`chip.
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`Several alternative techniques have been advanced,
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`none of which have met with great success.
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`In one method, the connections are formed sepa-
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`rately on multilayered ceramic substrates. With this
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`method, many of the interconnections between individ-
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`ual devices as well as substantially all of the external
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`connections to other sources are formed on the various
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`layers of the laminated ceramic structure. However,
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`this method has the basic flaw of consuming a large_
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`area as compared to the size of the semiconductor chip
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`mounted thereon. In addition to the basic flaw, there is
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`a problem of the length of the connection between the
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`device within the chip and the connection on the ce-
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`ramic. The longer the lead, other factors being equal,
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`the longer it will take a signal to propagate. This has led
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`to the rather anomalous result of having the transistor
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`“package” cause a considerable portion of the total
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`delay in signal propagation. Of course, as the art has
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`advanced in forming a device within a smaller area of
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`the semiconductor chip, this problem has grown stead-
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`ily worse, relatively speaking.
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`A second technique which has received considerable
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`publicity is the bonding of external connections at the
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`periphery of the chip itself or on a ceramic substrate
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`which holds the chip. These connections, in the form
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`of wires of minute diameter, jump over the active areas
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`of the chip, very similarly to conventional wiring. The
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`problems with this technique are the fragility of the
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`wires and the great difficulty in bonding the wires to
`small contact areas.
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`A third technique, to which the present invention is
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`directed, is to produce most of the conductive connec-
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`tions in multiple levels on the surface of the chip itself.
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`In circuits requiring relatively few interconnections be-
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`tween devices and few power connections, all of the
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`metallization may be confined to one level. However,
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`the art has progressed to having such increased density
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`of devices per chip that more than one metallization
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`level is required. In general, the prior art multilevel
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`metallization technique has comprised:
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`(1) the deposition of ohmic contacts and certain de-
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`vice interconnections on a first level; (2) depositing
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`one or more insulation layers atop the first metalliza-
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`tion; (3) producing via holes within the insulation; (4)
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`SUMMARY OF THE INVENTION
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`It is therefore an object of this invention to provide
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`an improved semiconductor structure with multilevel
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`metallization on the surface thereof and a method for
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`making it.
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`A further object is to provide an improved method
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`for eliminating humps occurring at crossover points of
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`insulation and metallization patterns.
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`Another object is to substantially eliminate pinholes
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`and stress cracks commonly occurring in semiconduc-
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`tor structures having multilevel metallization.
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`Another object is to provide a method for accurately
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`forming trenches in an insulating layer which allows an
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`accurate deposition of metallization in the trenches.
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`The preset invention accomplishes these and other
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`objects by providing a structure in which each level of
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`metallization is inlaid within an associated insulating
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`layer and bottomed on a passivating layer. In each lami-
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`nated section formed by the passivating and insulating
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`layers and the metallization, the surface of the metalli-
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`zation is flush with or somewhat lower than the surface
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`of the insulating layer. However, good results are ob-
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`tained if the surface of the metallization lies within the
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`Page 4 of 9
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`3
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`range of 50A higher than the surface of the insulating
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`layer and 2500A lower than the surface of the insulat-
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`ing layer. This range as defined is termed “substantially
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`flush” in this application and the term will be under-
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`stood to mean that range.
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`- The preferred method is to etch a trench in the insu-
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`lating layer and then deposit the metallization into the
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`trench. The bottom of the trench comprises the upper
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`surface of a passivating layer which is insensitive to the
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`etchant used to etch the insulating layer. Preferrably,
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`the insulating layer is glass and the passivating layer is
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`a conjoint layer of silicon oxide and silicon nitride; the
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`nitride is the upper portion of the conjoint layer.
`IN THE DRAWING
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`FIG. 1 is a sectional perspective view of the junctions
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`of a single active device within a passivated planar
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`semiconductor chip.
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`FIG. 1A is a view of the top surface of a portion of
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`the chip showing two active device areas.
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`FIG. 2-5 show various stages of producing ohmic '
`contacts and the first metallization level of active de-
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`vices in accordance with the invention.
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`FIGS. 6 and 7 show an active device with second and
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`third levels of metallization, respectively,
`in accor-
`dance with the invention.
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`FIGS. 6A and 7A are views of the top surface of the
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`chip showing the metallization patterns connecting the
`active devices.
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`All of the figures are not necessarily to scale. In some
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`instances, the dimensions have been exaggerated for
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`clarity and to show particular aspects of the invention.
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`Referring now to FIG. 1 and FIG. 1A, a semiconduc-
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`tor chip 8 is shown having a substrate 10 which is cov-
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`ered by two passivating coatings 12 and 14. The chip
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`is one section of perhaps 50 or 60 such chips which to-
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`gether form a semiconductor wafer. Within the sub-
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`strate 10 are areas, generally denoted as 16 and 18,
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`containing surface junctions which form active devices.
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`The bulk of substrate 10 may comprise a monocrystal-
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`line p—type silicon semiconductor body having an ori-
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`ented surface and exhibiting relatively high resistivity,
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`e.g., in the order of IO ohm-cm.
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`Typically, chip 8 is around 100 by 100 mils, and, of
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`course, contains many active areas of which areas 16
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`and 18 are merely illustrative. In addition, the chip may
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`contain regions which are passive, i.e., resistive and ca-
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`pacitive, which may also be connected on top of the
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`chip in accordance with the present invention.
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`FIG. 1 is a sectional perspective view of area 16,
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`taken along line l—l of FIG. 1A. Area 16 is totally
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`within chip 8 except for the upper surface, which ini-
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`tially is completely covered by conjoint passivating
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`coatings 12 and 14 which together form a passivating
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`layer. For simplicity and ease of understanding, area 16
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`is depicted as a segment removed from chip 8. Further-
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`more, it will be understood that each of the processes
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`to be performed on area 16 is also performed, prefera-
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`bly simultaneously, on area 18. Within area 16, there
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`is shown a planar N-P-N junction device. The fabrica-
`tion of this kind of device is well known to those skilled
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`in the art. It will be recognized that the invention is not
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`confined to a particular type of device or process of
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`forming the device. For instance, the device could be
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`a P-N-P type with an N type substrate 10. Also, germa-
`nium instead of silicon could be used as the semicon-
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`.
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`Pagei5iof9
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`60
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`65
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`3,838,442
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`4
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`It
`is important only that the ohmic
`ductor material.
`contacts be formed at the surface of the device, the sur-
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`face being substantially planar.
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`Coating 12 is preferrably an oxide of silicon. Any
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`conventional technique may be used to form the silicon
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`oxide layer. The particular choice will depend on the
`nature of the semiconductor material. In the case of a
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`silicon wafer, a silicon dioxide coating is formed prefer-
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`rably as a genetic coating formed by thermal growth
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`from the silicon body itself. One preferred technique is
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`to heat the body to between 900° C. to l400° C. in an
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`oxidizing atmosphere of air saturated with water vapor
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`or in an atmosphere of steam, thus forming a silicon di-
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`oxide coating. Alternately, an R.F. sputtering method
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`may be used to form the silicon dioxide coating. If the
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`semiconductor material is germanium rather than sii-
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`con, a silicon oxide coating may be formed by pyrolytic
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`decomposition of ethyl silicate vapor. In the present
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`embodiment, coating 12 is silicon dioxide with a depth
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`of 600a. The thickness preferrably ranges from 2000A
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`to 8000A. In the remainder of the specification, the
`term silicon oxide will be understood to also include sil-
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`icon dioxide. The silicon nitride coating 14 is contigu-
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`ous with silicon oxide coating 12. The silicon nitride
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`coating may be formed by known techniques such as
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`R.F. sputtering, as described in co-pending application
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`Ser. No. 494,789, filed Oct. 11, 1965, or by reactive
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`sputtering, as described in co-pending application Ser.
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`No. 583,175, filed Sept. 30, 1966. Both of these appli-
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`cations are assigned to the assignee of the present in-
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`vention. A third technique which could be used to form
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`the silicon nitride coating is the pyrolytic decomposi-
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`tion of a gaseous mixture of silane and ammonia which
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`is heated to around 900° C. The preferred technique is
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`to R.F. sputter the silicon nitride coating to a thickness
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`of around 1000A, but preferrably below 2000A.
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`The ranges of thickness of silicon oxide coating 12
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`and silicon nitride coating 14 may vary from the pre-
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`ferred thickness. However,
`in the preferred embodi-
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`ment of this invention, it is important that the total
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`thickness of the conjoint layer be precisely controlled
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`or measured after deposition, as the metallization layer
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`to be applied will be substantially flush with a glass
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`layer which will be applied in a later step. In place of
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`the conjoint passivating layer 12/14 of oxide and ni-
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`tride, a single layer of silicon nitride might be used.
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`However, the nitride layer alone may not insure the
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`requisite passivation for structures with extensive met-
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`allurgy.
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`The precise depth of the oxide and nitride coatings
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`may be calculated by standard techniques. For exam-
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`ple, the thicknesses may be measured by means of a
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`technique described in “Non-Destructive Technique
`for Thickness and Refractive Index Measurements of
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`Transparent Films," W. A. Pliskin and E. E. Conrad,
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`IBM Techincal" ' Disclosure Bulletin, Vol. 5, No. 10,
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`March 1963, pp. 6-8. Preferrably, this technique is
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`augmented with a spectrophotometer as described in
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`“Transparent Thin-Film Measurements by Visible
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`Spectrophotometry,” A. Decobert and M. Lachaud,
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`IBM Technical Disclosure Bulletin, Vol. 10, No. 11,
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`April 1968, p. 1799.
`‘Besides this non—destructive
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`method of testing the thickness of transparent thin
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`films, any well-known destructive method using a test
`wafer could be used. One known destructive method is
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`the so-called angle-lap technique. One end of the test
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`wafer is beveled at a very small angle to expose a rela-
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`Page 5 of 9
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`

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`3,838,442
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`6
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`Pat. No. 3,369,991, P. D. Davidse et al. Other deposi-
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`tion methods may be used. such as silk screening or py-
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`rolytic deposition. In any method the chemical compo-
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`sition of the glass is SIO2. As with the conjoint coatings
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`12 and 14, the thickness of glass layer 26 must be accu-
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`rately controlled or measured to insure that the quan-
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`tity of metal deposited in a later step will be substan-
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`tially flush with glass layer 26. The thickness of the
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`glass is preferrably from 5000A to 20,000A. In the
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`present embodiment it is l0,000A. The measurement
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`of the glass depth may be determined or controlled in
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`the same manner as previously described for the oxide
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`and nitride coatings. It is evident that the measurement
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`of the depth of conjoint passivating layer 12/14 could
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`be performed after layer 26 has been formed.
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`FIG. 4 is a sectional perspective view showing the
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`ohmic contact regions 21-24 re-exposed. FIG. 4 also
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`shows area 27 and trench 28 which have been forme_d
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`by conventional techniques in glass layer 26, but which
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`do not penetrate nitride layer 14. Area 27 is sur-
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`rounded on three sides by glass layer 26 and is bot-
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`tomed at nitride coating 14. Area 28 is a trench etched
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`in glass layer 26 and is also bottomed at nitride coating
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`14. FIG. 4A is a top view of wafer 8 at this point in the
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`process. FIG. 4A shows that areas 77 and 78, similar to
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`area 27 and trench 28, have also been formed over de-
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`vice 18 and that trenches 75 and 76 have been formed
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`in glass layer 26 to connect appropriate contacts of de-
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`vices 16 and 18. Trenches 75 and 76 are also bottomed
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`at nitride coating 14.
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`In forming the trenches and area 27, use is made of
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`the fact that the glass etchant, which is preferrably the
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`buffered hydrofluoric acid used previously to etch
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`oxide coating 12, will not attack the nitride to any sig-
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`nifiant degree. In the etching process, a photoresist
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`mask corresponding to openings 21-24, 27 and trench
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`28 is placed on the surface of glass 26. The surface of
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`glass 26 is then exposed to a buffered etchant, as previ-
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`ously described, which does not attack the nitride coat-
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`ing 14. Nitride coating 14 protects the surface of oxide
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`coating 12. The buffered etchant does not significantly
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`attack oxide coating 12 which surrounds resigns 21-24.
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`tively broad surface of the layer to be measured. The
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`beveled surface of the sample is stained or otherwise
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`treated to delineate clearly the exposed surface of the
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`layer. Monochromatic light is then directed through an
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`optically flat glass plate onto the beveled surface. Light
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`reflected from the beveled surface interfaces with light
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`reflected from the glass plate to establish interface
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`fringes along those locations of the beveled surface that
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`are displaced from the flat glass plate by some multiple
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`of a half wavelength of the light. These fringes can
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`therefore be interpreted as being contour lines repre-
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`senting successive gradations of height on the beveled
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`surface. The distance between each pair of fringes,
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`called an order of interference, is representative of a
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`vertical distance of one-half wavelength. An operator
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`counts the number of fringes located along the beveled
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`layer surface to be measured, and thereby estimates the
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`total thickness of the layer.
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`In the modern manufacturing process, of course,
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`there are other methods to determine and control the
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`thickness of the coatings. For example, the process may
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`be calibrated based on a test batch of wafers and the
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`results used in succeeding batches with no further ‘
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`measurements being needed. In addition, it may be pos-
`25
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`sible to monitor the deposition of the coatings during
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`the process, eliminating the need for thickness meas-
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`urements at the completion of the process.
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`Referring now to FIG. 2, device 16 is shown after
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`having received ohmic contacts at base regions 21 and
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`23, emitter region 22 and collector region 24. FIG. 2A
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`is a top view of the wafer showing identical contacts
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`having been formed in both devices 16 and 18. The
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`openings for contacts 21-24 are formed by first provid-
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`ing a conventional photoresist mask corresponding to
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`the openings. The silicon nitride coating 14 is then sub-
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`jected to an etchant which in the present embodiment
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`does not attack the oxide layer 12. Molten ammonium
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`hypophosphate (NH.,H,PO4) is preferrable. Alterna-
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`tively, hot phosphoric acid may be used. After the ni-
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`tride is removed from the areas not masked, the silicon
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`dioxide is removed from the same areas by a conven-
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`tional buffer etchant which does not attack the nitride.
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`A solution of hydrofluoric acid buffered in ammonium
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`fluoride is suitable. This procedure exposes the sur-
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`faces of the active regions at 21, 22, 23, and 24. Ohmic
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`contacts are then deposited, preferrably by applying a
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`blanket layer of metal to the entire surface of the struc-
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`ture. A preferred metal is a 200A blanket of platinum
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`which may be applied by sputtering. The platinum is
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`then sintered at about 450° C.
`to form a- platinum-
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`silicide ohmic contact. The contact causes only a slight
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`topology shift at surfaces 21-24, of around 40 A, most
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`of the platinum diffusing into the active regions. This
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`is too small
`to affect the desired substantially flush
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`characteristic of the metallization to be applied in a
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`later step and can be accurately estimated if necessary.
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`Other metals, such as molybdenum or tungsten, may be
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`used in lieu of platinum. In addition, this step might be
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`dropped altogether,
`if desired. The ohmic contact
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`might be formed at the same time as the later step of
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`metallization. In the preferred embodiment of this in-
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`vention, the blanket of platinum which covers the ni-
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`tride surface 14 is then removed by a conventional sub-
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`tractive etch process. Referring now to FIG. 3, a blan-
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`ket glass layer 26 is shown deposited over the entire
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`surface of the structure. Layer 26 is preferrably depos-
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`ited using R.F. sputtering apparatus described in U.S.
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`5
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`Page 6 of 9
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`10
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`30
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`35
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`40
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`45
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`FIG. 5 shows the structure after metallization has
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`been applied. The metal may be deposited by any suit-
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`able means such as evaporation, pyrolytic decomposi-
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`tion, or sputtering. The preferred metallization process
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`is to mask the entire surface" except contact regions
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`50
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`21-24. A first blanket layer of metal is now evaporated
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`, with a thickness equal to the depth of conjoint pasivat-
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`ing layer 12/14. This first mask is then replaced with a
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`second mask which masks the entire surface except
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`contact regions 21-24, area 27 and trench 28. A sec-
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`ond blanket of metal is now evaporated with a thick-
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`ness equal to or somewhat less than the depth of glass
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`layer 26. In FIG. 5, the metallization in area 27 is de-
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`noted by the corresponding notation 127. Similar nota-
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`tion 121-124 and 128 is used for the metallization ap-
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`0 plied in areas 21-24 and trench 28, respectively. It will
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`be apparent that other techniques might be used to
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`apply the metallization. For example, a mask might be
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`placed over only area 27 and trench 28. A first blanket
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`of metallization might then be applied over the entire
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`surface 26 and into the uncovered regions 21-24. The
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`metallization on the surface would then be stripped off
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`by a subtractive etch technique. A second blanket
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`might then be applied over the entire surface, all open-
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`55
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`65
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`Page 6 of 9
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`ings being uncovered. The quantity applied in the sec-
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`ond blanket would bring the level of metallization in
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`the openings to be substantially flush with the glass
`layer 26. The metallization on the surface would then
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`be stripped off by subtractive etching.
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`The amount of metal to be deposited may be calcu-
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`lated accurately prior to the evaporation process by
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`calculating the volume of the openings and trenches in
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`the passivating and insulating layers. Th surface area of
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`the opening and trenches are precisely defined by the
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`masks used to form them. This is well known. The
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`depth of the passivating and insulating layers is calcu-
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`lated as previously described. In practice, however, the
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`depth is the only key factor, because in either method
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`of depositing the metallization, a uniform blanket will
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`descend on the entire surface of the chip. As a result,
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`all openings are filled uniformly with respect to the sur-
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`face area. The depth of metal deposited may be con-
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`trolled by conventional techniques. In the method of
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`evaporation, a crystal oscillator oscillating at a known
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`frequency is placed inside the evaporation chamber. As
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`the metal is deposited on the wafers and the oscillator,
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`the frequency change in the oscil