(12)
`
`United States Patent
`Hardacker et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,020,121 B2
`Mar. 28, 2006
`
`US007020121B2
`
`(54) METHOD AND SYSTEM FOR WIRELESS
`DIGITAL MULTIMEDIA TRANSMISSION
`
`-
`
`e
`
`3 * > < 3
`
`ylton ...
`
`- - - -
`
`3/1997 Hylton ....................... 455/3.1
`5,613,190 A
`3/1997 Nelson ...
`... 475/248
`5,613,919 A
`5/1997 Hylton ...
`... 455/3.3
`5,630,204 A
`
`(75) Inventors: Robert Hardacker, Escondido, CA ; * ! !. #. - - -
`- - - º
`§§ David A. Desch, Poway, CA
`5,878,324. A
`3/1999 Borth ............
`... 455/3.1
`5,940,757 A.
`8/1999 Callaway, Jr.
`... 455/426
`6,008,777 A 12/1999 Yiu ............................... 345/2
`6,263,503 B1
`7/2001 Margulis .......
`... 725/81
`6,647,015 B1
`11/2003 Malkemes .....
`... 370/401
`2001/0021998 A1
`9/2001 Margulis .......
`... 725/81
`2002/0038459 A1
`3/2002 Talmola .....
`... 725/81
`2002/0181608 A1* 12/2002 Kim et al
`... 375/295
`2003/0126623 A1
`7/2003 Hara ................
`... 725/153
`2003/0.1452.58 A1* 7/2003 Warner et al. .
`... 714/704
`2003/0226,149 A1 12/2003 Chun ...............
`... 725/109
`2004/0196920 A1 * 10/2004 Loheit et al. ............... 3.75/281
`* cited by examiner
`Primary Examiner—Duc Ho
`(74) Attorney, Agent, or Firm—John L. Rogitz
`
`-
`e
`(73) Assignees: Sony Corporation, Tokyo (JP). Sony
`Electronics Inc., Park Ridge, NJ (US)
`-
`-
`- -
`-
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 145 days.
`
`-
`(*) Notice:
`
`(21) Appl. No.: 10/790,162
`
`(22) Filed:
`(65)
`
`Mar. 1, 2004
`Prior Publication Data
`|US 2005/0105498 A1
`May 19, 2005
`
`Related U.S. Application Data
`60) Provisional application No. 60/520.588, filed on Nov.
`(60) º application No
`,588, Illed on Nov
`s
`-
`(51) Int. Cl.
`(2006.01)
`H04Q 7/24
`(2006.01)
`H04L 12/28
`52) U.S. Cl. ....................................... 370/338: 370/401
`: Field of Classification Search
`s
`None
`See application file for complete search history
`-
`References Cited
`
`(56)
`
`|U.S. PATENT DOCUMENTS
`5,243,415 A * 9/1993 Vance ......................... 725/81
`5,559,808 A
`9/1996 Kostreski .................... 370/108
`
`(57)
`
`ABSTRACT
`
`Digital Visual Interface (DVI), or High Definition Multi
`media Interface (HDMI), data is received from a source and
`sent to a transmitter chip that includes a transition mini
`mized differential signaling (TMDS) receiver that outputs a
`3-data and 1-clock physical signaling stream representing
`the DVI or HDMI data. This stream is rendered into I and Q
`data by an ASIC or FPGA and sent to a wireless transmitter
`for modulation, upconverting, and transmission to, e.g., a
`nearby display device without ever rendering the data into
`baseband video on the transmitter chip. The display device
`has a receiver chip that is essentially the inverse of the
`transmitter chip.
`
`18 Claims, 2 Drawing Sheets
`
`16
`
`
`
`DV
`DATA
`SOURCE
`
`DISPLAY
`DV]
`INPUT
`
`RADIO Tx CHIP
`
`22
`
`24
`
`HTC EXHIBIT 1028
`
`Page 1 of 6
`
`

`

`U.S. Patent
`
`Mar. 28, 2006
`
`Sheet 1 of 2
`
`US 7,020,121 B2
`
`16
`/
`RADIO Tx CHIP
`t= RADiO
`TX
`TMDS |
`Rx FPGA OR T- TX
`ASIC
`
`
`
`
`
`
`2
`
`22
`
`24
`
`
`
`DV
`DATA
`SOURCE
`
`DISPLAY
`DVI
`
`RECEIVE DATA
`FROM DVI DATA
`SOURCE
`
`RENDER THE DATA
`|NTO A PHYSICAL
`SIGNALLING
`STREAM
`(3–DATA TMDS)
`
`
`
`STABILIZE
`CLOCK,
`DEJITTER
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`UPCONVERT
`AND
`WIRELESSLY
`TRANSMIT
`
`
`
`
`
`
`
`
`
`FEC, RANDOMIZE
`o?"ºol- DATA, AND
`T
`DIFFERENTIALLY
`X
`ENCODE
`
`Aº.2
`
`TRANSMITTER LOGIC
`
`Page 2 of 6
`
`

`

`U.S. Patent
`
`Mar. 28, 2006
`
`Sheet 2 of 2
`
`US 7,020,121 B2
`
`48
`
`|
`
`FROM | AND Q
`RENDER 3–DATA
`PHYSICAL
`SIGNALLING
`STREAM
`
`
`
`
`
`
`
`
`
`50
`
`
`
`
`
`USE PHYSICAL
`SIGNALLING
`TRANSMITTER (TMDS)
`TO OUTPUT TO
`DISPLAY
`
`
`
`
`
`
`
`
`
`
`
`
`RECEIVE DATA
`AND
`DOWNCONVERT
`TO | AND Q
`
`
`
`
`
`AA. 3
`
`RECEIVER LOGIC
`
`Page 3 of 6
`
`

`

`1
`METHOD AND SYSTEM FOR WIRELESS
`DIGITAL MULTIMEDIA TRANSMISSION
`
`US 7,020,121 B2
`
`RELATED APPLICATIONS
`
`This application claims priority from U.S. provisional
`patent application Ser. No. 60/520,588, filed Nov. 17, 2003.
`
`FIELD OF THE INVENTION
`
`The present invention relates generally to wireless mul
`timedia systems.
`
`10
`
`BACKGROUND
`
`15
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`20
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`25
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`30
`
`35
`
`Digital video can be transmitted from a source, such as a
`computer or Set Top Box (STB), to a display, such as a video
`monitor or entertainment display and associated audio and
`control functions, using one of two protocols known as
`Digital Visual Interface (DVI) and High Definition Multi
`media Interface (HDMI). Having been developed primarily
`for computers, DVI, and having been developed primarily
`for digital displays, HDMI are intended for wired transmis
`sion.
`As recognized herein, to save table space and to increase
`people’s mobility and viewing lines in the room, it may be
`desirable to view the multimedia on a display using a
`minimum of wiring. For instance, it may be desirable to
`mount a projector on the ceiling or to mount a plasma
`display or liquid crystal high definition (HD) television
`display on a wall, out of the way and capable of receiving
`multimedia data for display without the need for wires, since
`as understood herein among other things, while power lines
`exist in ceilings and walls, data transmission lines often do
`not exist in ceilings or walls.
`The present invention further understands, however, that
`not just any wireless transmission system will do. Specifi
`cally, if a wireless link such as IEEE 802.11(b, g or a) is used
`that has a bandwidth which is insufficient to carry uncom
`pressed multimedia such as uncompressed high definition
`40
`(HD) video, compressed multimedia video (standard defi
`nition or high definition) would have to be transmitted,
`requiring a relatively expensive compression module at the
`source and decompression module at the display. Some links
`such as IEEE 802.11 (a) do have a bandwidth high enough
`to carry compressed HD video but not uncompressed SD or
`HD video. Also, in the case of 802.11(a) copyright protec
`tion may be implicated because the link is sufficiently long
`range (extending beyond the room in which it originates)
`that it can be detected beyond the immediate location of the
`transmitting device. With this in mind, the present invention
`recognizes the need for a very short range, preferably
`directional, high bandwidth wireless link that is particularly
`suited for the short range wireless communication of uncom
`pressed multimedia, particularly the rather voluminous
`genre of multimedia known as HD video.
`In any case, as mentioned above for the DVI standard,
`wireless transmission is not envisioned. The present inven
`tion recognizes that to effect wireless short-range transmis
`sion of DVI data, a DVI receiver chip can receive 1 clock
`line and 3-data physical signaling streams representing DVI
`clock, data and control functions and demultiplex it to
`baseband video of 24 bits video and 7 control lines. The
`baseband video can be fed into a processor that re-multi
`plexes the signals and produces both Ain-phase(a), I and
`Aquadrature(a), Q, signals that can be up converted (modu
`lated) by a radio and wirelessly transmitted to a DVI
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`transmitter chip. The DVI transmitter chip can perform the
`inverse of the above process to produce a clock and 3-data
`physical signaling stream that is sent to drive a display.
`As critically recognized herein, the above-discussed sys
`tem, while useful, can be further simplified. Accordingly, the
`solution herein is provided.
`
`SUMMARY OF THE INVENTION
`
`A system includes a transition minimized differential
`signaling (TMDS) receiver on a first substrate, with the
`TMDS receiver being configured for receiving digital visual
`interface (DVI) or high definition multi-media interface
`(HDMI) data. A transmitter processor is on the first substrate
`and receives data from the TMDS receiver. The transmitter
`processor may be implemented a field programmable gate
`array (FPGA) or an application specific integrated circuit
`(ASIC). A wireless transmitter on the first substrate receives
`data from the transmitter processor for wireless transmission
`thereof.
`The system also includes a wireless receiver configured to
`receive data from the wireless transmitter, and a receiver
`processor receiving data from the wireless receiver. Like the
`transmitter processor, the receiver processor may be imple
`mented by an FPGA or ASIC. A TMDS transmitter is
`configured for receiving data from the receiver processor
`and outputting DVI input signals to a display. The preferred
`system thus does not reduce data to a baseband video signal
`during processing.
`The preferred transmitter processor can include phase
`locked loop circuitry for clock stabilization, de-jitter cir
`cuitry for input data stabilization, and it can apply forward
`error correction prior to differential encoding of data. The
`transmitter processor may output I and Q data to the wireless
`transmitter in response to 3-data and 1-clock TMDS streams
`received from the TMDS receiver.
`In another aspect, a method for wireless transmission of
`video data includes receiving the video data at a physical
`signaling stream receiver, rendering the data into a physical
`signaling stream, and rendering the physical signaling
`stream into data suitable for modulation by a radio trans
`mitter. The rendering acts are undertaken without rendering
`the data into baseband video at any time, and then the data
`is wirelessly transmitted. The method includes receiving the
`data and rendering demodulated data from the received data.
`Then, physical signaling stream data is rendered from the
`demodulated data, and these rendering acts likewise are
`undertaken without rendering the data into baseband video
`at any time. The data is output to a display device using a
`physical signaling stream transmitter.
`In yet another aspect, a digital video transmitter includes
`a transmitter processor configured to receive a physical
`signaling stream representing digital video data and based
`thereon, without rendering baseband information represent
`ing the digital video data, outputting a quadrature signal
`suitable for processing by a wireless transmitter.
`In still another aspect, a digital video receiver includes a
`receiver processor configured to receive a demodulated
`quadrature signal and based thereon, without rendering
`baseband information representing the digital video data,
`outputting a physical signaling stream representing digital
`video data.
`The details of the present invention, both as to its structure
`and operation, can best be understood in reference to the
`accompanying drawings, in which like reference numerals
`refer to like parts, and in which:
`
`Page 4 of 6
`
`

`

`US 7,020,121 B2
`
`3
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram showing the inventive system;
`FIG. 2 is a flow chart of the present transmitter logic; and
`FIG. 3 is a flow chart of the present receiver logic.
`
`5
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`
`4
`system can be achieved. For example; when DQPSK is used,
`a data rate of twice the symbol rate can be achieved. For
`8-PSK a data rate of 3.3 Gbps may be achieved.
`It may further be appreciated that the wireless receiver 26
`includes circuitry that is complementary to the wireless
`transmitter 20, namely, a downconverter, a 60 GHz demodu
`lator, and a decoder. In any case, I and Q data from the
`wireless receiver 26 is sent to a receiver processor 28 for
`error correction and for recovering the 3-data physical
`signaling stream from the I and Q data. The receiver
`processor 28 may be implemented by, e.g., an ASIC or
`FPGA. The output of the receiver processor 28 is sent to a
`TMDS transmitter 30, which sends the data over a cable or
`other wire to a display device 32 that may be part of a media
`player such as a DVD player or TV or other player. The
`display device 32 decrypts the multimedia data (if
`encrypted) and presents the data on a display such as a
`cathode ray tube (CRT), liquid crystal display (LCD),
`plasma display panel (PDP), or TFT, or projector with
`screen, etc.
`The skilled artisan can now appreciate that the system 10
`does not include a full DVI or HDMI receiver in the
`transmitter chip 16 or a full DVI or HDMI transmitter in the
`receiver chip 27. Thus, the system 10 does not derive or
`render twenty four lines of baseband video and control
`signals from the 3-data and 1-clock TMDS stream received
`from the source 12, nor does it render baseband video from
`the I and Q signals received over the wireless link from the
`transmitter 16 prior to outputting data to the display device
`32.
`According to the present invention, the components (14
`and 18) of the transmitter 16 may be contained on a single
`chip, or on separate substrates. Indeed, the transmitter 16
`may be integrated into the source 12. Likewise, the compo
`ments (28 and 30) of the wireless receiver 27 may be
`implemented on a single chip and may be integrated into the
`display device 32 if desired.
`FIGS. 2 and 3 illustrate the operation of the transmitter 16
`and receiver 27, respectively. Commencing at block 34 in
`FIG. 2, DVI data is received from the source 12 and
`rendered into a 3-data physical signaling stream by the
`TMDS receiver 14 at block 36. The data is sent to the
`transmitter processor 18 which, at block 38, uses phase
`locked loop (PLL) principles known in the art to stabilize the
`signal clock, and which also applies de-jitter to the signal in
`accordance with de-jitter principles known in the art. At
`block 40 the stabilized 3-data and 1-clock physical streams
`are multiplexed into 2 streams. Also, if desired the trans
`mitter processor 18 can, at block 40, apply forward error
`correction (using, e.g., Reed–Solomon principles), random
`ize the data, and differentially encode the data.
`Block 42 indicates that importantly, the processor 42
`renders the 3-data physical signaling stream into I and Q
`quadrature modulation input data, which is input to the radio
`transmitter 20. At block 44, the radio transmitter 20 up
`converts the data and wirelessly transmits it in accordance
`with wireless transmission principles known in the art.
`Now referring to FIG. 3, at block 46 the data is received
`by the wireless receiver 26 and downconverted to I and Q
`data. The I and Q data is sent to the receiver processor 28,
`which, at block 48, demultiplexes and renders it into 3-data
`and 1-clock physical signaling stream (and which can under
`take conventional functions if desired, such as decryption,
`etc.). The 3-data physical signaling stream is sent to the
`TMDS transmitter 30, which sends it to the display device
`32 for display at block 50.
`
`10
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`15
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`20
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`25
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`30
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`35
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`40
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`50
`
`Referring initially to FIG. 1, a system is shown, generally
`designated 10, which includes a source 12 of Digital Visual
`Interface (DVI) or HDMI data that may be a set-top box,
`laptop computer or other multimedia computer or server. Or,
`it can be a satellite, broadcast, or cable receiver, or it can be
`a DVD player or other multimedia source.
`The data is sent to a physical signaling receiver 14 of a
`transmitter board 16 that preferably contains all of its
`components on a single substrate. In the preferred embodi
`ment, the receiver 14 is a transition minimized differential
`signaling (TMDS) receiver.
`The output of the receiver 14 is sent to a transmitter
`processor 18 that can be implemented by an application
`specific integrated circuit (ASIC) or field programmable
`gate array (FPGA). The processor 18 processes the data in
`accordance with the disclosure below for wireless transmis
`sion by a wireless transmitter 20 over a transmitting antenna
`22. As set forth further below, the transmitter processor 18
`can, among other things, render the input data into I and Q
`quadrature signals such as might be required to support
`QPSK, DQPSK, or similar modulation by the wireless
`transmitter 20. Additional control signals for the display
`may also be multiplexed within the video data stream. Also,
`error correction may be implemented that is appropriate for
`wireless transmission in accordance with wireless transmis
`sion principles known in the art, and data encryption can be
`employed if desired.
`In any case, the multimedia data is wirelessly transmitted
`over a wireless link to a receiver antenna 24, which sends the
`data to a wireless receiver 26 of a receiver board 27 that
`preferably contains all of its components on a single sub
`strate. In accordance with present principles, the link carries
`a frequency which is sufficiently high that the signal on the
`link substantially cannot be received outside the room. Also,
`multimedia may be transmitted in an uncompressed form on
`the link such that so much data is transmitted each second
`that bootlegging the content is essentially untenable,
`although some data compression less preferably may be
`implemented. The data may also be transmitted in com
`pressed form if desired. The transmitter 20 and receiver 26
`(and, hence, the link there between) preferably operate at a
`fixed (unvarying, single-only) frequency of approximately
`sixty Gigahertz (60 GHz), and more preferably in the range
`of 59 GHz—64 GHz, and the link has a data rate, preferably
`fixed, of at least two Gigabits per second (2.0 Gbps). When
`DQPSK is used the data rate may be 2.2 Gbps, and the link
`55
`may have a data rate of approximately 2.5 Gbps. The link
`may have a fixed bandwidth of two and half Gigahertz (2.5
`GHz).
`With this in mind, it may now be appreciated that the
`wireless transmitter 20 preferably includes an encoder for
`encoding in accordance with principles known in the art.
`The data is modulated at approximately 30 GHz by a 30.125
`GHz modulator and up converted by a subharmonic mixer to
`a frequency of approximately 60 GHz for transmission over
`the link 30. Using the above-described wide channel and a
`simpler modulation scheme such as but not limited to
`DQPSK, QPSK, BPSK or 8-PSK, a high data rate yet simple
`
`60
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`65
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`Page 5 of 6
`
`

`

`US 7,020,121 B2
`
`5
`
`10
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`15
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`20
`
`5
`While the particular METHOD AND SYSTEM FOR
`WIRELESS DIGITAL MULTIMEDIA TRANSMISSION
`as herein shown and described in detail is fully capable of
`attaining the above-described objects of the invention, it is
`to be understood that it is the presently preferred embodi
`ment of the present invention and is thus representative of
`the subject matter which is broadly contemplated by the
`present invention, that the scope of the present invention
`fully encompasses other embodiments which may become
`obvious to those skilled in the art, and that the scope of the
`present invention is accordingly to be limited by nothing
`other than the appended claims, in which reference to an
`element in the singular is not intended to mean “one and
`only one” unless explicitly so stated, but rather “one or
`more”. It is not necessary for a device or method to address
`each and every problem sought to be solved by the present
`invention, for it to be encompassed by the present claims.
`Furthermore, no element, component, or method step in the
`present disclosure is intended to be dedicated to the public
`regardless of whether the element, component, or method
`step is explicitly recited in the claims. No claim element
`herein is to be construed under the provisions of 35 U.S.C.
`section 112, sixth paragraph, unless the element is expressly
`recited using the phrase “means for’’ or, in the case of a
`method claim, the element is recited as a “step” instead of
`25
`an “act”. Absent express definitions herein, claim terms are
`to be given all ordinary and accustomed meanings that are
`not irreconcilable with the present specification and file
`history.
`What is claimed is:
`1. A system, comprising:
`a transition minimized differential signaling (TMDS)
`receiver on a first substrate configured for receiving at
`least one of digital visual interface (DVI) data, and
`high definition multi-media (HDMI) data;
`at least one transmitter processor on the first substrate and
`receiving data from the TMDS receiver, the transmitter
`processor being implemented by one of a field pro
`grammable gate array (FPGA), and application specific
`integrated circuit (ASIC);
`at least one wireless transmitter on the first substrate and
`receiving data from the transmitter processor for wire
`less transmission thereof;
`at least one wireless receiver configured to receive data
`from the wireless transmitter;
`at least one receiver processor receiving data from the
`wireless receiver, the receiver processor being imple
`mented by one of a field programmable gate array
`(FPGA), and application specific integrated circuit
`(ASIC); and
`a transition minimized differential signaling (TMDS)
`transmitter configured for receiving data from the
`receiver processor and outputting at least one of DVI,
`and HDMI, input signals to a display.
`2. The system of claim 1, wherein the system does not
`reduce data to a baseband video signal during processing.
`3. The system of claim 1, wherein at least the transmitter
`processor includes phase-locked loop circuitry for clock
`stabilization.
`4. The system of claim 1, wherein at least the transmitter
`processor includes de-jitter circuitry for input data stabili
`zation.
`
`55
`
`6
`5. The system of claim 1, wherein at least the transmitter
`processor applies forward error correction prior to differen
`tial encoding of data.
`6. The system of claim 1, wherein at least the transmitter
`processor outputs I and Q data to the wireless transmitter.
`7. The system of claim 6, wherein the transmitter proces
`sor receives three data TMDS data and 1 TMDS clock
`streams from the TMDS receiver.
`8. A digital video transmitter, comprising:
`a wireless transmitter:
`at least one transmitter processor configured to receive a
`physical signaling stream representing digital video
`data and based thereon, without rendering baseband
`information representing the digital video data, output
`ting a quadrature signal suitable for processing by the
`wireless transmitter; and
`a substrate holding the wireless transmitter and the trans
`mitter processor.
`9. The digital video transmitter of claim 8, wherein the
`processor is an ASIC.
`10. The digital video transmitter of claim 8, wherein the
`processor is an FPGA.
`11. The digital video transmitter of claim 8, wherein the
`transmitter processor includes phase-locked loop circuitry
`for clock stabilization.
`12. The digital video transmitter of claim 8, wherein at
`least the transmitter processor includes de-jitter circuitry for
`input data stabilization.
`13. The digital video transmitter of claim 8, wherein at
`least the transmitter processor applies forward error correc
`tion prior to differential encoding of data.
`14. The digital video transmitter of claim 8, wherein at
`least the quadrature signal is I and Q data and the physical
`signaling stream is 3-data and 1-clock TMDS information,
`and the digital video transmitter further comprises a TMDS
`receiver coupled to the processor.
`15. A digital video receiver, comprising:
`at least one receiver processor configured to receive a
`demodulated quadrature signal and based thereon,
`without rendering baseband information representing
`the digital video data, outputting a physical signaling
`stream representing digital video data;
`a wireless receiver communication with the receiver pro
`cessor; and
`a substrate holding the wireless receiver and the receiver
`processor.
`16. The digital video receiver of claim 15, wherein the
`processor is an ASIC.
`17. The digital video receiver of claim 15, wherein the
`processor is an FPGA.
`18. The digital video receiver of claim 15, wherein at least
`the quadrature signal is I and Q data and the physical
`signaling stream is 3-data and 1-clock TMDS information,
`and the digital video receiver further comprises a TMDS
`receiver coupled to the processor.
`
`30
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`40
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`50
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`Page 6 of 6
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