Digital Visual Interface
`Revision 1. 0
`
`Digital Display Working Group
`
`Digital Visual Interface
`DVI
`
`Revision 1.0
`
`02 April 1999
`
`Page 1 of 76
`
`HTC EXHIBIT 1016
`
`

`

`Dig ital Visual Interface
`Revision 1. 0
`
`Digital Display Working Group
`
`The Digital Display Working Group Promoters (''DDWG Promoters") are Intel Corporation, Silicon Jmage, lnc.,
`Compaq Computer Corporation, Fujitsu Limited, Hewlett-Packard Company, lntemational Business
`Macbines Corporation, and NEC Corporation
`
`TffiS SPECIFICATION IS PROVIDED "AS lS" WJTH NO WARRANTIES WHATSOEVER, INCLUDING ANY
`WARRANTY OF MERCHANTAB[LITY, NONlNFRlNGEMENT, FITNESS FOR ANY PARTICULAR
`PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECWICATION OR
`SAMPLE.
`
`The DDWG Promoters disclaim all liability, including liability for infringement of any proprietary rights, relating to usc
`of information in this sprxilil:ation. No license. express or implied, by estoppel or othetwise, to any intellectual property
`rights is granted herein.
`
`The DDWG Promoters may have patents and/or patent applications related to the Digital Visua//nteJfaoe Specification.
`The DDWG Promoters intend to make available to the industry <Ul Adopter's Agreement that will include a limited.
`reciprocal, royalty-free license to tl1e electrical interfaces. mechanical interfaces. signals, si~:,'llaling and coding protocols,
`and bus protocols described in, and required by, the Digita/11isual Tnte1jace Specfftcation Revision }.() finalized and
`published by the DDWG Promoters. To encourage early adoption. Adopters will be required to retum their executed
`copy of the Adopter's Agreement during an "Adoption Period" which is within one year after the DVl Specification
`Revision 1.0 is first published or within one year after the Adopter first sells products that comply with that
`specification, whichever is later. This Adoption Period requirement will give parties ample time to understand the
`benefits of becoming an Adopter and encourage tl1em to remember this important step.
`
`Copyright © DDWG Promoters l999.
`
`*Third-party br:ands and nan1es are the propeny of their respective owners.
`
`Acknowledgement
`
`The DDWG acknowledges the concerted efforts of employees of Silicon lmage, Inc.
`and Molex Inc., who authored major portions ofthis specification. Both companies
`have made a signjficant contribution by developing and licensing to the industry the
`core technologies upon which this i11dustry specification is based; transition
`minimized differential signaling (T.M.D.S.) technology from Silicon Image, and
`connector teclmology from Molex.
`
`REVISION HISTORY
`
`02 Ap r 99- 1.0 Initial Specification Release
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`Page 2 of 76
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`Digital Visual Interface
`Revision 1.0
`
`Acknowledgement. ..................................................................................................... 2
`
`REVISION HISTORY ................................................................................................... 2
`
`1.
`1.1.
`1.2.
`1.2.1.
`1.2.2.
`1.3.
`1.3.1.
`1.3.2.
`1.3.3.
`1.3.4.
`1.3.5.
`1.3.6.
`1.3.7.
`
`2.
`2.1 .
`2.2.
`2.2.1.
`2.2.2.
`2.2.3.
`2.2.4.
`2.2.5.
`2.2.6.
`2.2.7.
`2.2.8.
`2.2.9.
`2.2.10.
`2.2.11.
`2.2.12.
`2.3.
`2.3.1.
`2.3.2.
`2.4.
`2.4.1.
`2.4.2.
`2.4.3.
`2.5.
`2.5.1.
`2.5.2.
`2.5.3.
`2.5.4.
`2.6.
`3.
`3.1
`3.1.1
`3.1.2
`3.1.3
`3. 1.4
`3.1.5
`3.2
`3.2.1
`
`Introduction ................................................................................................ 5
`Scope and Motivation ..................................................................................... 5
`Performance Scalability ............................................................... ................... 6
`Bandwidth Estimation .................................................................................... 7
`Conversion to Selective Refresh ................................................................... 8
`Related Documents ........................................................................................ 8
`VESA Display Data Channel (DOC) Specification ........................................ 8
`VESA Extended Display Identification Data (ED/D) Specification ................ 8
`VESA Video Signal Standard (VSIS) Specification ....................................... 8
`VESA Monitor Timing Specifications (DMT) ................................................. 9
`VESA Generalized Timing Formula Specification (GTF) .............................. 9
`VESA Timing Definition for LCD Monitors Specification ............................... 9
`Compatibility with Other T.M.D.S. Based Implementations .......................... 9
`Architectural Requirements. ................................................................... 1 0
`T.M.D.S. Overview ........................................................................................ 10
`Plug and Play Specification .......................................................................... 1 0
`Overview ...................................................................................................... 10
`T.M. O.S. Link Usage Model ........................................................................ 11
`High Color Depth Support ........................................................................... 13
`Low Pixel Format Support ........................................................................... 14
`ED/D ............................................................................................................ 14
`DOC ............................................................................................................. 15
`Gamma ........................................................................................................ 15
`Scaling ......................................................................................................... 15
`Hot Plugging ................................................................................................ 16
`HSync, VSync and Data Enable Required .................................................. 17
`Data Formats ............................................................................................... 18
`fnteroperability with Other T.M.D.S. Based Specifications ......................... 18
`Bandwidth ................................... ................................................................. 18
`Minimum Frequency Supported .................................................................. 18
`Alternate Media ............................................................................................ 19
`Digital Monitor Power Management.. ............................................................. 19
`Link Inactivity Definition ............................................................................... 21
`System Power Management Requirements ................................................ 21
`Monitor Power Management Requirements ................................................ 21
`Analog ........................................................................................................... 22
`Analog Signal Quality .................................................................................. 22
`HSync and VSync Required ........................................................................ 22
`Analog Timings ............................................................................................ 22
`Analog Power Management ........................................................................ 23
`Signal List. ................................... ................................................................. 23
`
`T.M.D .. S. Protocol Specification ............................................................. 24
`Overview ............................................................. ......................................... 24
`Link Architecture .......................................................................................... 24
`Clocking ....................................................................................................... 24
`Synchronization ........................................................................................... 25
`Encoding ................................... ................................................................... 25
`Dual-Link Archit.ecture ................................................................................. 25
`Encoder Specification ................................................................................... 26
`Channel Mapping ........................................................................................ 26
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`Digital Visual Interface
`Revision 1. 0
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`3.2.2
`3.2.3
`3.3
`3.3.1
`3.3.2
`3.3.3
`3.3.4
`3.3.5
`3.4
`4.
`4.1 .
`4 .2.
`4 .3.
`4 .4 .
`4.5.
`4.6.
`4 .7.
`4.7.1.
`4.7.2.
`4.7.3.
`4.7.4.
`4.7.5.
`4.7.6.
`4.7.7.
`4.7.8.
`4.7.9.
`4.7.10.
`
`Digital Display Working Group
`Encode Algorithm ..................... ................................................................... 28
`Serialization ................................................................................................. 30
`Decoder Specification ..................................................................................... 30
`Clock Recovery ............................................................................................ 3D
`Data Synchronization .................................................................................... 30
`Decode Algorithm ......................................................................................... 31
`Channel Mapping ......................................................................................... 31
`Error Handling ............................................................................................... 31
`Link Timing Requirements .............................................................................. 32
`T.M.D.S. Electrical Specification ............................................................ 33
`Overview .......................................................................................................... 33
`System Ratings and Operating Conditions ..................................................... 35
`Transmitter Electrical Specifications ............................................................... 35
`Receiver Electrical Specifications ................................................................... 38
`Cable Assembly Specifications ....................................................................... 39
`Jitter Specifications ......................................................................................... 39
`Electrical Measurement Procedures ............................................................... 40
`Test Patterns ... ............................................................................................ 40
`Normalized Amplitudes ................................................................................ 40
`Clock Recovery ............................................................................................ 40
`Transmitter Rise/Fall Time ........................................................................... 41
`Transmitter Skew Measurement.. ................................................................ 41
`Transmitter Eye ........................................................................................... 41
`Jitter Measurement ....................................................................................... 42
`Receiver Eye ................................................................................................ 42
`Receiver Skew Measurement ....................................................................... 42
`Differential TOR Measurement Procedure ................................................. .42
`
`Physical Interconnect Specification ...................................................... 43
`5.
`Overview .......................................................................................................... 43
`5.1.
`Mechanical Characteristics ............................................................................. 43
`5.2.
`Signal Pin Assignments ............................................................................... 43
`5.2.1.
`Contact Sequence ....................................................................................... 44
`5.2.2.
`Digital-Only Receptacle Connectors ............................................................ 45
`5.2.3.
`Combined Analog and Digital Receptacle Connectors ............................... 46
`5.2.4.
`Digital Plug Connectors ................................................................................ 47
`5.2.5.
`Analog Plug Connectors ............................................................................... 47
`5.2.6.
`Recommended Panel Cutout ....................................................................... 48
`5.2.7.
`Mechanical Performance .............................................................................. 49
`5.2.8.
`Electrical Characteristics ................................................................................. 50
`5 .3.
`Connector Electrical Performance ............................................................... 50
`5.3.1.
`Cable Electrical Performance ....................................................................... 52
`5.3.2.
`Environmental Characteristics ........................................................................ 53
`5.4.
`Test Sequences .............................................................................................. 54
`5.5.
`Group 1: Mated Environmental .................................................................... 54
`5.5.1.
`Group II: Mated Mechanical ........................................................................ 55
`5.5.2.
`Group Ill: Mechanical Mate/Unmate Forces ................................................ 56
`5.5.3.
`Group IV: Insulator Integrity ......................................................................... 57
`5.5.4.
`Group V: Cable Flexing ............................................................................... 58
`5.5.5.
`Group VI: Electrostatic Discharge ............................................................... 58
`5.5.6.
`Appendix A. Glossary of Terms ..................................... , ...................................... 59
`
`Appendix B.
`Appendix C.
`
`Contact Geometry ........................................................................ 61
`Digital Monitor Power State- State Diagram .............................. 76
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`Page 4 of 76
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`Digital Visual Interface
`Revision 1. 0
`
`1.
`
`Introduction
`
`Digital Display Working Group
`
`The Digital Visual Interface (hereinafter DYT) specification provides a high-speed digital
`connection for visual data types that is display technology independent. The interface is
`primarily focused at providing a connection between a computer and its display device. The
`DVl specification meets the needs of all segments of the PC industry (workstation, desktop,
`laptop, etc) and will enable these different segments to unite arowud one monitor interface
`specification.
`
`The DVl interface enables:
`I. Content to remain in the lossless digital domain from creation to consumption
`2. Display technology independence
`3. Plug and play through hot plug detection, EDlD and DDC28
`4. Djgital and Analog support in a single connector
`
`This interface specification is organized as follows:
`+ Chapter 1 provides motivation, scope, and direction of the specificatjon.
`• Chapter 2 provides a technical overview and the specific system and display architectural
`and programming requirements that must be met in order to create a11 inter-operable
`context for the DVI i11terface.
`+ Chapter 3 provides a detailed description of the transition minimized differential
`signaling (hereinafter T.M.D.S.) protocol and encoding algorithm.
`+ Chapter 4 provides a detailed description of the electrical requirements ofT.M.D.S ..
`• Chapter 5 contains the connector mechanical description and the electrical characteristics
`of the connector, including signal placement.
`+ A[ppendix A is a glossary.
`• Appendix 8 details the connector contact geometry
`• A[ppendix C enlarged digital monitor power state diagram
`
`1.1. Scope and Motivation
`
`The purpose of this interface specification is to provide an industry specificat ion for a digital
`interface between a personal computing device and a display device. This specification
`provides for a simple low-cost implementation on both the host and monitor while allowing
`for monitor manufacturers and syste m providers to add feature rich values as appropriate for
`their specific application.
`
`The DDWG has worked to address the various business models and requirements of the
`iodusu·y by delivering a transition methodology that addresses the needs of those various
`requirements. This is accomplished by specifying two connectors with identical mechanical
`characteristics: one that is digital only and one that is digital and analog. The combined
`digital and analog connector is designed to meet the needs of systems with special form factor
`or perfom1ance requirements. Having support for the analog and digital interfaces for the
`computer to monitor interconnect wj[[ allow the end user to simply plug the display into the
`DVI connector regardless of the display technology.
`
`The digital only DVI connector is designed to coexist with the standard VGA connector.
`With the combined connector or the digital only connector the opportunity exists for the
`removal of the legacy YGA collllector. The removal of the legacy YGA connector is
`anticipated to be driven strictly by bllsiness demands.
`
`A digital interface for the computer to monitor interconnect has several benefits over the
`standard VGA connector. A digital interface ensures all content transferred over this interface
`
`Page 5 of 76
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`Digital Visual Interface
`Revision 1. 0
`
`Digital Display Working Group
`remains in the lossless digital domain 1iom creation to consumption. The digital interface is
`developed with no assumption made as to the attached display technology.
`
`This specification completely describes the interface so that one could implement a complete
`transmission and interconnect solution or any portion of the interface. The T.M.D.S. protocol
`and associated electrical signaling as developed by Silicon !mage is described in detail. The
`mechanical specification of the connector and the signal placement within the connector are
`described ..
`
`A device that is compliant with this specification is should be interoperable with other
`compliant devices tlu·ough the plug and play configuration and implementation provided for
`in this specification. The plug and play ioterface provides for hot plug detection and monitor
`feature detection. Additionally, this specification describes the number ofT.M.D.S. links
`available to the display device and the method for configuring the T.M.D.S. links.
`
`The bandwidth and pixel formats that are anticipated and supported by this specification are
`described. This specification describes the signal quality characteristics required by the cable
`to support the l1igh data rates required by large pixel format displays. Additionally the DVI
`specification provides for alternate media implementations. Power management and plug and
`play configuration management are both fully described. To ensure baseline functionality,
`low-pixel format requirements are included.
`
`As appropriate, this interface makes use of existing VESA specifications to allow for simple
`low-cost implementations. Specifically VESA Extended Display Identification Data (EDID)
`and Display Data Channel (DOC) specifications are referenced for monitor identification and
`the VESA Monitor Timing Specification (DMT) is referenced for the monitor timings.
`
`1.2. Performance Scalability
`
`The amount of raw bandwidth that is required to support a display type is technology specific.
`For example a typical CRT allocates a blanking interval time. This blanking interval
`requirement is technology specific and forces the data transfer to occw· in a limited time slot.
`This limited time slot increases the bandwidth requirement of the data active window while
`mandating long data inactive time periods to allow for the blanking to complete. A blanking
`period is display technology specific and should not be forced on all display types. Reduced
`blanking periods provide more ofthe actual interconnect bandwidth to the display device. It
`is anticipated that d isplay technology will continue to advance such that blanking period
`overheads will be decreased and will eventually be elimi.nated thus providing the maximum
`bandwidth of the interface to the display device. As displays advance even beyond the
`capabi lities of the copper physical layer it is anticipated display interfaces will migrate toward
`providing only changed data to the display. This limited update architectltre is an expectation
`only, not a requiJement.
`
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`Digital Visual I nt erface
`Revision 1.0
`
`'iii'3
`.0
`~
`.c
`.3 2 Copper Barrier
`:0
`c: co
`Ill
`
`"0
`
`::::::::::::::4:::::: Selective Refresh
`.................................................................................
`::::::::::::::::::::
`.
`
`~1 c: co .c
`
`()
`(I) c;,
`.c:
`i:i)
`
`0
`
`60Hz LCD
`5% blanking
`60Hz CRT
`
`75Hz CRT
`GTF blanking
`
`85Hz CRT
`GTF blanking
`
`.. --...
`GTF blanking ·-· .....-- -x- -
`• •
`..
`• •
`
`Ul
`0
`
`....
`
`0
`0
`
`....
`
`Ul
`0
`
`r.J
`0
`0
`
`w
`w
`r.J
`c.n
`0
`Ul
`0
`0
`0
`Pixel Bandwidth [MPix/sec)
`
`x-
`
`•+
`
`X
`
`I
`
`+--
`
`e--+-
`
`·•
`
`Legend:
`
`Proposed Spec
`-
`--- Future Architecture
`
`• VGA (640x480)
`• SVGA (800x600)
`XGA (1024x768)
`SXGA (1280x1024)
`• UXGA (1600x1200)
`+ HDTV (1920x1080)
`• QXGA (2048x1536)
`
`Figure 1-1. Available Link Bandwidth
`
`Figure 1-L Available Link Bandwidth. represents the raw bandwidth available from each
`T.M.D.S. link. The three horizontal axes across the bottom of the figw·e represent the
`different overhead requirements of the various display technologies. To detem1ine the
`number of links required for a specific application simply use the legend on the right to select
`tbe pixel format, then find the pixel format on the horizontal axis that represents the display
`technology of interest. Once the pixel format has been identified draw a vertical line to
`intersect the T.M.D .S. bandwidth curve, this is the bandwidth required for the pixel format
`and djsplay technology selected.
`
`1.2. 1. Bandwidth Estimation
`
`The bandwidth that is requjred over a physical medium is easy to estimate. Data reqLtired as
`input are Horizontal Pixels, Vertical Pixels, Refresh Frequency (Hz), Bandwidth Overhead
`(loosely defined as blanking). An equation to quickly estimate the bandwidd1 required is:
`
`[ # Horizonta/Pixelsx# Vertica/Pixels x Rate x ( J + %~~~ead)] = Pixeo/secand
`
`Equation 1-1. Pixels per Secoml.
`Where overhead is defined as
`
`Blanking
`ver ea = ___ _..;:;;._
`0
`h d
`1- Blanking
`Eqntllionl-2. 01·erhead.
`
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`Digital Visual Interface
`Revision 1.0
`
`Digital Display Working Group
`To measure the link bandwidth i.n pixels per second assumes each of the three charmels is
`transmitting an R-pel, G-pel, and B-pel data in unison.
`
`A pel is a pixel element, i.e. the singLLiar red value or green value or blue value of an RGB
`pixel. Pixels per second can be converted to bits per second by multiplying the pixels per
`second value by the number of bits per pixel. Using E quation 1-1 and the T.M.D.S. signaling
`protocol, pixels per second equals tbe T.M.D.S. clock link frequency.
`
`1.2.2. Conversion to Selective Refresh
`
`It is anticipated that in the future the refreshing of the screen will become a function of the
`monitor. Only when data has changed will the data be sent to the monitor. A monitor would
`bave to employ an addressable memory space to enable this feature. With a selective refresh
`interface, the high refresh rates required to keep a monitor ergonomically pleasing can be
`maintained while not requiring an artificially high data rate between the graphics controller
`and tbe monitor. The DVI specification does nothing to preclude this potential migration.
`
`1.3. Related Documents
`
`The DVI specificadon references other VESA specifications to enable low cost
`implementations. Additionally, the DVJ specification references the VESA specifications to
`help enable plug and play interoperability.
`
`1.3.1. VESA Display Data Channel (DOC) Specification
`
`This specification incorporates a subset of the Display Data Channel for operation between a
`DDC compliant host and DDC compliant monitor. The DDC level support required in this
`specification is DDC2B. Compatibility with earlier DDC versions is not supported. l t is
`anticipated that the DVI specification will require support for the Enhanced-DOC
`specification within 12 months of VESA adoption. Refer to VESA DOC Specifica.tion
`Version 3.0 for more information.
`
`1.3.2. VESA Extended Display Identification Data (EDID) Specification
`
`Both DVl compliant systems and monitors must support the EDID data shlJCture. EDID 1.2
`and 2.0 are recommended for interim support for systems. Complete requirements are
`detailed in section 2.2.5. The system is required to read the EDID data structure to determine
`the capabilities supported by the monitor. It is anticipated that the DVl specification will
`require support for the EDID J .3 data structw·e support within 12 months ofVESA adoption.
`Refer to VESA EDID Specification Version 3.0 for more information.
`
`1.3.3. VESA Video Signal Standard (VSIS) Specification
`
`Systems implementing the analog portion of the DVI specification must be in compliance
`with the VESA VSJS specification within 12 months ofVESA adoption. Refer to VESA
`VSIS Specification Version 1.6p for more informatio n.
`
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`Digital Visual Interface
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`1.3.4. VESA Monitor Timing Specifications (DMT)
`
`Systems implementing the analog portion of tbe DVl specification should be in compliance
`with the VESA and Industry Standards and Guidelines for Computer Display Monitor
`Timings specification. Refer to VESA and lndustry Standards and Guidelines for Computer
`Display Monitor Timings Version 1.0 Revision 0.8 for more infom1ation
`
`1.3.5. VESA Generalized Timing Formula Specification (GTF)
`
`Systems implementing the analog portion of the DVI specification should be in compliance
`with the VESA Generabzcd Timing Fommla Specification. Refer to VESA Generalized
`Timing Formula Specificatio n Version l.O Revision 1.0 for more information.
`
`1.3.6. VESA Timing Definition for LCD Monitors Specification
`
`LCD monitors should be in compliance with the VESA Timing Definition for LCD Monitor
`Specification. Refer to VESA Timing Definition for LCD Monitor Specification Version I
`Draft 8 for more information.
`
`1.3.7. Compatibility with Other T.M.D.S. Based Implementations.
`
`The DVI specification is based on a T.M.O.S. electrical layer. Every effo1t has been made to
`ensure interoperabi lity with existing p roducts that support similarT.M.D.S. signaling.
`[mplementations ofVESA DFP or VESA P&D specification should connect to the DVI
`specified coru1ector through a simple adapter.
`
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`Digital Visual Interface
`Revision 1.0
`
`2. Architectural Requirements
`
`2.1. T.M.D.S. Overview
`
`The Digital Visual Interface uses transition minimized differential signaling for the base
`electrical interconnection. The T.M .D.S. link is used to send grapllics data to the monitor.
`The transition minimization is achieved by implementing an advanced encoding algoritlun
`that conve-tts 8 bits of data into a 1 O-bit transition minimized, DC balanced character.
`
`This interface specification allows for two T.M.D.S. links enabling large pixel format digital
`display devices, see Figure 2-1. One or two T.M.D.S. links are available depending on the
`pixel format and timings desired. The two T.M.D.S. links share the same clock allowing the
`bandwidth to be evenly divided between the two links. As the capabilities of the monitor are
`determined the system will choose to enable one or both T.M.D.S. links.
`_____ A ___ ~
`T.M.D .S. Links
`)
`(
`
`Graphics
`Controller
`
`Pixel Data
`
`Control
`
`Data Channel 1
`
`Data Channel 2
`
`~Qat~~h_gnnel_3 __
`
`~.-Data Channel 4 _
`
`Data Channel 5
`
`Pixel Data
`
`Control
`
`Display
`Controller
`
`Figure 2-1. T.M.D.S. l,ogical Links
`
`The transmitter incorporates an advanced coding algorithm to enable T.M.D.S. signaling for
`reduced EM I across copper cables and DC-balancing for data transmission over fiber optic
`cables. ln addition, d1e advanced coding algorithm enables robust clock recovery at the
`receiver to achieve high-skew tolerance for driving longer cable lengths as well as shorter low
`cost cables.
`
`2.2. Plug and Play Specification
`
`2.2.1. Overview
`
`On initial system boot a YGA compliant device might be assumed by the graphics controller.
`To accommodate system boot modes and debug modes, the DVI compliant monitor must
`support the low pixel format mode defined in section 2.2.4.2. Both BIOS POST and the
`operating system are likely to query the monitor using the DDC2B protocol to determine what
`pixel formats and interface is supported. DVl makes use of the EDID data structure for tbe
`identification of the monitor type and capabilities. The combination of pixel formats
`supported by the monitor, pixel fon11ats supported by the graphics subsystem, and user input
`will detennine what pixel format to display.
`
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`Digital Visual Interface
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`
`Digital Display Working Group
`DVI provides for single or dual T.M.D.S. link implementations. The single Link can supp011
`greater than high definition television (HDTV) pixel formats at a reduced blanking interval.
`The dual Link configuration is intended to provide support for the higher bandwidth demands
`of displays that do not support reduced blanking. The dual link configuration will enable
`support for large pixel format digital CRTs; the dual link is not limited to large pixel format
`digital CRT support. Digital CRTs are envisioned to be similar to classical CRTs except the
`graphi·cal data received by the display transducer is in the digital domain with the final digital
`to analog conversion occurring in the monitor. Digital CRTs require time to be allocated to
`horizontal and vertical retrace intervals. For a CRT to display the same pixel fonnat as a
`reduced blanking Flat Panel monitor, the retrace time a llocation places a high peak bandwidth
`requirement on the graphics subsystem. The higher bandwidth requirement of the digital
`CRTs is achieved by using two T.M .D.S. links. With the use oftbe second link and today's
`technology transmitter, a digital CRT that is compliant with VESA 's Generalized Timing
`Formula (GTF) can support pixel for mats of greater than 2.75 million pixels at an 85Hz
`refresh rate. A display device that slllpports reduced blankings and refi·esh rates can easily
`support more than 5 million pixels with two T.M.D.S. links.
`
`On initial system boot, if a digital monitor is detected, only the primary T.M.D.S. link can be
`activated. The secondary T.M.D.S. link can become active after the graphics controller driver
`has determiJ1ed the capability for the second link e!lists in the monitor. The two T.M.O.S.
`links share the same clock allowing the bandwidth to be evenly divided between the two
`links. lf an analog DVI compliant monitor is attached to the system, the system should treat
`the analog DVI compliant monitor a s it would a analog monitor connected ro the 15 pin VGA
`connector.
`
`If the DV1 compliant monitor was not present during the boot process, the Hot Plug Detection
`mechanism exists to allow the system to determine when a DVI compliant monitor has been
`plugged in. After the Hot Plug-IJ1 event the system will query the monitor using the DDC2B
`interface and enable the T.M.D.S. link if required.
`
`After the pixel format and timings have been detenuined there are two more parameters that
`effect the user perception of the picture quality, gamma and scaling.
`
`The gamma characteristic of a monitor is display teclmology dependent. ln the past a CRT
`has been assumed as the primary display technology to be used. To ensure display
`independence, no assumption is made of display technology. The DVI requires a gamma
`characteristic of the data at the interface allowing monitors of varying display technologies to
`compensate for their specific display tr