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`US006165826A
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`[11]
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`[45]
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`Patent Number:
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`Date of Patent:
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`6,165,826
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`*Dec. 26, 2000
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`Kunishima el al.
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`Ildereni et al.
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`.................
`Sato et al.
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`.............
`Ozturk et al.
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`Fujii et al.
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`Sitaram et al.
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`Yoo et al.
`..
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`Beyer et al.
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`437/200
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`.. 437/41
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`. 437/44
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`257/192
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`257/19
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`257/377
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`437/200
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`. 437/44
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`257/383
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`437/89
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`11/1992
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`12/1992
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`7/1993
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`2/1994
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`8/1994
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`8/1994
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`10/1994
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`2/1995
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`3/1995
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`4/1995
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`5,162,263
`5,168,072
`5,231,042
`5,285,088
`5,336,903
`5,341,014
`5,352,631
`5,393,685
`5,397,909
`5,405,795
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`(List continued on next page.)
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`FOREIGN PATENT DOCUMENTS
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`5/1998 European Pat. Off. .
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`Japan .......................... .. 438/FOR 168
`3/1986
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`8448061
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`36 1 05 1959
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`Primary Examiner—Long Pham
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`Atmmey, Agent, or Firm—Blakely, Sokoloff, Taylor &
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`Zafman LLP
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`[57]
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`ABSTRACT
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`A novel transistor with a low resistance ultra shallow tip
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`region and its method of fabrication in a complementary
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`metal oxide semiconductor (CMOS) process. According to
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`the preferred method of the present invention, a first gate
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`dielectric and a first gate electrode are formed on a first
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`portion of a semiconductor substrate having a first conduc-
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`tivity type, and a second gate dielectric and a said gate
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`electrode are formed on a second portion of semiconductor
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`substrate having a second conductivity type. Asilicon nitride
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`layer is formed over the first portion of the semiconductor
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`substrate including the first gate electrode and over the
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`second portion of the semiconductor substrate including the
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`second gate electrode. The silicon nitride layer is removed
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`from the second portion of the silicon substrate and from the
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`top of the second gate electrode to thereby form a first pair
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`of silicon nitride spacers adjacent to opposite sides of the
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`second gate electrode. Apair of recesses are then formed in
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`the second portion of the semiconductor substrate in align-
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`ment with the first pair of sidewall spacers. A selectively
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`deposited semiconductor material
`is then formed in the
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`recesses.
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`52 Claims, 13 Drawing Sheets
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`United States Patent
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`[19]
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`Chau et al.
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`[54]
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`[75]
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`TRANSISTOR WITH LOW RESISTANCE TIP
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`AND METHOD OF FABRICATION IN A
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`CMOS PROCESS
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`Inventors: Robert S. Chau, Beaverton;
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`Chia-Hong Jan, Portland; Chan-Hong
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`Chern, Portland; Leopoldo D. Yau,
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`Portland, all of Oreg.
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`Assignee:
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`Intel Corporation, Santa Clara, Calif.
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`N0tiC6Z
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`This patent issued on a continued pros-
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`ecution application filed under 37 CFR
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`1.53(d), and is subject to the twenty year
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`patent
`term provisions of 35 U.S.C.
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`154(a)(2).
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`Appl. No.: 08/581,243
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`Filed:
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`Dec. 29, 1995
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`Related U.S. Application Data
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`Continuation—in—part of application No. 08/363,749, Dec.
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`23, 1994, Pat. No. 5,710,450.
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`Int. Cl.7 ............................................... .. H01L 21/8238
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`U.S. Cl.
`........................ .. 438/231; 438/226; 438/233;
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`438/232; 438/305; 438/306; 438/586; 438/589;
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`438/576; 438/558; 438/561; 438/664
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`Field of Search ................................... .. 438/589-663,
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`438/664, 191, 226-223, 229, 230, 231,
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`232, 259, 270, 330, 301, 303, 305, 306,
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`586, 576, 558, 565, 581, 583, FOR 168,
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`FOR 180, FOR 197, FOR 216, FOR 217,
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`FOR 218, FOR 251, FOR 250, FOR 219;
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`148/DIG. 147, DIG. 19, DIG. 59; 257/288,
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`900
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`References Cited
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`U.S. PATENT DOCUMENTS
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`
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`Maclver et al.
`....................... ,. 148/1.5
`1/1979
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`8/1987
`Naguib et al.
`.......................... .. 437/41
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`10/1989
`Pfiester ....... ..
`437/34
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`3/1991
`Rodder et al.
`357/23.1
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`4/1991
`De Jong et al.
`437/31
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`4,133,704
`4,683,645
`4,876,213
`4,998,150
`5,006,476
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`'oio;'o:'o.."o.
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`TSMC Exhibit 1013
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`Page 1 of 29
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`6,165,826
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`........................ .. 438/301
`4/1997 Hwang et al.
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`............................. 257/344
`1/1998 Chau etal.
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`3/1998 Segawa 6‘ a1~
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`6/1998 Chen etal.
`........................... .. 438/305
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`5,620,912
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`5,710,450
`5926971
`5,770,507
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`U.S. PATENT DOCUMENTS
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`5,478,776
`12/1995 Luflman em. ......................N 4377163
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`5,538,909
`7/1996 Hsu .......... ..
`437/35
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`5,569,624 10/1996 Weiner .................................. .. 437/200
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`U.S. Patent
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`Dec. 26,2000
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`Sheet 1 of 13
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`6,165,826
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`FIG. 1 (PRIOR ART)
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`U.S. Patent
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`Dec. 26,2000
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`Sheet 2 of 13
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`6,165,826
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`N.9".
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`_..__.._E_.__.__.._H
`.,.u.aw..
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`U.S. Patent
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`Dec. 26,2000
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`Sheet 3 of 13
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`Sheet 4 of 13
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`6,165,826
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`FIG. 4C
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`Sheet 7 of 13
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`6,165,826
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`FIG. 5A
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`FIG. 5C
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`Page 10 of 29
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`Sheet 9 of 13
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`U.S. Patent
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`Dec. 26,2000
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`Sheet 10 of 13
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`6,165,826
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` 3111115Ila30’~.
`7111111..
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`§II|§
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`IIIII*‘—"'*IIIII
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`|E2F;IIIl*"—~Il II
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`FIG. 6C
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`Page 12 of 29
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`Page 12 of 29
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`U.S. Patent
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`Dec. 26, 2000
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`Sheet 11 of 13
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`6,165,826
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`FIG. 6D
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`Page 13 of 29
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`U.S. Patent
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`Dec. 26,2000
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`Sheet 12 0f 13
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`6,165,826
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`FIG. 7A
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`FIG. 7B
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`FIG. 7C
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`Page 14 of 29
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`FIG. 7F
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`Page 15 of 29
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`Page 15 of 29
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`6,165,826
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`1
`TRANSISTOR WITH LOW RESISTANCE TIP
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`AND METHOD OF FABRICATION IN A
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`CMOS PROCESS
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`This application is a Continuation-in-Part of U.S. patent
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`application Ser. No. 08/363,749, filed Dec. 23, 1994 now
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`U.S. Pat. No. 5,710,450 and assigned to the present
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`Assignee.
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
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`The present invention relates to the field of semiconductor
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`integrated circuits, and more specifically, to the ultra large-
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`scale fabrication of submicron transistors.
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`2. Discussion of Relates Art
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`transistors are
`Today literally millions of individual
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`coupled together to form very large-scale integrated (VLSI)
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`circuits, such as microprocessors, memories, and applica-
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`tions specific integrated circuits (ICs). Presently, the most
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`advanced ICs are made up of approximately three million
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`transistors, such as metal oxide semiconductor (MOS) field
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`effect transistors having gate lengths on the order of 0.5 gm.
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`In order to continue to increase the complexity and compu-
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`tational power of future integrated circuits, more transistors
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`must be packed into a single IC (i.e., transistor density must
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`increase). Thus, future ultra large-scale integrated (ULSI)
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`circuits will require very short channel
`transistors with
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`effective gate lengths less than 0.1 gm. Unfortunately, the
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`structure and method of fabrication of conventional MOS
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`transistors cannot be simply “scaled down” to produce
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`smaller transistors for higher density integration.
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`The structure of a conventional MOS transistor 100 is
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`shown in FIG. 1. Transistor 100 comprises a gate electrode
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`102, typically polysilicon, formed on a gate dielectric layer
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`104 which in turn is formed on a silicon substrate 106. Apair
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`of source/drain extensions or tip regions 110 are formed in
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`the top surface of substrate 106 in alignment with outside
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`edges of gate electrode 102. Tip regions 110 are typically
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`formed by well-known ion implantation techniques and
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`extend beneath gate electrode 102. Formed adjacent
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`opposite sides of gate electrode 102 and over tip regions 110
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`are a pair of sidewall spacers 108. A pair of source/drain
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`regions 120 are then formed, by ion implantation, in sub-
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`strate 106 substantially in alignment with the outside edges
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`of sidewall spacers 108.
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`order to fabricate a smaller transistor, the depth at which tip
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`region 110 extends into substrate 106 must also be scaled
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`characteristics of the fabricated transistor. Unfortunately, the
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`length of tip region 110, however, must be larger than 0.07
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`pm to insure that the later, heavy dose, deep source/drain
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`implant does not swamp and overwhelm tip region 110.
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`in the fabrication of a small scale transistor with
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`conventional methods, as shown in FIG. 1, the tip region 110
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`is both shallow and long. Because tip region 110 is both
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`shallow and long, tip region 110 exhibits substantial para-
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`(reduces) the transistors drive current.
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`Thus, what is needed is a novel transistor with a low
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`resistance ultra shallow tip region with a VLSI manufactur-
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`able method of fabrication in a CMOS process.
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`SUMMARY OF THE INVENTION
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`A novel transistor with a low resistance ultra shallow tip
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`region and its method of fabrication in a complementary
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`2
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`metal oxide semiconductor process (CMOS) is described.
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`According to a preferred method of the present invention, a
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`first gate dielectric and a first gate electrode are formed on
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`a first portion of a semiconductor substrate having a first
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`conductivity type, and a second gate dielectric and a second
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`gate electrode are formed on a second portion of a semi-
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`conductor substrate having a second conductivity type.
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`Next, ions of a second conductivity type are implanted into
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`the first portion of the semiconductor substrate in alignment
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`with the outside edges of the first gate electrode. A silicon
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`nitride layer is then formed over the first portion of the
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`semiconductor substrate including the first gate electrode
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`and over the second portion of the semiconductor substrate
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`including the second gate electrode. The silicon nitride layer
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`is then removed from the second portion of the silicon
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`substrate and from the top of the second gate electrode to
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`thereby form a first pair of silicon nitride spacers adjacent to
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`opposite sides of the second gate electrode. A pair of
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`recesses are then formed in the second portion of the
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`semiconductor substrate in alignment with the first pair of
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`silicon nitride spacers. A selectively deposited semiconduc-
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`tor material is then formed in the recesses. Dopants are then
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`diffused from the selectively deposited semiconductor mate-
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`rial into the substrate beneath the first pair of silicon nitride
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`spacers. Next, a first pair of sidewall spacers are formed
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`adjacent to opposite sides of the first gate electrode and a
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`second pair of sidewall spacers are formed on the deposited
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`semiconductor material adjacent to the outside edge of the
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`first pair of silicon nitride spacers. Ions of a second con-
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`ductivity type are then implanted into the first portion of the
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`semiconductor substrate in alignment with the outside edges
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`of the first pair of sidewall spacers adjacent to the first gate
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`electrode to thereby form a first pair of source/drain contact
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`regions in the first portion of the semiconductor substrate.
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`Silicide is then formed on the source/drain contact regions
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`and on the first gate electrode and on the deposited semi-
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`conductor material in alignment with the outside edges of
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`the second pair of sidewall spacers are on the second gate
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`electrode.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIG. 1 is an illustration of a cross-sectional view of a
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`conventional transistor.
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`FIG. 2 is an illustration of a cross-sectional view of a low
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`resistance ultra shallow tip transistor of the present inven-
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`tion.
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`FIG. 3a is an illustration of a cross-sectional view of the
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`formation of a first gate electrode on a p-well and the
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`formation of a second gate electrode on a n-well.
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`FIG. 3b is an illustration of a cross-sectional view of the
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`formation of a N— tip region in the p-well in alignment with
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`opposite sidewalls of the first gate electrode of the substrate
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`of FIG. 3a.
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`FIG. 3c is an illustration of a cross-sectional view of the
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`formation of a silicon nitride layer over the substrate of FIG.
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`3b.
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`FIG. 3d is an illustration of a cross-sectional view show-
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`ing the formation of a first pair of sidewall spacers on
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`opposite sides of a gate electrode formed on a substrate and
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`the formation of recess regions in the n-well of the substrate
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`of FIG. 3c.
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`FIG. 36 is an illustration of a cross-sectional view show-
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`ing the deposition of semiconductor material on the sub-
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`strate of FIG. 3d.
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`FIG. 3f is an illustration of a cross-sectional view showing
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`the formation of an oxide layer and a silicon nitride layer
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`over the substrate of FIG. 36.
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`Page 16 of 29
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`3
`FIG. 3g is an illustration of a cross-sectional view show-
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`ing the formation of a first pair of sidewall spacers adjacent
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`to the first gate electrode and a second pair of sidewall
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`spacers adjacent to the first pair of silicon nitride spacers on
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`the substrate of FIG. 3f.
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`FIG. 3k is an illustration of a cross-sectional view show-
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`ing the formation of silicide in the source/drain contact
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`regions and on the deposited semiconductor material of FIG.
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`3g.
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`FIG. 4a is an illustration of a cross-sectional view show-
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`ing the formation of a boron doped glass layer and the
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`formation of N— tip regions in the substrate of FIG. 3a.
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`FIG. 4b is an illustration of a cross-sectional view show-
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`ing the formation of a silicon nitride layer over the substrate
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`of FIG. 4a.
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`FIG. 4c is an illustration of a cross-sectional view show-
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`ing the formation of a first pair of composite sidewall
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`spacers adjacent to the gate electrode over the n-well of the
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`substrate of FIG. 4b.
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`FIG. 4d is an illustration of a cross-sectional view show-
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`ing the formation of semiconductor material on the substrate
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`of FIG. 4c.
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`FIG. 4e is an illustration of a cross-sectional view show-
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`ing the formation of a first pair of spacers adjacent to the gate
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`electrode formed over the p-well and the formation of a
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`second pair of spacers adjacent to the first pair of composite
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`spacers formed adjacent to the gate electrode over the n-well
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`of the substrate of FIG. 4d.
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`FIG. 4f is an illustration of a cross-sectional view showing
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`the out diffusion of impurities from deposited semiconductor
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`material and the formation of silicide on the substrate of
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`FIG. 4e.
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`FIG. 5a is an illustration of a cross-sectional view show-
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`ing the formation of a silicon nitride layer over the substrate
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`of FIG. 3a.
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`FIG. 5b is an illustration of a cross-sectional view show-
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`ing the formation of spacers and recesses on the substrate of
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`FIG. 5a.
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`FIG. 5c is an illustration of a cross-sectional view show-
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`ing the masking of the n-well and the formation of semi-
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`conductor material on the p-well of the substrate of FIG. 5b.
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`FIG. 5d is an illustration of a cross-sectional view show-
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`ing the formation of a mask over the p-well and the
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`formation of semiconductor material on the n-well of the
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`substrate of FIG. 5c.
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`FIG. Se is an illustration of a cross-sectional view show-
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`ing the formation of a thin oxide layer and the formation of
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`a thicker silicon nitride layer over the substrate of FIG. 5a’.
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`FIG. 5f is an illustration of a cross-sectional view showing
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`the formation of a second pair of spacers and the out
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`diffusion of dopants from semiconductor material on the
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`substrate of FIG. 5e.
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`FIG. 6a is an illustration of a cross-sectional view show-
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`ing the formation of p-type semiconductor material on a
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`n-well, and the formation of undoped semiconductor mate-
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`rial on a p-well of a substrate.
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`FIG. 6b is an illustration of a cross-sectional view show-
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`ing the formation of a mask and the ion implantation of the
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`substrate of FIG. 6a.
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`FIG. 6c is an illustration of a cross-sectional view show-
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`ing the formation of sidewall spacers and the implantation of
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`the substrate of FIG. 6b.
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`FIG. 6a’ is an illustration of a cross-sectional view show-
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`ing the diffusion of impurities from semiconductor material
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`and the formation of silicide of the substrate of FIG. 6c.
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`65
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`Page 17 of 29
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`4
`FIG. 7a is an illustration of a cross-sectional view show-
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`ing the formation and patterning of a boron doped glass layer
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`on the substrate of FIG. 3a.
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`FIG. 7b is an illustration of a cross-sectional view show-
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`ing the formation of a silicon nitride layer over the substrate
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`of FIG. 7a.
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`FIG. 7c is an illustration of a cross-sectional view show-
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`ing the formation of spacers and recesses in the substrate of
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`FIG. 7b.
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`FIG. 7a’ is an illustration of a cross-sectional view show-
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`ing the formation of semiconductor material over the sub-
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`strate of FIG. 7c.
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`FIG. 7e is an illustration of a cross-sectional view show-
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`ing the formation of a second pair of spacers over the
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`substrate of FIG. 7d.
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`FIG. 7f is an illustration of a cross-sectional view showing
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`the out diffusion of impurities from deposited semiconductor
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`material and the formation of silicide on the substrate of
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`FIG. 7e.
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`DETAILED DESCRIPTION OF THE PRESENT
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`INVENTION
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`A novel transistor with a low resistance ultra shallow tip
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`and its method of fabrication in a complementary metal
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`oxide semiconductor (CMOS) process is described. In the
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`following description numerous specific details are set forth,
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`such as specific materials, dimensions, and processes, etc.,
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`in order to provide a thorough understanding of the present
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`invention. It will be obvious, however, to one skilled in the
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`that
`the invention may be practiced without
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`art,
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`specific details. In other instances, well-known semiconduc-
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`tor equipment and processes have not been described in
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`particular detail in order to avoid unnecessarily obscuring
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`the present invention.
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`A preferred embodiment of a novel transistor 200 with
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`low resistivity, ultra shallow tip of the present invention is
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`shown in FIG. 2. Transistor 200 is formed on a silicon
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`substrate or well 201. A gate dielectric layer 202 is formed
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`on a surface 203 of substrate 201 and a gate electrode 204
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`is in turn formed on gate dielectric layer 202. A first pair of
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`thin sidewall spacers 206 are formed on opposite sides of
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`gate electrode 204 (spacers 206 run along the “width” of
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`gate electrode 204). Transistor 200 also includes a second
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`pair of substantially thicker sidewall spacers 208 formed
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`adjacent to the outside edges of the first pair of sidewall
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`spacers 206. Transistor 200 includes a pair of source/drain
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`regions 211 each comprising a pair of tips or source/drain
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`extensions 210 and a source/drain contact region 212.
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`Tip or source/drain extension 210 is defined as the source/
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`drain region located beneath second sidewall spacer 208,
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`first sidewall spacer 206, and the outside edge of gate
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`electrode 204. Tip 210 comprises an ultra shallow tip portion
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`214 and a raised tip portion 216. Ultra shallow tip portion
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`214 is comprised of a doped semiconductor substrate 215
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`formed by “out diffusing” dopants from selectively depos-
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`ited semiconductor material 217 into substrate 201. Ultra
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`shallow tip 214 extends from beneath first sidewall spacer
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`206 to the outside edges of gate electrode 204. Ultra shallow
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`tip 214 preferably extends at least 100 A beneath (laterally)
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`gate electrode 204 and preferably 500 A for a transistor with
`an effective gate length of approximately 0.10 microns (or
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`1000
`and a drawn gate length of 0.2 gm. Additionally,
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`ultra shallow tip 214 preferably extends less than 1000 A
`deep into substrate 201 beneath substrate surface 203 for a
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`0.10 pm effective gate length. It is to be appreciated that
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`because novel methods of fabrication are employed in the
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`Page 17 of 29
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`6,165,826
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`5
`present invention, ultra shallow tip 214 can be characterized
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`by a very abrupt junction.
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`Tip 210 of transistor 200 also includes a raised tip portion
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`216. Raised tip portion 216 is located beneath second
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`sidewall spacer 208 and is adjacent to the outside edges of
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`first sidewall spacer 206. Raised tip 216 is preferably formed
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`of doped semiconductor material 217 selectively deposited
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`both above and below surface 203 of semiconductor sub-
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`strate 201. Raised tip portion 216 also includes a portion 215
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`doped by “out diffusing” dopants from selectively deposited
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`semiconductor material 217 into substrate 201. Because a
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`portion of raised tip 216 is formed above semiconductor
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`substrate surface 203, raised tip 216 is said to be “raised”. A
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`raised tip significantly reduces the parasitic resistance of
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`transistor 200 and thereby improves its performance.
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`A pair of source/drain contact regions 212 are formed
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`adjacent to the outside edge of second sidewall spacer 208.
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`Source/drain contact regions 212 comprise selectively
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`deposited semiconductor material 217 and “out diffused”
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`doped semiconductor substrate 215. Source/drain contact
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`regions 212 are partially raised source/drain regions. Silicide
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`218 is preferably formed on source/drain regions 212 in
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`order to reduce the contact resistance of transistor 200.
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`Additionally, according to the present invention, first semi-
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`conductor material 217 is preferably deposited onto the top
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`surface of gate electrode 204. Silicide 218 is also preferably
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`formed on deposited semiconductor material 217 on gate
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`electrode 204 to help improve contact resistance.
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`Additionally, if desired, source/drain contact regions 212
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`can be made into deep junction source/drain contacts by ion
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`implanting or diffusing additional dopants into a region 220
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`in substrate 201 in alignment with the outside edges of
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`second sidewall spacers 208.
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`It is to be appreciated that a valuable feature of the present
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`invention is the fact that transistor 200 includes a tip or
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`source/drain extension 210 which is both ultra shallow and
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`raised. In this way, transistor 200 has a shallow tip with a
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`very low parasitic resistance. The novel structure of tran-
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`sistor 200 allows for tip scaling necessary for the fabrication
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`of transistor 200 with effective gate length less than 0.12 gm.
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`Because of the novel
`tip structure 210 of the present
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`invention,
`transistor 200 has good punchthrough perfor-
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`mance and reduced VT roll-off. Additionally, because of tip
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`210, transistor 200 has a low parasitic resistance, resulting in
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`good drive current.
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`The present invention describes several methods of inte-
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`grating the fabrication of a transistor with a low resistance
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`ultra shallow tip into a CMOS process (i.e. into a process
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`where both n-type and p-type transistors are formed).
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`According to a first preferred method of the present
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`invention, as illustrated in FIGS. 3a—3h, a PMOS transistor
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`having a low resistance ultra shallow tip is fabricated with
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`a conventional NMOS transisto