[56]
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`United States Patent
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`Nagasawa et al.
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`[191
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`[54] METHOD FOR MANUFACTURING
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`COMPLEMENTARY INSULATED GATE
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`FIELD EFFECT TRANSISTORS
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`[75]
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`Inventors: Kouichi Nagasawa, Kunitachi;
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`Yzisunobn Kosa; Satoshi Meguro,
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`both of Kodaira, all of Japan
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`[73] Assignee: Hitachi, Ltd., Japan
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`[21] Appl. No.: 756,711
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`Jan. 4, 1977
`[22] Filed:
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`[30]
`Foreign Application Priority Data
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`Jan. 12, 1976 [JP]
`Japan .................................... 51-2057
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`Int. c1.2 .............................................. 1301.1 17/00
`[51]
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`[52] U.S. c1. .......................... .. 29/571
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`[53] Field of Search .................... .. 29/571; 357/23, 41,
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`357/42, so
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`8 Claims, 6 Drawing Figures
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`Page 1 of 7
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`[11]
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`[45]
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`4,110,899
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`Sep. 5, 1978
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`References Cited
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`U.S. PATENT DOCUMENTS
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`3,913,211
`............................ 29/571
`10/1975
`Seeds et al.
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`Spadea .......
`3,983,620
`10/1976
`29/571
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`6/1977 Deal et al. ............................ .. 29/571
`4,027,380
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`Primary Examiner--Gerald A. Dost
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`Attorney, Agent, or Firm—Craig & Antonelli
`
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`ABSTRACI‘
`[57]
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`Method for manufacturing complementary insulated
`gate field effect transistors of LOCOS (local oxidation
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`of silicon) structure wherein after the formation of a
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`well layer, an impurity having higher doping level than
`and the same conductivity type as a semiconductor
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`substrate (well layer) is ion implanted at an area in the
`semiconductor substrate on which a field oxide layer is
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`to be formed using a silicon nitride layer as a mask, and
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`the semiconductor substrate surface is selectively ther-
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`mally oxidized using the silicon nitride layer as a mask.
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`Page 1 of 7
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`TSMC Exhibit 1006
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`US. Patent
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`Sept. 5,1978
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`Sheetl of 2
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`4,110,899
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`U. S. Patent
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`Sept. 5,1978
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`Sheet2 on
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`4,110,899 A
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`Page 3 of 7
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`Page 3 of 7
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`1
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`4,110,899
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`2
`the technique disclosed therein, particularly in the right
`column on page 20 and FIG. 2 on page 21, the P-type
`well layer is formed by ion implantation technology
`after the formation of the LOCOS oxide (field oxide)
`layer. Therefore, while the parastic channel
`is not
`readily formed, a complex design of layout for the MOS
`FET’s and the wiring layers therefor is required when a
`plurality of MOS FET’s are to be incorporated in the
`P-type well layer because LOCOS oxides cannot be
`formed in the P-type well layer. The operating voltage
`is also limited. That is, according to the disclosed tech-
`nique, the operating supply voltage should be up to
`about 10 volts because as the operating voltage rises, the
`area immediately beneath the LOCOS oxide formed in
`the semiconductor body is more apt to form a parastic
`channel by a wiring layer extending over the LOCOS
`oxide layer although the above area is made more N-
`type conductive by sodium (+) ions present in the
`LOCOS oxide. Furthermore, due to the threshold volt-
`age V,,, of the active region in the P-type well layer, it
`becomes impossible to prevent the formation of the
`parastic channel in the P-type well as the operating
`. voltage rises. Accordingly, the field of application of
`25
`the semiconductor integrated circuit device manufac- ._
`tured by the disclosed technique is
`On the other hand, the field of application of the
`semiconductor integrated circuit device comprising
`CMIS FET’s is wide in these days and, actually, the
`operating voltage therefor varies widely depending on
`the specification of a particular product. It is, therefor,
`required to manufacture CMIS FET’s applicable to a
`variety of products of various specifications in a com-
`mon process and provide CMIS FET’s which are satis-
`factorily operable with a wide range of operating volt-
`ages. To this end, a method for manufacturing CMIS
`FET’s which can control the threshold voltage V,,, of
`the active region of the CMIS FET’s and the threshold
`voltage V,,, of the parastic MOS FET to predetermined
`voltages is required.
`SUMMARY OF THE INVENTION
`
`METHOD FOR MANUFACTURING
`COMPLEMENTARY INSULATED GATE FIELD
`EFFECT TRANSISTORS
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to a method for manu-
`facturing complementary insulated gate field effect
`transistors (hereinafter referred to as CMIS FET’s)
`having a field oxide layer of LOCOS (local oxidation of
`silicon) structure, and more particularly to a method for
`manufacturing a semiconductor integrated circuit de-
`vice comprising such transistors.
`2. Description of the Prior Art
`In prior art CMIS FET’s of the LOCOS structure, a
`power supply voltage therefor is determined by a
`threshold voltage V,;, of an active region which is a
`channel region immediately beneath a gate electrode
`and a threshold voltage V,,, of a parastic MOS FET in a
`field oxide layer region. Accordingly, when it is desired
`to raise the power supply voltage for the CMIS FET’s,
`it is necessary to change the impurity concentration of a
`substrate and the impurity concentration of a well layer
`which is of opposite conductivity type to that of the
`substrate. Namely, the threshold voltage V,,, is defined
`by
`
`Van
`
`= Q, + 9.
`3
`
`<1)
`
`where Qbis a charge in a bulk, Q,,is surface state and
`oxide charge, and Csis the capacitance of the gate. A
`simple way to control the threshold voltage V,,, defined
`by the equation (1) is to control Q, That is, Q,, is related
`to the impurity concentration of the substrate and it
`increases as the impurity concentration of the substrate
`increases. Accordingly, V,,, can be increased by increas-
`ing the impurity concentration of the substrate.
`Thus, when it is desired to raise the operation volt-
`age, a voltage applied to a wiring layer extending over
`the field oxidation region also rises, resulting in a paras-
`tic channel immediately beneath the field oxide layer
`region. That is, a parastic MOS PET is formed. In order
`to avoid the formation of such a parastic MOS FET, it
`is necessary to increase the impurity concentration of
`the substrate or the impurity concentration of the well
`layer as seen from the above equation to raise the
`threshold voltage V,,, of the parastic MOS FET. How-
`ever, since the impurity concentrations of the substrate
`and the well layer are determined by electrical charac-
`teristics of the CMIS FET’s such as the threshold volt-
`
`age V,,, and mutual conductance gm, the range of the
`operating voltage for the CMIS FET’s is limited and
`the magnitude thereof is very small. For example, when
`the threshold voltage V,;, of an N-channel MOS FET
`formed in a P-type well layer is 0.45 volts, a parastic
`channel is formed at about 4 volts because an N-type
`inversion layer is readily formed because of many so-
`dium (+) ions present in the field oxide layer. As a
`result, the operating voltage should be up to about 3
`volts.
`As a commonly used method for manufacturing the
`CMIS FET’s of the LOCOS structure which avoids the
`formation of the parastic channel in the P—type well
`layer and which can be practiced in a simple way, a
`technique disclosed in the Philips Technical Review,
`Vol. 34, No. l, 1974, pp. 19-23, is known. According to
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`Page 4 of 7
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`It is an object of the present invention to provide a
`method for manufacturing CMIS FET’s of LOCOS
`structure which allows the establishment of the thresh-
`old voltage V,,, of the parastic MOS FET in the field
`oxide layer region independently of the threshold volt-
`age V,,, of the active region whereby the operating volt-
`age can be raised and the range thereof can be widened.
`It is another object of the present invention to pro-
`vide a method for manufacturing CMIS FET’s of
`LOCOS structure suited for a semiconductor integrated
`circuit device comprising a number of CMIS FET’s of
`LOCOS structure.
`
`It is another object of the present invention to pro-
`vide a method for manufacturing CMIS FBT's of
`LOCOS structure suited for a semiconductor integrated
`circuit device operating at a high supply voltage.
`It is another object of the present invention to pro-
`vide a method for manufacturing CMIS FET’s of
`LOCOS structure having less crystal defects.
`It is another object of the present invention to pro-
`vide a method for manufacturing CMIS FET’s of
`LOCOS structure which allows a high integration den-
`sity.
`It is another object of the present invention to pro-
`vide a method for manufacturing CMIS FET’s of
`
`

`

`4,110,899
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`3
`LOCOS structure which is less influenced by contami-
`nation.
`In order to achieve the above objects, the method of
`manufacturing the CMIS FET’s of the LOCOS struc-
`ture according to the present invention comprises the
`following steps of;
`(l) forming a P(or N)—type well layer in a portion of
`an N(or P)-type semiconductor substrate surface and
`then forming a thin thermal oxidation layer over the
`entire surface and then forming a silicon nitride layer
`over the entire surface thereof,
`(2) etching away the silicon nitride layer at areas on
`which field oxide layers are to be formed,
`(3) ion implanting donor (or acceptor) and acceptor
`(or donor) impurities at those areas in the N(or P)-type
`semiconductor substrate and the P(or N)-type well
`layer on which the field oxide layers are to be formed,
`(4) heat treating the substrate to selectively thermally
`oxidize the areas on which the field oxide layers are to
`be formed, using said silicon nitride layer as a mask, and
`(5) removing the silicon nitride layer formed in the
`step (1) and the thin thermal oxidation film beneath the
`silicon nitride layer and then forming a gate insulation
`layer, a source region and a drain region of a MIS de-
`vice in the N(or P)-type semiconductor substrate and
`the P(or N)-type well layer.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIGS. 1 through 6 show one embodiment of the
`present invention illustrating a sequence of steps, in
`partial sectional views, of manufacturing a semiconduc-
`tor integrated circuit device comprising a plurality of
`CMIS FET‘s of LOCOS structure.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`
`The method for manufacturing a CMIS FET IC of
`LOCOS structure of the present invention is now ex-
`plained in the order of manufacturing steps.
`(a) A portion of a surface of an N-type silicon sub-
`strate is delimited, in which a P-type well layer 2 of a
`thickness of about 6-8 pm is formed by ion implantation
`technique. Thereafter, the surface of the substrate is
`thermally oxidized in a dry 0, atmosphere at about
`1000' C. to form a silicon oxide (SiO2) layer 3 of the
`thickness of about 700 A. Then, a silicon pitride (Si N.)
`layer 4 of the thickness of about 1000 A - 1400 A is
`formed by vapor reaction on the layer 3. (FIG. 1)
`(b) The Si3N4 layer 4 and the SiO, layer 3 therebe-
`neath are etched away except at areas 4a and 417 on
`which field oxide layers are to be formed, using a photo-
`resist layer 5 (5a and 5b) as a mask. Then, that portion
`of the surface of the substrate 1 on which a P-channel
`MOS device is to be formed is covered with a photore-
`sist layer 6. and then boron (B) impurity 7 is ion im-
`planted at 75KeV at that area of the surface of the sub-
`strate l on which the field oxide layer of the N-channel
`MOS device is to be formed, using, as a mask, a photo-
`resist layer 6 and the photoresist layer 5a which has
`been used in etching the Si3N. layer 4 and the underly-
`ing SiO;layer 3 so that a surface impurity concentration
`of about 2 X 10" atoms/cm’ to 5 X 10"’ atoms/cm’ is
`obtained at the said area. (FIG. 2)
`(c) After removing the photoresist layers 5 and 6, a
`new photoresists layer 8 is selectively formed on that
`portion of the surface of the substrate 1 in which the
`N-channel MOS device is to be formed. Then, using the
`selectively formed photoresist layer 8 and the silicon
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`Page 5 of 7
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`4
`nitride (Si3N4) layer under which the P-channel MOS
`device is to be formed as a mask, phosphorus (P) impu-
`rity 9 is ion implanted at 45KeV in that portion of the
`surface of the substrate 1 on which the field oxide layer
`of the P-channel MOS device is to be formed. (FIG. 3)
`The ion implantation energy of 45KeV for the phospho-
`rus impurity is enough to obtain an area of a sufficiently
`high surface impurity concentration. On the other hand,
`with the acceleration energy of below 60KeV, phos-
`phonis ions can be masked only by the Si3N.,layer or the
`SiO2 layer. Accordingly, the photoresist layer need not
`be maintained on the Si3N4 layer 4b. This means that the
`alignment of the mask used in exposing step for the
`photoresist layer 8 need not be highly accurate. That is,
`an edge 8S of the photoresist layer 8 may extend beyond
`a PN junction J between the P-type well layer 2 and the
`N-type substrate 1.
`(d) After removing the photoresist layer 8, the sub-
`strate 1 is oxidized in a wet oxygen atmosphere at 1000"
`C. for about 7.5 hours to form selective silicon oxide
`(SiO,_) layers 10 of a thickness of about 1.4 pm of
`LOCOS structure (FIG. 4). In this case, because of the
`masking action of the Si3N4 layer 4 to the oxygen, sili-
`con oxide (SiO.,) layer is not formed on the areas cov-
`ered with the Si,N, layer 4. Then, the selective oxida-
`tion mask of the Si3N4 layer 4 and the underlying thin
`SiO2 layer 3 are removed (FIG. 4).
`Through the heat treatment for forming the thick
`SiO; layers 10 of the LOCOS structure, the impurities
`which have been ion implanted in the previous step are
`activated and diffused so that P+-type field diffusion
`layers 7a and N+-type field diffusion layers 9a, which
`act as parastic channel stopper layers, are formed (FIG.
`4).
`
`(e) On the surface of the substrate 1, gate oxide layers
`11 of a thickness of about 1000 A are formed in a dry
`0, atmosphere at 1000“ C. Then, on the surfaces of the
`gate oxide layers 11, polycrystalline silicon layers 12 are
`deposited to a thickness of about 3500 A. the polycrys-
`talline silicon layers are then etched away by photo-
`etching except those areas which are to act as gate
`electrodes. Etching is again carried out using the re-
`maining polycrystalline silicon layers 12 as a mask to
`remove the gate oxide layers 11 on the source and drain
`regions. The drain regions 13, 14 and the source regions
`13a, 14a of the MOS devices are then formed using the
`thick field oxide layers 10 and the polycrystalline silicon
`layers 12 as a mask (FIG. 5).
`The formation of the drain regions 13, 14a and the
`source regions 13a, 14 of the P-channel and N-channel
`MOS devices, respectively, is explained in more detail.
`A photoresist layer is formed on an area in which the
`N-channel MOS device is to be formed. Those portions
`of the gate oxide layer 11 which correspond to the
`source and drain regions of the P-channel MOS device
`are removed. Then, phosphorus impurity is diffused in
`the exposed surface of the substrate 1 using the poly-
`crystalline silicon layer 12 for the gate electrode G, and
`portions of the field oxide layers 10 as a diffusion mask,
`to form the source region 14 and the drain region 14a.
`In this manner, the P-channel MOS device is formed.
`Then, the photoresist layer is removed and new photo-
`resist layers are formed on the source region 14 and the
`drain region 14a, and the portions of the gate oxide
`layer 11 which correspond to the source and drain re-
`gions of the N-channel MOS device are removed.
`Thereafter, using the polycrystalline silicon layer 12 for
`the gate electrode G, of the P-channel MOS device and
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`mask, boron impurity is diffused to form the source
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`region 13a and the drain region 13.
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`(f) To insulate the polycrystalline silicon layers 12 for
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`the gates G, a silicon oxide (SiO2) layer 15 is deposited
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`on the surface of the substrate by thermal decomposi-
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`tion of silane (SiH4) (FIG. 6). A PSG (phosphosilicate
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`glass) layer is preferable as an insulating layer to insulate
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`the polycrystalline silicon layers 12 for the gate elec-
`trodes G. Then, after forming windows for contacts, an
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`aluminum layer of a thickness of 1 pm is formed by
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`vacuum deposition and required aluminum wiring pat-
`terns as well as source electrodes S and drain electrodes
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`D are formed by a conventional photoetching process
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`(FIG. 6).
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`(g) The wafer treatment process is thus completed.
`Thereafter it is sliced into chips in a conventional man-
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`ner, and they are assembled into devices.
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`The present method for manufacturing the CMIS
`FET’s of the LOCOS structure described hereinabove
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`has the following features.
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`(1) Since the field diffusion layers 7a and 9a having
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`impurity concentrations higher than that of the sub-
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`strate 1 or the P-type well layer 2 and selected indepen-
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`dently of those impurity concentrations are formed
`under the thick SiO2 layer 10 which act as the field
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`oxide layer, the threshold voltage V,,, of the parastic
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`MOS transistor in the region of the field oxide layer 10
`can be controlled to any value by adjusting the amount
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`of ion implantation, and it can be set independently of 30
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`the threshold voltages V,,, of the substrate 1 and the
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`P-type well layer 2. Therefore, according to the present
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`invention, it is possible to manufacture CMIS FET’s
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`and semiconductor integrated circuit devices compris-
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`ing a number of CMIS FET’s having different operat-
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`ing voltages in the same manufacturing process.
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`(2) In the formation of the field diffusion layers 7a
`and 9a, the Si3N4 layer 4 which serves as the mask in
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`forming the thick field silicon oxide layer 10 by the
`thermal oxidation is used in situ. Therefore, the field
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`diffusion layers 7a and 9a are self-aligned with the field
`silicon oxide layer 10 and the sources and drains of the
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`devices resulting in a high integration density. Thus, the
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`semiconductor device of the present invention can be
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`manufactured in a very simple way.
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`(3) Because of the CMIS semiconductor device of the
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`LOCOS structure, fine processing is possible. Further-
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`more the performance of the device is high in that it
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`provides a high operation speed and a low power con-
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`sumption. Therefore, the CMIS FET’s of the present
`invention can be applied to various products.
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`(4) Since the P-type well layer is formed before the
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`formation of the field oxide layer, it is possible to form
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`the field oxide layer in the well layer. Thus, when it is
`desired to form a plurality of MOS FET’s in the well
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`layer, the design of the layouts of the MOS FET’s and
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`the wiring layers therefor is facilitated. Furthermore,
`the source and drain regions can be readily formed
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`using the field oxide layers in the well layer as the mask.
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`In ion implanting the impurity in the above embodi-
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`ment, the thin SiO2 layer 3 under the Si3N4 layer 4 is
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`removed to expose the surfaces of the N-type substrate
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`1 and the P-type well layer 2. However, the thin SiO2
`layer 3 may be left unremoved. In this case, less defects
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`on the surfaces of the N-type substrate 1 and the P-type
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`well layer 2 due to the ion damage take place and the
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`affect by the contamination is minimized because the
`surfaces are not exposed. Furthermore, by the presence
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`of the thin SiO2 layer 3, bird-beaks do not grow. That is,
`when the thin SiO2 layer 3 is etched away, the parts of
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`the SiO2 layer 3 under the Si3N4 layers 4a and 4b, which
`are called overhung, are also etched away. As a result,
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`lateral oxidation proceeds more rapidly resulting in the
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`growth of the bird-beaks. On the other hand, when the
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`thin SiO2 layer 3 is left unremoved, the bird-beaks are
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`grown less slowly so that the area occupied by the field
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`oxide layers is minimized resulting in the increase in the
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`integration density.
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`In the above embodiment, the parastic channel stop-
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`per layers (field diffusionlayers) are formed under the
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`field oxide layers formed in the P-type well layer and
`the substrate. In this case, the operating voltage of up to
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`about 50 volts is permitted. On the other hand, if the
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`semiconductor integrated circuit device manufactured
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`by the present method is to be used at the operating
`voltage of less than 10 volts, the phosphorus ion implan-
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`tation shown in FIG. 3 may be omitted, because if the
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`V,,, of the P-channel MOS FET is 0.45 volts the V,,, of
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`the N-type parastic channel is as high as 12 volts or
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`higher and it is not readily inverted at the operating
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`voltage of below 10 volts.
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`It should be understood that the present invention is
`not limited to the embodiment described above but it
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`can be applied to the CMIS FET’s of the LOCOS struc-
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`ture having various gate electrodes or gate insulation
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`layers and the semiconductor integrated circuit devices
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`comprising such CMIS FET’s.
`We claim:
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`1. A method for manufacturing complementary insu-
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`lated gate field effect transistors comprising the steps of:
`(a) delimiting a portion of a surface of a semiconduc-
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`tor substrate of a first conductivity type and form-
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`ing therein a well layer of a second conductivity
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`type, forming a thin insulating layer over the entire
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`surface thereof and then forming a silicon nitride
`layer over the entire surface thereof;
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`(b) etching away said silicon nitride layer at least
`those areas on which field oxide layers are to be
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`formed;
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`(c) introducing impurity of the second conductivity
`type at that area in said well layer of the second
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`conductivity type on which the field oxide layer is
`to be formed;
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`(d) heat treating the substrate to selectively thermally
`oxidize the areas on which the field oxide layers are
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`to be formed, using said silicon nitride layer as a
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`mask to form a thick field oxide layer; and
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`(e) removing the silicon nitride layer and the underly-
`ing thin insulating layer formed in said step (a),
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`selectively forming gate insulation layers and sili-
`con layers on the exposed substrate and well layer,
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`forming source regions and drain regions of MIS
`devices in said semiconductor substrate of the first
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`conductivity type and the well layer of the second
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`conductivity type using said silicon layers and said
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`thick field oxide layers as masks, and forming diffu-
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`sion layers of desired impurity concentrations be-
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`neath said thick field oxide layers.
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`2. A method for manufacturing complementary insu-
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`lated gate field effect transistors according to claim 1
`wherein said step (b) includes a sub-step of etching
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`away the thin insulating layer under the silicon nitride
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`layer.
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`3. A method for manufacturing complementary insu-
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`lated gate field effect transistors according to claim 2
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`Page 6 of 7
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`Page 6 of 7
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`4,110,899
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`(0 removing the silicon nitride layer and the underly-
`ing thin thermal oxidation layer formed in the step
`(a), selectively forming gate insulation layers and
`silicon layers on the exposed surface area of the
`substrate and well layer, forming source regions
`and drain regions of the respective MIS devices
`using said silicon layers and said thick field oxide
`layers as masks. and forming difiusion layers of
`desired impurity concentrations under said field
`oxide layers.
`8. A method for manufacturing a semiconductor inte-
`grated circuit device including complementary insu-
`lated gate field effect transistors comprising the steps of:
`(a) delimiting a portion of a surface of an N-type
`silicon substrate and forming a P-type well layer
`therein by ion implantation, forming a silicon diox-
`ide layer over the entire surface thereof and then
`forming a silicon nitride layer over the entire sur-
`face thereof;
`(b) selectively forming a first photoresist layer on said
`silicon nitride layer over said N-type silicon sub-
`strate and said P-type well layer;
`(c) etching away said silicon nitride layer and the
`underlying silicon nitride layer using said first photore-
`sist layer as a mask to expose surfaces of said N-type
`silicon substrate and said P-type well layer;
`(d) covering the exposed N-type silicon substrate
`surface with a second photoresist layer;
`(e) ion implanting an acceptor impurity into the ex-
`posed surface area of said P-type well layer usin
`said first photoresist layer as a mask;
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`(t) removing said first and second photoresist layers
`and covering the exposed surface of said P-type
`well layer with a third photoresist layer;
`(g) ion implanting a donor impurity into the exposed
`surface area of said N-type silicon substrate using
`said silicon nitride as a mask;
`(h) removing said third photoresist film and selec-
`tively thermally oxidizing the exposed surfaces of
`said P-type well layer and said N-type silicon sub-
`strate using said silicon nitride layer as a mask to
`form thick field silicon dioxide layers;
`(i) etching away said silicon nitride layer and the
`underlying silicon dioxide layer to expose said
`P-type well layer and said N-type silicon substrate;
`(j) oxidizing the exposed surfaces of said P-type well
`layer and said N-type silicon substrate to form gate
`silicon dioxide layers;
`(k) forming silicon layers over entire surfaces of said
`field silicon dioxide layers and said gate silicon
`dioxide layers;
`(1) selectively etching away said silicon layers and
`said gate silicon dioxide layers to expose the sur-
`faces of said N-type silicon substrate and said P-
`type well layer;
`(in) diffusing an acceptor impurity into the exposed
`N-type silicon substrate and a donor impurity into
`the exposed P-type well layer using the remaining
`silicon layer and said field silicon dioxide layers as
`masks to form source regions and drain regions,
`respectively, and
`(n) connecting aluminum layers to said source regions
`and drain regions formed in said N-type silicon
`substrate and said P-type well layer, respectively.
`0
`0
`O
`O
`O
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`15
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`7
`wherein said thin insulating layer is a thermal oxidation
`layer.
`4. A method for manufacturing complementary insu-
`lated gate field effect transistors according to claim 1
`wherein in said step (c) said impurity of the second 5
`conductivity type is introduced, by ion implantation,
`into those areas of the well layer of the second conduc-
`tivity type on which the field oxide layers are to be
`formed.
`5. A method for manufacturing complementary insu- 10
`lated gate field effect transistors comprising the steps of:
`(a) delimiting a portion of a surface of an N-type
`semiconductor substrate and forming a P-type well
`layer therein, forming a thin thermal oxidation
`layer over the surface thereof and then forming a
`silicon nitride film over the surface thereof;
`(b) etching away said silicon nitride layer at those
`areas on which field oxide layers are to be formed;
`(c) ion implanting donor and acceptor impurities into
`those areas in said N-type semiconductor substrate
`and the P-type well layer, respectively, on which
`the field oxide layers are to be formed, using a
`portion of said silicon nitride layer as a mask;
`(d) heat treating the substrate to selectively thermally
`oxidize those areas on which the field oxide layers
`are to be formed, using said silicon nitride layer as
`a mask for forming the field oxide layers of
`LOCOS structure; and
`(e) removing said silicon nitride layer and the under-
`lying thin thermal oxidation layer formed in said
`step (a), selectively forming gate insulation layers
`and semiconductor layers on the exposed N-type
`substrate and exposed P-type well layer, forming
`source regions and drain regions of MIS devices in
`said N-type semiconductor substrate and said P-
`type well layer using said semiconductor layers
`and said field oxide layers as masks.
`6. A method for manufacturing complementary insu-
`lated gate field effect transistors according to claim 5
`wherein in said step (c) the donor is phosphorus and the
`acceptor is boron.
`7. A method for manufacturing complementary insu-
`lated gate field effect transistors comprising the steps of:
`(a) delimiting a portion of a surface of an N(P)-type
`semiconductor substrate and forming a P(N)-type
`well layer therein, forming a thin thermal oxidation
`layer over the entire surface thereon, and then
`forming a silicon nitride layer over the entire sur-
`face thereof;
`(b) etching away said silicon nitride layer and the
`underlying thin thermal oxidation layer at those
`areas on which field oxide layers are to be formed;
`(c) ion implanting acceptor (donor) or donor (accep-
`tor) impurity in the exposed surface area of the
`substrate in the area of N(P) channel of P(N) chan-
`nel device;
`(d) ion implanting donor (acceptor) or acceptor (do-
`nor) impurity in the exposed surface area of the sub-
`strate in the area of P(N) channel of N(P) channel de-
`vice;
`(e) heat treating the substrate to selectively thermally
`oxidize the exposed surface areas of the substrate using
`said silicon nitride layer as a mask to form thick field
`oxide layers; and
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