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`Lowreyet al.
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`1s)
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`{11] Patent Number:
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`[45] Date of Patent:
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`5,021,353
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`Jun. 4, 1991
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`[54] SPLIT-POLYSILICON CMOS PROCESS
`INCORPORATING SELF-ALIGNED
`
`
`SILICIDATION OF CONDUCTIVE REGIONS
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`[75]
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`Inventors: Tyler A. Lowrey; Dermot M. Durcan;
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`Trung T. Doan; Gordon A. Haller;
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`MarkE. Tuttle, all of Boise, Id.
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`[73] Assignee:
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`Micron Technology, Inc., Boise, Id.
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`[21} Appl. No.: 485,029
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`[22] Filed:
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`Feb. 26, 1990
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`[56]
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`[51] mt. C5 esceecsssssssee HOIL 21/265; HOIL 21/336
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`[52] U.S. Che ceessssssssssssssssssssssessuse ssassssse 437/345 437/44;
`437/57; 357/42; 357/44
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`[58] Field of Search ws 437/27, 28, 29, 30,
`437/34, 56, 57, 200, 192, 40, 41, 44, 233;
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`357/23.3, 23.4, 40, 41, 42, 44
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`"References Cited
`
`
`U.S. PATENT DOCUMENTS
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`4,530,150 7/1985 Shirato vc.esstenessceteees 437/44
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`4,745,086
`5/1988 Parrillo .........
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`FOREIGN PATENT DOCUMENTS
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`
`2/1981 Japan ....sscccescsesssesessrersersensens 437/41
`0019669
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`
`
`
`
`1/1982 Japan.....
`» 437/34
`0017164
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`
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`
`
`3/1984 Japan.....
`» 437/41
`0055068
`
`
`
`
`
`
`0213051 10/1985 Japan.....
`wees 437/44
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`
`
`
`0165355
`7/1987 Japan ....scecccesseeseceeeeeeeeees 437/233
`
`
`
`
`
`
`Primary Examiner-——Olik Chaudhuri
`
`
`Assistant Examiner—M. Wilczewski
`
`
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`
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`
`
`Attorney, Agent, or Firm—Angus C. Fox,III; Stanley N.
`
`
`
`Protigal; Albert Crowder
`
`
`
`
`
`
`
`ABSTRACT
`(57]
`An improved CMOSfabrication process which uses
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`separate masking steps to pattern N-channel and P-
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`channel transistor gates from a single layer of conduc-
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`tively-doped polycrystalline silicon (poly) and incorpo-
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`rates self-aligned salicidation of conductive regions.
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`The object of the improved processis to reduce the cost
`and improvethe reliability, performance and manufac-
`
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`turability of CMOS devices by a process which features
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`a dramatically reduced number of photomasking steps
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`and which further allows self-aligned salicidation of
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`transistor conductive regions. By processing N-channel
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`and P-channel devices separately, the number of photo-
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`masking steps required to fabricate complete CMOS
`circuitry in a single-polysilicon-layer or single-metal
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`layer process can be reduced from eleven to eight.
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`Starting with a substrate of P-type material, N-channel
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`devices are formedfirst, with unetched polyleft in the
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`future P-channel regions until N-channel processing is
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`complete. The improved CMOSprocess provides the
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`following advantages over conventional process tech-
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`nology: Use of a masked high-energy punch-through
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`implant for N-channel devices is not required; individ-
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`ual optimization of N-channel and P-channel transistors
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`is made possible; a lightly-doped drain (LDD) design
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`for both N-channel and P-channeltransistors is readily
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`implemented;
`source/drain-to-gate
`offset may be
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`changed independently for N-channel and P-channel
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`devices; and N-channel and P-channel transistors can be
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`independently controlled and optimized for best LDD
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`performance andreliability.
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`5 Claims, 13 Drawing Sheets
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`Page 1 of 20
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`TSMCExhibit 1017
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`TSMC Exhibit 1017
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`Page 1 of 20
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`U.S. Patent
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`June 4, 1991
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`Sheet 1 of 13
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`5,021,353
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`U.S. Patent
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`June 4, 1991
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`Sheet 3 of 13
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`5,021,353
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`June 4, 1991
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`Sheet 4 of 13
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`June 4, 1991
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`5,021,353
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`SPLIT-POLYSILICON CMOS PROCESS
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`INCORPORATING SELF-ALIGNED
`
`
`SILICIDATION OF CONDUCTIVE REGIONS
`
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`2
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`arsenic or phosphorus to create the N-wells. The N-
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`well regions are then oxidized using a first conventional
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`LOCOS (LOCal Oxidation of Silicon) step to create a
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`silicon oxide layer to protect them from an optional
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`boron implant which adjusts the concentration of the
`FIELD OF THE INVENTION
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`P-type substrate for the N-channel devices. During the
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`LOCOSprocess, the pad oxide servesasa stress relief
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`This invention describes a process sequence for the
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`layer. Alternatively, an oxide deposition or oxide
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`fabrication of Complimentary Metal Oxide Semicon-
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`growth step could replace the first LOCOSstep,elimi-
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`ductor (hereinafter “CMOS”)integrated circuits. More
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`nating the need for thefirst pad oxide layer and thefirst
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`nitride layer. A subsequent high-temperature drive step
`tors of both channel types, using self-alignedsilicidation
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`ofgates and source/drain regions to reduce the number
`is used to achieve the desired N-well junction depth.
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`of photomasking steps required in a split-polysilicon
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`Following removalofthe oxide layer, a second layer of
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`process.
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`pad oxide is grown over the entire wafer. A second
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`silicon nitride layer is then deposited on top of the pad
`BACKGROUND OF THE INVENTION
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`oxide layer.
`Although CMOSintegrated circuit devices are often
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`The second photomask is used to pattern portions of
`referred to as “semiconductor” devices, such devices
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`the secondsilicon nitride layer which define the future
`are fabricated from various materials which are either
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`active areas on the wafer.
`electrically conductive, electrically nonconductive or
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`The third photomask is used to cover the N-well
`electrically semiconductive. Silicon,
`the most com-
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`regions in order to effect a selective boron field-isola-
`monly used semiconductor material can be made con-
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`tion implant. Following the stripping of the third photo-
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`ductive by doping it (introducing an impurity into the
`mask, the regions on the wafer that are not protected by
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`silicon crystal structure) with either an element such as
`the remaining portions of the secondsilicon nitride
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`boron which has oneless valence electron thansilicon,
`layer are oxidized to form field oxide regions using a
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`or with an element such as phosphorusor arsenic which
`second conventional LOCOSstep. The nitride layeris
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`have one morevalenceelectron thansilicon. In the case
`then stripped,as is the pad oxide layer. A layer ofsacri-
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`of boron doping, electron “holes” become the charge
`ficial oxide is then grown to eliminate the “white rib-
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`carriers and the dopedsilicon is referred to as positive
`bon”or Kooieffect in the active areas that follows field
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`or P-type silicon. In the case of phosphorusor arsenic
`oxidation. An unmasked implant may be used as a
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`doping,
`the additional electrons become the charge
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`threshold voltage (V7) adjustment.
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`carriers and the dopedsilicon is referred to as negative
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`The fourth photomask exposes only the channel re-
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`or N-typesilicon. If dopants of opposite type conduc-
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`gions of the N-channel
`transistors to a high-energy
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`tivity are used, counter doping will result, and the con-
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`boron punch-through implant. This implant increases
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`ductivity type of the most abundant impurity will pre-
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`both source-to-drain breakdownvoltage and the thresh-
`vail. Silicon is used either in single-crystal or polycrys-
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`old voltage,
`thus avoiding the short-channel effects
`talline form. Polycrystalline silicon is referred to herein-
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`after as “polysilicon” or simply as ‘poly’. Originally,
`which are inherent to nonimplanted, sub-micron N-
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`MOSdevices were manufactured from metal (used as
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`channel devices. Following the punch-through implant,
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`the transistor gate), semiconductor material (used as the
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`the fourth photomask is stripped, as is the sacrificial
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`transistor channel material), and oxide (used as the di-
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`oxide layer. A layer of gate oxide is then grown onall
`electric between the gate and the substrate. Currently,
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`active areas, following which a polysilicon layer is de-
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`however, most MOStransistors are fabricated using a
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`posited on top of the gate oxide using conventional
`conductively-doped polycrystalline silicon layer for the
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`means(e.g., chemical vapor deposition). The poly layer
`gate material.
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`is then doped with phosphorus, coated with a layer of
`CMOSprocesses begin with a lightly-doped P-type
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`tungsten silicide by various possible techniques(e.g.,
`or N-type silicon substrate, or lightly-doped epitaxial
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`chemical vapor deposition, sputtering, or evaporation).
`silicon on a heavily doped substrate. For the sake of
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`The fifth photomask patterns the silicide-coated
`simplicity,
`the prior art CMOS process will be de-
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`polysilicon layer to form the gates of both P-channel
`scribed using P-type silicon as the starting material. If
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`and N-channeltransistors. Stripping of the fifth photo-
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`N-type silicon were used, the process steps would be
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`maskis followed by a source/drain oxidation.
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`virtually identical, with the exception that
`in some
`The sixth photomask is used to expose only the N-
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`cases, dopant types would be reversed. Fabrication of
`channel source and drain regions to a relatively low-
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`sub-micron CMOSdevices havingasilicided single
`dosage phosphorusimplant whichcreateslightly-doped
`55
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`poly layer and a single metal layer using prior art tech-
`N- regions. Following the stripping of the sixth mask, a
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`nology generally requires at least 11 photoresist masks
`layer of silicon dioxide is deposited on the wafer. An
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`(or simply “photomasks”) to create N-channel and P-
`anisotropic etch and a subsequent optional isotropic
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`channeltransistors on a silicon substrate (an additional
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`etch of thesilicon dioxide layer leave oxide spacers on
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`one or two masks. is required if lightly-doped drain
`the sides of each N-channel and P-channeltransistor
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`design is required for both types of transistors). No
`gate.
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`attemptis madeatsiliciding source and drain regionsin
`the N-channel
`The seventh photomask exposes
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`this process. The function of these 11 masks is described
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`source and drain regions to a relatively high-dosage
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`below.
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`phosphorusorarsenic implant which creates the heavi-
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`Thefirst photoresist mask is used to define N-wells.
`ly-doped N-+tregions. Following the stripping of the
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`This is done by creating a first layer of pad oxide on a
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`seventh mask, the wafer is optionally subjected to ele-
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`lightly-doped P-type substrate, depositing a layer of
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`vated temperature for the purpose of diffusing the N-
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`nitride on top ofthe pad oxide, masking thenitride layer
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`to expose certain regions which are then implanted with
`channel implants.
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`_ 0
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`Page 15 of 20
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`Page 15 of 20
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`5,021,353
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`3
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`The eighth photomask is used for the high-dosage
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`implantation of either boron or boron difluoride, which -
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`creates heavily doped source and drain regions for the
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`P-channel transistors. Following the stripping of the
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`eighth mask, an elevated-temperature drive step is per-
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`formed, after which the transistors are fully formed. All
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`structures are then covered by anisolation oxide layer.
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`The ninth photomask is used to define contact vias
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`which will pass through the isolation oxide layer to the
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`poly structures or active area conductive regions be-
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`low. A deposition of an aluminum metal layer follows.
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`The tenth photomaskis used to pattern the aluminum
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`layer for circuit interconnects. Using a blanket deposi-
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`tion process, the circuitry is covered with one or more
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`passivation layers.
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`The eleventh photomask defines bonding pad open-
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`ings which will expose bonding pad regions on the
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`aluminum layer below. This completes the conventional
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`single-poly, single-metal CMOSprocess.
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`The business of producing CMOS semiconductor
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`devices is a very competitive, high-volume business.
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`Process efficiency and manufacturability, as well as
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`productquality, reliability, and performanceare the key
`factors that will determine the economic success or
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`failure of such a venture. Each new generation of
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`CMOSdevices is expected to be faster and more com-
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`pact than the generation it replaces. Four-fold density
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`increases from one generation to the next have become
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`standard. If this increase in density is achieved with no
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`increase in die size, device geometries must be more or
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`less halved. As geometries shrink, each photolitho-
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`graphic step becomes more costly. The increase and
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`cost maybeattributed to a numberoffactors, including:
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`higher capital costs for precision “state-of-the-art”
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`photolithographic equipment;
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`lowered yields and decreasedreliability due to defect
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`density increases invariably associated with each photo-
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`masking step;
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`an increase in the numberof processing steps for each
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`mask level, which slows the fabrication process and
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`requires additional expensive equipment;
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`the requirement for ultra-clean fabrication facilities
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`which are both expensive to construct and expensive to
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`operate;
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`greater investment per wafer during fabrication,
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`whichincreases the cost of scrapping defective devices;
`and
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`costs associated with the step required subsequent to
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`the masking step, whether it be an implant or an etch.
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`From the aforementioned discussion,it is evident that
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`the elimination of photomasking steps from a CMOS
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`process will have a direct impact on the cost,reliability,
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`and manufacturability of the product.
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`A novel process is disclosed in the 1982 Japanese
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`patent issued to Masahide Ogawa (No. 57-17164) for
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`fabricating a CMOSintegrated circuit by processing
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`N-channel and P-channel devices separately. As with
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`the conventional CMOSprocess, .a single polysilicon
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`layer is used to form both N-channel and P-channel
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`gates. However, N-channel devices are formedfirst,
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`with unetched polysilicon left in the future P-channel
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`regions until N-channel processing is complete. The
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`mask used to subsequently pattern the P-channel de-
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`vices is also used to blanket and protect the already-
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`formed N-channel devices. This process is herein re-
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`ferred to as the split-polysilicon CMOS process. The
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`spilt-polysilicon CMOS process,
`through largely ig-
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`nored by semiconductor manufacturers in the U.S. and
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`5
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`4
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`abroad, holds tremendouspotential for reducing photo-
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`masking steps in a CMOS process.
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`A pending U.S. Pat. No. 7/427,639, submitted by
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`Tyler A. Lowrey, Randal W. Chance, and Ward D.
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`Parkinson of Micron Technology, Inc. of Boise, Id.
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`details an improved split-polysilicon CMOS process.
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`The improved CMOSfabrication process is based on
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`the aforementioned split-polysilicon CMOS process
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`developed in Japan by Mashahide Ogawa. The im-
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`proved process utilizes an unmasked N-channel punch-
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`through implant and unmasked N-channel source/drain
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`implants that are self-aligned to gate electrodes to cre-
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`ate high-performance LDD-type N-channeltransistors.
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`These high-performance transistors have both punch-
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`through regions and LDD-type source/drain regions.
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`By utilizing the split-polysilicon CMOSprocessin com-
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`bination with the unmasked implants, the number of
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`masks required to form both N-channel and P-channel
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`devices can be reduced from eleven (for the standard
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`CMOSprocess) to eight (for the improved process).
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`P-channel source and drain regions, although of con-
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`ventional non-LDDdesign,are offset from the edges of
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`the P-channel gates by undercutting the gates beneath
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`the photoresist during the gate-patterning etch. The
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`gate-patterning photoresist is then used as an offsetting
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`implant mask.
`SUMMARYOF THE INVENTION
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`The object of the present invention is to reduce the
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`cost and improve the reliability, performance and
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`manufacturability of CMOSdevices by implementing a
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`variation of the improvedsplit-polysilicon CMOSfabri-
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`cation process developed by Mssrs. Lowrey, Chance
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`and Parkinson which provides LDd sources and drains
`for both N-channel and P-channeltransistors with no
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`increase in the number of photomaskingsteps, and in-
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`corporatesself-aligned silicidation of transistor gates,
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`sources and drains. Like the original Micron-developed
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`improved split-polysilicon CMOS process,
`the new
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`split-polysilicon silicide process, which is the focus of
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`the present invention, also utilizes eight masks to fabri-
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`cate both types of transistors. The function of each of
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`the eight required photomasks is described below. For
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`the sake of simplicity,
`the process will be described
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`using P-type silicon as the starting material. If N-type
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`silicon were used, theprocess steps would bevirtually
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`identical, with the exception that dopant types would be
`reversed in somecases.
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`The first photomask is used to form the N-well re-
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`gions in a conventional manner.
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`The second photomask is used to conventionally
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`define the active areas by patterning a nitride layer.
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`The third photomask is used to cover the N-well
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`regions in order to effect the boronfield isolation im-
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`plant, also in accordance with conventional CMOS
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`‘technology. Following the stripping of the third mask,
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`LOCOSis used to growthefield oxide regions, and an
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`unmasked boron implantis used as a transistor threshold
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`enhancement. The use of a masked punch-through im-
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`plantat this pointis not required. Following the deposi-
`tion and doping with phosphorusofa polysilicon layer,
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`the process further deviates from convention.
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`The fourth photomaskis used to pattern the gates of
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`the N-channel transistors and to cover the P-channel
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`regions. An anisotropic dry etch is used to form the
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`N-channeltransistor gates, following which the fourth -
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`mask photoresist is stripped. Following an unmasked
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`self-aligned boron punch-through implant, a source/-
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`Page16 of 20
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`Page 16 of 20
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`5,021,353
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`5
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`drain oxidation is performed. A low-dosage unmasked
`
`
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`
`
`
`phosphorus implant then creates the lightly-doped N-
`
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`
`
`
`
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`regions of the N-channel sources and drains. Spacer
`
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`
`oxide deposition is followed by an anisotropic dry etch
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`and an optional isotropic etch (in that order), which
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`leave spacers on both sides of the N-channel gates.
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`Spacer formation is followed by a high-dosage un-
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`masked phosphorus orarsenic implant, which creates
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`the heavily-doped N+ regions of the N-channel
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`sources and drains. Doping of the poly layer in the
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`P-channel regions with the aforementioned N-channel
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`implants will have essentially no effect on P-channel
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`transistor performance, since only the gate is doped,
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`with the future source and drain regions remaining
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`untouched. Since the gate poly is doped n-type anyway,
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`there is no electrical impact on P-channel transistors.
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`Thefifth photomaskis used to pattern the gates of the
`P-channel transistors and to cover the N-channel! re-
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`gions.
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`An anisotropic etch is used to etch the P-channel
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`transistor gates. A low-dosage boron implant may then
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`be optionally performed in the regions not protected by
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`the fifth photomask,thus creating lightly-doped sources
`and drains for the P-channel devices. Removal of the
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`fifth photomaskis followed by the blanket deposition of
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`‘a spacer oxide layer, which is anisotropically etched
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`(and optionally subsequently isotropically etched) to
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`create spacers on both sides of the P-channel gates.
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`P-channel spacer formation is followed by a boron or
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`boron-defluoride high-dosage unmasked implant, thus
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`creating heavily-doped sources and drains for the P-
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`channel devices. Since the dosage of the boron-difluo-
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`ride implantis only approximately one-third to one-sev-
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`enth the dosage of the arsenic implants used to create
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`the source/drain regions for the N-channel devices,
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`performance of the N-channel devices remains largely
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`unaffected by the partial counter-doping of the N-chan-
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`nel source/drain regions.
`A second embodiment of the invention allows P-
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`channel transistor gates to be created by an isotropic
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`dry etch with the fifth photomask in place. The fifth
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`photomask patterns the P-channel transistor gates, and
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`the isotropic dry etch produces gates,
`the edges of
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`which are purposely undercut (recessed) under the
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`patterning photoresist. After the etch, and with the fifth
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`photomaskstill in place, a high-dosage boron or boron
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`difluoride implant is used to create P-channel sources
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`and drains. The undercut P-channel gate offsets the
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`high-dosage P-channel source/drain implant such that
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`implant diffusion related to subsequent
`temperature
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`steps does not result in excessive gate overlap by these
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`implants. Using only a single P-channel source/drain
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`implant eliminates the problem of counter-doping of the
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`N-channel source/drain regions, since all N-channel
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`devices are protected by the fifth photomask. Removal
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`of the fifth photomaskis followed by the blanket deposi-
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`tion of a spacer oxide layer, which is anisotropically
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`etched (and optionally subsequently isotropically
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`etched) to create spacers on both sides of the P-channel
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`gates.
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`A layer of titanium metalis sputter deposited (sputter
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`deposition is only one of several useable techniques) on
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`top gfall the circuitry. A sintering step causes the tita-
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`nium to react with all unoxidized silicon (i.e., all gates
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`and source/drain regions for both N-channel and P-
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`channeltransistors) to form titanium silicide. A sulfuric
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`acid and hydrogen peroxide bath and a subsequent am-
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`monium hydroxide and hydrogen peroxide bath remove
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`Page 17 of 20
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`6
`all unreacted titanium as well as titanium nitride. This
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`self-aligned siliciding step greating improves the speed
`of both N-channel and P-channel devices.
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`At this point, transistor formation using the improved
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`CMOSprocess is complete.
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`Thesixth, seventh, and eighth photomasksare used to
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`complete the circuitry in a conventional manner, and
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`correspond respectively to the ninth, tenth, and elev-
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`enth photomasks utilized for the previously-described
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`conventional process.
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`The improved CMOSprocess provides the following
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`advantages over conventional process technology:
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`It permits a dramatic reduction in the number of
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`photomasking steps required in a modern high density
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`CMOSprocess;
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`It is applicable to both low and high density (sub-
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`micron) integration levels;
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`Use of a masked high-energy boron punchthrough
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`implant for N-channel transistors is not required (a un-
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`maskedself-aligned implant after polysilicon deposition
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`is used instead);
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`Individual optimization of N-channel and P-channel
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`transistors is made possible;
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`It allowslightly-doped drain (LDD) design for both
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`N-channel and P-channel transistors (the LDD design
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`makespossible a significant reduction in device length
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`without incurring the detrimental “short channel” ef-
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`fects seen with conventional transistor design, in addi-
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`tion to greatly reducing high electric field hot-electron
`effects);
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`Offset distance of source/drain implants are easily
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`changed independently for N-channel and P-channel
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`devices, allowing greater flexibility for device optimiza-
`tion;
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`The N-channel and P-channeltransistors can be inde-
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`pendently controlled and optimized for best LDD per-
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`formance and reliability (this fact allows maximum
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`shrinkablity for subsequent generation products and
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`reduces retooling for changes in N-channel or P-chan-
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`nel transistors);
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`It is compatible with contemporary IC fabrication
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`equipment, and requires no exotic new equipment;
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`Self-aligned siliciding of all transistor gates, sources
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`and drains is accomplished without adding any masking
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`steps; and
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`The reduced number of process steps and reduced
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`mask count
`improves electrical sort yields, reduces
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`manufacturing costs,
`increases productivity, reduces
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`cycle times through fabrication, reduces total process
`inventory needed for a given run rate, allows more
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`rapid response to process changesin volume quantities,
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`and provides more products having less variation.
`BRIEF DESCRIPTION OF THE DRAWINGS
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`The drawing Figures each show cross-sections of a
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`portion of a semiconductorcircuit device whichutilizes
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`the present invention.
`_
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`FIG. 1 showsa lightly-doped P-type silicon substrate
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`being implanted with phosphorus to create a well of
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`N-type silicon following the growth ofa first layer of
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`pad oxide, deposition of a first silicon nitride layer,
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`masking of the first silicon nitride layer with a first
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`photoresist mask and etchingofthesilicon nitride layer;
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`FIG. 2 shows the semiconductor device of FIG. 1
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