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`United States Patent ou
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`Ueda et al.
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`US005733812A
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`[11] Patent Number:
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`[45] Date of Patent:
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`5,733,812
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`Mar. 31, 1998
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`[54] SEMICONDUCTOR DEVICE WITH A FIELD-
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`EFFECT TRANSISTOR HAVING A LOWER
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`RESISTANCE IMPURITY DIFFUSION
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`LAYER, AND METHOD OF
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`MANUFACTURING THE SAME
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`[75]
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`4,713,356 121987 Hirata eeeeeeseeeserseseneenneeee 437/41
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`4,727,043
`2/1988 Matsumoto etal.
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`4,780,429 10/1988 Roche etal. ....
`437/41
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`5,209,816
`5/1993 Yuetal.
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`156/636
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`5,245,210
`9/1993 Nishigoori
`soe 257/382
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`5,289,443
`2/1994 Jang ...........
`437/40 GS
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`5,340,370
`8/1994 Cadien et al.
`wee 51/308
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`Inventors: Tetsuya Ueda; Takashi Uehara;
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`5,346,584
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`156/636
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`Kousaku Yano; Satoshi Ueda, all of
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`5,447,874=9/1995 Grivna et al. ...esecseseeseeceesse 437/40 GS
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`FOREIGN PATENT DOCUMENTS
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`1/1993
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`[73] Assignee: Matsushita Electric Industrial Co.,
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`Ltd., Osaka, Japan
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`[21] Appl. No.: 571,131
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`[22] Filed:
`Dec. 12, 1995
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`Related U.S. Application Data
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`[63] Continuation-in-part of Ser. No. 340,341, Nov. 14, 1994,
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`abandoned.
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`Foreign Application Priority Data
`[30]
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`[JP]
`Japan «sccsereesenecnsnsenereenees 5-284820
`Nov. 15, 1993
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`Japan occcsssscessesrecsnsssenerenenss 7-278546
`Oct 26, 1995
`ETP]
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`[SL]
`Tint. CRS neseccecccccssssscssnnsesecccesseransanensecs HOIL 21265
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`[52] US. CU. eeeccseesseeneeee 438/289; 438/297; 438/301;
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`438/586; 438/691
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`[58] Field of Search 0.0.0... 437/40 R, 40 GS,
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`437/40 RG, 41 R, 41 GS, 44, 45, 187,
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`979, 228 POL, 29, 228 PL; 156/636.1,
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`645.1; 216/52; 148/DIG. 163; 438/289,
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`297, 301, 586, 691
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`[56]
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`5-13432
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`Japan .
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`Primary Examiner—Brian Dutton
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`Attorney, Agent, or Firm—McDermott. Will & Emery
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`[57]
`ABSTRACT
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`There is formed an isolation which surrounds an active
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`region of a semiconductor substrate. Formed over the active
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`region and onthe isolation, respectively. are a gate electrode
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`and two gate interconnections on both sides thereof.
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`Betweenthe gate electrode and the gate interconnections are
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`located two first interspaces each of which is smaller in
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`width than a specified value and a second interspace which
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`is larger in width than the specified value and interposed
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`between the two first interspaces. In forming side walls on
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`both side faces of the gate electrode and gate interconnec-
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`tions by depositing an insulating film on the substrate, the
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`interspaces are buried with the insulating film.
`first
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`Thereafter, a metal film is deposited on the substrate, fol-
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`lowed by chemical mechanical polishing till
`the gate
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`electrode, gate interconnections, and side walls become
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`exposed. By the process, withdrawn electrodes from a
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`source/drain region for contact with the active region is
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`References Cited
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`formed by self alignment, while the withdrawn electrodes
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`U.S. PATENT DOCUMENTS
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`are insulated from the gate electrode and gate interconnec-
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`tions by the side walls.
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`D/L9BL Nicholas:
`....ccsssssssensseessseee 437/41 GS
`4,287,660
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`4,330,931—S/19B2 Litt ...eseescerssseccersereennesatneeneneneneess 29/571
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`4,584,761—4V1986 WU ....eecseses cee neseeonereerenseee 437/41 R
`11 Claims, 27 Drawing Sheets
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`U.S. Patent
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`U.S. Patent
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`Sheet 5 of 27
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`Sheet 7 of 27
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`5,733,812
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`Sheet 11 of 27
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`Fig.13
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`U.S. Patent
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`Fig.18(a)
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`PRIOR ART
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`Fig.23(a)
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`Sheet 22 of 27
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`Fig2
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`Fig.25
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`Sheet 25 of 27
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`Fig.27
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`Sheet 27 of 27
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`1
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`SEMICONDUCTOR DEVICE WITH A FIELD-
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`LAYER, AND METHOD OF
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`This application is a Continuation-In-Part of application
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`Ser. No. 08/340,341, filed Nov. 14, 1994 now abandoned.
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`BACKGROUND OF THE INVENTION
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`The present invention relates to a semiconductor appara-
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`tus in which a field-effect transistor (FET)is disposed and to
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`developed “salicide” technology for actual use, which is a
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`method wherein a metal with high melting point such as Ti
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`lowering the resistance value of the impurity diffusion layer.
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`there has been introduced a method
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`wherein tungsten is buried in a contact hole by selective
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`combination of the above two technologies, in “A NOVEL
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`DOUBLE-SELF-ALIGNEDTiSi,/TIN CONTACT WITH
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`SELECTIVE CVD W PLUG FOR SUBMICRON DEVICE
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`AND INTERCONNECT APPLICATIONS (EEE. VLSI
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`Symp 5—5 p.41, 1991)” by Martin S. Wangetal.
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`Below, the composite salicide method disclosed in the
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`above document will be described with reference to FIGS.
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`18(a) to 18(). which illustrate the transition of the cross
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`sectional structure of a silicon substrate during the process
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`of manufacturing a semiconductor apparatus.
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`FIG. 18(a) shows a MOStransistor of LDD structure that
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`sion layer includes a low-concentration source/drain 6a and
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`a high-concentration source/drain 6b). The manufacturing
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`method is identical with a conventional method of manu-
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`facturing a CMOSdevice, up to the stage shown in FIG.
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`18(a). Moreover, the doping with As, P, and B and the
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`subsequent thermal treatment have been conducted in accor-
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`dance with the characteristics of a p-channel MOStransistor.
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`Next, as shown in FIG.. 18(b). a Tithin film 30 for a salicide
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`is deposited by sputtering, followed by annealing for sili-
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`cidization as shown in FIG. 18(c). After that, the titanium on
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`the oxide film is removed by wetetching so as to implant N,.
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`Subsequently, TiSi, (silicidized titanium layer) 30 is formed
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`only on the impurity diffusion layers 6 and gate polysilicon
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`4. After a BPSG film 10 was deposited, a contact hole 11 is
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`formed in a desired position of the BPSG film 10 by
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`photolithography and by dry etching (using a gas containing
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`2
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`CHF,+0,as its main component). as shown in FIG. 18(¢).
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`Next, as shown in FIG. 18(e), a W (tungsten) plug 12 is
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`deposited by selective CVD. Then, after depositing a film
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`consisting of TiN/AISiCu/Ti by sputtering, as shown in FIG.
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`18(f). the resulting film is patterned to form a metal inter-
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`connection 13. The above process provides a semiconductor
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`apparatus having the MOStransistor with the salicide struc-
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`ture and the W plug formed by selective CVD.
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`However, the conventional semiconductor apparatus with
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`the structure described above has the following disadvan-
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`tages:
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`(1) Although the formationof a silicide film 7b requires
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`the reaction between the metal with high melting point and
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`the underlying silicon, if the impurity diffusion layer 6 is
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`shallow, it becomesdifficult to form a junction between the
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`metal with high melting point and silicon. However, since a
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`future device requires the formation of an impurity diffusion
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`layer as shallow as possible, it becomesdifficult to form an
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`effective junction, so that the salicide technology is not
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`necessarily compatible with a future device.
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`(2) Since the sllicide layer shows poor immunity to a gas
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`containing CF as its main componentin etching for forming
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`a contact hole, defects such as a pin hole are easily caused.
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`which mayincur an increase in the resistance of the impurity
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`diffusion layer.
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`(3) In a transistor with a shallow junction formed between
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`the metal with high melting point andsilicon, over-etching
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`for surely forming each contact hole cannot be performed
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`satisfactorily in etching for forming a contact hole in the
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`shallow junction therebetween. Consequently, the reliability
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`of an interconnection may be impaired.
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`(4) A thermal treatmentat 650° C.or a higher temperature
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`is required in order to lower the resistance of the silicide
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`layer. Consequently,
`the electrical characteristics of the
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`transistor may be impaired.
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`(5) Thesilicide layer hardly serves as a satisfactory barrier
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`metal layer in forming the W plug by selective CVD, so that
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`its manufacturing conditions for preventing junction leakage
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`become more stringent.
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`(6) With the structure shown in FIG. 18(). the degree of
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`planarization of the base underlying the BPSGfilm 10 is not
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`satisfactory.
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`SUMMARYOF THE INVENTION
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`To attain the above object, a basic method of manufac-
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`turing a semiconductor apparatus according to the present
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`invention comprises: a first step of forming an isolation
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`which surrounds an active region of a semiconductor sub-
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`strate in which a MISFET is to be formed; a second step of
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`introducing an impurity for controlling a threshold of the
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`above MISFET into the above active region; a third step of
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`formingat least three first conductive interconnections serv-
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`ing as a gate electrode of the above MISFET over the above
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`active region and serving as gate interconnections of the
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`above MISFET onthe isolation on both sides of the above
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`active region such that an interspace between the above gate
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`electrode and each of the above gate interconnections is
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`composed ofat least two first interspaces, each of whichis
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`smaller in width than a specified value T. and of a second
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`interspace between the above first interspaces, which is
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`larger in width than the above specified value T; a fourth step
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`of depositing an insulating film over the above first conduc-
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`tive interconnections and the above interspaces; a fifth step
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`of performing anisotropic etching with respect to the above
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`insulatingfilm so as to form side walls composed of remain-
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`ing portions of the above insulating film on both side faces
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`10
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`15
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`45
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`55
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`65
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`Page 29 of 41
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`Page 29 of 41
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`

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`5,733,812
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`3
`of the above first conductive interconnections with the above
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`insulating film buried in the above first interspaces, while
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`partially exposing the active region on both sides of the
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`abovefirst conductive interconnections in the above second
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`interspace; a sixth step of forming two impurity diffusion
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`layers serving as a source/drain region of the above MISFET
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`in those regions of the active region which are located on
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`both sides of the above gate electrode; a seventh step of
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`depositing, after the above sixth step, a metal film over the
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`entire surface of the substrate; and an eighth step of
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`performing, after the above seventh step, chemical mechani-
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`cal polishing for partially removing the above metal film,the
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`abovefirst conductive interconnections, and the above side
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`walls such that, in a plane when the chemical mechanical
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`polishing is completed, the above gate electrode, the above
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`gate interconnections, and the above metal film are partially
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`left and two remaining portions of the above metal film on
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`the above respective impurity diffusion layers, which are
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`surrounded by the above side walls and the above insulating
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`film buried in the first interspaces, form second conductive
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`interconnections electrically isolated from each other.
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`By the method, the second conductive interconnections
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`for contact with the active region function as withdrawn
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`electrodes from the source/drain region of the MISFET.
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`Moreover, the individual withdrawn electrodes are electri-
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`cally isolated from each other by the insulating film buried
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`in the first interspaces, while the individual withdrawn
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`electrodes and the first conductive interconnections (gate
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`electrode and gate interconnections) are isolated from each
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`other by the side walls. Consequently, the withdrawn elec-
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`trodes for contact with the active region, which occupy a
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`large area, can be formed by self alignment, so that inter-
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`connections in the semiconductor apparatus can be minia-
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`turized without incurring a defective connection between the
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`electrodes and the active region.
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`In the above basic method of manufacturing a semicon-
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`ductor apparatus, a LOCOSfilm can be formed in the above
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`first step of forming an isolation. Alternatively, the isolation
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`with trench structure can be formed by forming a trench
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`portion surrounding the above active region in the above
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`semiconductor substrate and then burying the above trench
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`portion.
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`In the above basic method of manufacturing a semicon-
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`ductor apparatus, the first conductive interconnections can
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`be formed from a polysilicon film in the above third step.
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`By the method. it becomes possible to utilize general-
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`purpose polysilicon process, thereby facilitating the manu-
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`facturing of semiconductor apparatus and reducing manu-
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`facturing cost.
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`In the above basic method of manufacturing a semicon-
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`ductor apparatus, the first conductive interconnections can
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`be formed from a two-layer film consisting of a lower
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`conductive layer and an upper insulating layer in the above
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`third step.
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`By the method. in the step of forming the side walls, a
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`damage caused by anisotropic etching to the first conductive
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`interconnections can surely be prevented.
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`The above basic method of manufacturing a semiconduc-
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`tor apparatus further comprisesthe step of, prior to the above
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`fifth step, forming side walls for LDD at least on the side
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`faces of the first conductive interconnection serving as the
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`gate electrode, wherein the side walls formed in the above
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`second step can function only as side walls for isolation.
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`By the method, there is formed an active element having
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`LDDstructure and miniaturized interconnections.
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`In the above basic method of manufacturing a semicon-
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`ductor apparatus, after the above fifth step, the above side
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`4
`walls can be partially processed by dry etching, thereby
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`electrically connecting the abovefirst conductive intercon-
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`nections to the above second conductive interconnections.
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`Bythe method, it becomes possible to electrically isolate
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`the first conductive interconnections from the second con-
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`ductive interconnections by the side walls, while electrically
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`connecting the first conductive interconnections to the sec-
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`ond conductive interconnections in a desired area without
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`forming an additional interconnection. Consequently, the
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`manufacturing process is simplified and the circuit area is
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`further reduced.
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`In the above basic method of manufacturing a semicon-
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`ductor apparatus, in the above third step, the first conductive
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`interconnections which consist of an upper layer composed
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`of an insulating film with a high etching rate and a lower
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`layer composed of a conductive film are formed, the above
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`method further comprising the step of, after the above fifth
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`step, selectively removing only the insulating film with a
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`high etching rate composing the upper layer of the above
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`first conductive interconnections, wherein in the above
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`seventh step, the above metal film is composed of a metal
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`material with a low resistance and in the above eighth step,
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`the metal film over the above active region is isolated from
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`the metal film over the first conductive interconnections by
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`the above side walls and the above second conductive
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`interconnections are composed only of the above metal film,
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`while chemical mechanical polishing can be performed so as
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`to composethe above first conductive interconnections of a
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`multi-layer film of the above first conductive film and the
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`above metal film.
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`By the method, the resistance of the active region, i.e., the
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`resistance of the region of the diffusion layer of the active
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`element can be reduced without performing high-
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`temperature thermal
`treatment such as salicide process.
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`Moreover, the underlying semiconductor substrate is not
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`consumed, so that an active element with minimum junction
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`leakage can be obtained.
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`To reduce the capacitance of a gate electrode, there are
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`also provided the following second and third methods of
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`manufacturing semiconductor apparatus. The second
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`method of manufacturing a semiconductor apparatus com-
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`prises the steps of: forming a circumferential
`isolation
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`region which surrounds an active region of a semiconductor
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`substrate in which a MISFET is to be formed; introducing an
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`impurity for controlling a threshold of the above MISFET
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`into the above active region; forming a stepped insulating
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`film consisting of a portion which is sufficiently thin to
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`enable the function of the above MISFET and a portion
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`which is sufficiently thick to disenable the function of the
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`MISFET and a gate electrode; forming side walls from an
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`insulating material on both sides of the above gate electrode;
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`forming two impurity diffusion layers which serve as a
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`source/drain region of the above MISFET in those regions of
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`the above active region which are located on both sides of
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`the above gate electrode; depositing a metal film over the
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`entire surface of the substrate after forming the above gate
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`electrode, the above side walls, and the above circumferen-
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`tial isolation region; partially removing the above metal
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`film, the above circumferential isolation region, the above
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`gate electrode, and the above side walls by chemical
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`mechanical polishing such that, in a plane when the chemi-
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`cal mechanical polishing is completed, two remaining por-
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`tions of the above metal film on the above respective
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`impurity diffusion layers are surrounded by the above gate
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`electrode and the above circumferential isolation region and
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`electrically isolated from each other.
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`The third method of manufacturing a semiconductor
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`apparatus comprises the steps of: forming a circumferential
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`10
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`20
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`35
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`50
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`65
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`Page 30 of 41
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`5
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`isolation region which surrounds an active region of a
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`semiconductor substrate in which a MISFET is to be formed;
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`introducing an impurity for controlling a threshold of the
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`above MISFET into the above active region so as to form,
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`in a region in which a gate electrode is to be formed, a region
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