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`US0057338 12A
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`[11] Patent Number:
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`[45] Date of Patent:
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`5,733,812
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`Mar. 31, 1998
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`4,713,356 12/1987
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`Z1988 Matsumoto et al.
`4,727,043
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`4,780,429 10/1988 Roche et al.
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`5,209,816
`5/1993
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`257/382
`5,245,210
`9/1993
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`437/40 GS
`5,289,443 H1994
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`5,447,874
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`9/1995 Grivna et al.
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`FOREIGN PATENT DOCUMENTS
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`1/1993
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`United States Patent
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`Ueda et al.
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`1191
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`[54] SEMICONDUCTOR DEVICE WITH A FIELD-
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`EFFECT TRANSISTOR HAVING A LOWER
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`RESISTANCE IMPURITY DIFFUSION
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`LAYER, AND METHOD OF
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`MANUFACTURING THE SAME
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`Inventors: Tetsuya Ueda; Takashi Uehara;
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`Kousaku Yano; Satoshi Ueda. all of
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`Osaka. Japan
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`Assignee: Matsushita Electric Industrial Co.,
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`Ltd.. Osaka. Japan
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`App]. No.2 571,131
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`[22] Filed:
`Dec. 12, 1995
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`Related U.S. Application Data
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`[63] Continuation-in-part of Ser. No. 340341, Nov. 14, 1994.
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`abandoned.
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`[30]
`Foreign Application Priority Data
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`[JP]
`Japan .................................... 5-284820
`Nov. 15, 1993
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`Japan .................................... 7-278546
`Oct. 26, 1995
`[JP]
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`[51]
`Int. Cl.‘ ................................................... H01L 21/265
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`[52] U.S. Cl.
`.......................... 438/289; 433/297-, 438/301;
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`438/586; 438/691
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`[58] Field of semi. ............................. 437/40 R. 40 GS.
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`437/40 no, 41 R, 41 GS. 44, 45, 137.
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`979. 223 POL. 29. 228 PL; 156/636.1.
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`645.1; 216/52; 148/DIG. 163; 433/239.
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`297. 301.586. 691
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`[56]
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`4,287,660
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`4,330,931
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`4,584,761
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`References Cited
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`U.S. PATENT DOCUMENTS
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`9/1981 Nicholas ............................ 437/41 GS
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`5/1982 Liu
`....... 29/571
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`4/1986 Wu ........................................ 437/41 R
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`5-13432
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`Japan.
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`Primary Examiner—Brian Duuon
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`Attome}; Agent, or Firm—McDermott. Will & Emery
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`[57]
`ABSTRACT
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`There is formed an isolation which surrounds an active
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`region of a semiconductor substrate. Formed over the active
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`region and on the isolation. respectively. are a gate electrode
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`and two gate interconnections on both sides thereof.
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`Between the gate electrode and the gate interconnections are
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`located two first interspaces each of which is smaller in
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`width t;han a specified value and a second interspace which
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`is larger in width than the specified value and interposed
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`between the two lirst interspaces. In forming side wmls on
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`both side faces of the gate electrode and gate interconnec-
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`tions by depositing an insulating film on the substrate. the
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`interspaces are buried with the insulating film.
`first
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`Thereafter. a metal film is deposited on the substrate. fol-
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`lowed by chemical mechanical polishing till
`the gate
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`electrode. gate interconnections. and side walls become
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`exposed. By the process. withdrawn electrodes from a
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`source/drain region for contact with the active region is
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`formed by self alignment. while the withdrawn electrodes
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`are insulated from the gate electrode and gate interconnec-
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`tions by the side walls.
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`11 Claims, 27 Drawing Sheets
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`U.S. Patent
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`U.S. Patent
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`Mar. 31, 1993
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`Sheet 3 of 27
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`U.S. Patent
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`Mar. 31, 1993
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`Sheet 4 of 27
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`Sheet 6 of 27
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`Sheet 7 of 27
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`Sheet 8 of 27
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`U.S. Patent
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`Mar. 31, 1993
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`Sheet 9 of 27
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`5,733,812
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`U.S. Patent
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`Mar. 31, 1993
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`Sheet 10 of 27
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`U.S. Patent
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`Mar. 31, 1993
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`Sheet 11 of 27
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`Fig.13
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`U.S. Patent
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`U.S. Patent
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`Mar. 31, 1998
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`Sheet 13 of 27
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`U.S. Patent
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`Mar. 31, 1998
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`Sheet 14 of 27
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`U.S. Patent
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`Mar. 31, 1998
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`Sheet 15 of 27
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`Page 16 of 41
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`U.S. Patent
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`Mar. 31, 1993
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`Sheet 16 of 27
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`5,733,812
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`U.S. Patent
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`Mar. 31, 1998
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`Sheet 17 of 27
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`U.S. Patent
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`Mar. 31, 1993
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`Sheet 13 of 27
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`U.S. Patent
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`Mar. 31, 1993
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`Sheet 20 of 27
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`5,733,812
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`Page 21 of 41
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`U.S. Patent
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`Mar. 31, 1998
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`Sheet 21 of 27
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`5,733,812
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`U.S. Patent
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`Mar. 31, 1998
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`Sheet 22 of 27
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`5,733,812
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`Page 23 of 41
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`Page 23 of 41
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`U.S. Patent
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`Mar. 31, 1993
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`Sheet 23 of 27
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`U.S. Patent
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`Mar. 31, 1998
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`Sheet 24 of 27
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`U.S. Patent
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`Mar. 31, 1998
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`Sheet 25 of 27
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`U.S. Patent
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`Mar. 31, 1993
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`Sheet 26 of 27
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`Page 27 of 41
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`U.S. Patent
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`Mar. 31, 1998
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`Sheet 27 of 27
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`1
`SEMICONDUCTOR DEVICE WITH A FIELD-
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`Cl-lF,+O2 as its main component). as shown in FIG. 18(d).
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`ing portions of the above insulating film on both side faces
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`10
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`SS
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`65
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`This application is a Continuation-In—Part of application
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`Ser. No. 08/340341. filed Nov. 14. 1994 now abandoned.
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`BACKGROUND OF THE INVENTION
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`The present invention relates to a semiconductor appara-
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`tus in which a field-effect transistor (FET) is disposed and to
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`a method of manufacturing the same. More particularly. it
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`relates to a method of lowering the resistance of an impurity
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`dilfusion layer in the FET.
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`With the increasing miniaturization of a large-scale semi-
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`conductor integrated circuit in recent years. a MISFET has
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`been reduced in size by lowering the resistances of its
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`impurity dilfusion layer and gate interconnection. To lower
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`the resistance of an impurity diffusion layer. there has been
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`developed “salicide” technology for actual use. which is a
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`method wherein a metal with high melting point such as Ti
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`is deposited on the impurity diffusion layer in a silicon
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`substrate and then the vicinity of the Si—Ti
`interface is
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`silicidized through the mutual dilfusion of Si and Ti between
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`the silicon substrate and the resulting Ti film.
`thereby
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`lowering the resistance value of the impurity dilfusion layer.
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`On the other hand.
`there has been introduced a method
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`wherein tungsten is buried in a contact hole by selective
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`CVD or blanket tungsten is used to fill up the contact hole.
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`since the aspect ratio of the contact hole has been increased
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`in order to
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`nection and silicon.
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`There has also been proposed a method. which is a
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`combination of the above two technologies. in “A NOVEL
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`DOUBLE-SELF-ALIGNED TiSi2lI‘iN CONTACT WITH
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`SELECTIVE CVD W PLUG FOR SUBMICRON DEVICE
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`AND 1NT'ERCONNECT APPLICAIFIONS (IEEE. VLSI
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`Syrup 5—5 p.41. 1991)" by Martin S. Wang et al.
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`Below. the composite salicide method disclosed in the
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`above document will be described with reference to FIGS.
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`l8(a) to 180‘). which illustrate the transition of the cross
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`sectional structure of a silicon substrate during the process
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`of manufacturing a semiconductor apparatus.
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`FIG. 18-(a) shows a MOS transistor of LDD structure that
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`has been formed previously. In the drawing. 1 designates a
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`silicon substrate. 2 designates an isolation formed by a
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`LOCOS method. 3 designates a gate oxide film. 4 designates
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`a polysilicon electrode. 5 designates a side wall. and 6
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`designates an impurity diffusion layer (the impurity difl’u-
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`sion layer includes a low-concentration source/drain 6a and
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`a high-concentration sourceldrain 6b). The manufacturing
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`method is identical with a conventional method of manu-
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`factming a CMOS device. up to the stage shown in FIG.
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`18(a). Moreover, the doping with As. P. and B and the
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`subsequent thermal treatment have been conducted in accor-
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`dance with the characteristics of a p-channel MOS transistor.
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`Next. as shown in FIG.. 18(b). aTi thin filru 30 for a salicide
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`is deposited by sputtering. followed by annealing for sili-
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`cidization as shown in FIG. 18(c). After that. the titanium on
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`the oxide film is removed by wet etching so as to implant N2.
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`Subsequently. TiSi, (silicidized titanium layer) 30 is formed
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`only on the impurity dilfusion layers 6 and gate polysilicon
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`4. After a BPSG film 10 was deposited. a contact hole 11 is
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`forrued in a desired position of the BPSG film 10 by
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`photolithography and by dry etching (using a gas containing
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`Page 29 of 41
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`Page 29 of 41
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`

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`5,733,812
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`3
`of the above first conductive interconnections with the above
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`insulating film buried in the above first interspaces. while
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`partially exposing the active region on both sides of the
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`above first conductive interconnections in the above second
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`interspace; a sixth step of forming two impurity diffusion
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`layers serving as a source/drain region of the above MISFET
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`in those regions of the active region which are located on
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`both sides of the above gate electrode; a seventh step of
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`depositing. after the above sixth step. a metal film over the
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`entire surface of the substrate; and an eighth step of
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`performing. after the above seventh step. chemical mechani—
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`cal polishing for partially removing the above metal film. the
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`above first conductive interconnections. and the above side
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`walls such that. in a plane when the chemical mechanical
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`polishing is completed. the above gate electrode. the above
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`gate interconnections. and the above metal film are partially
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`left and two remaining por1:ions of the above metal film on
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`the above respective impurity diffusion layers. which are
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`surrounded by the above side walls and the above insulating
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`film buried in the first interspaces. form second conductive
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`interconnections electrically isolated from each other.
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`By the method. the second conductive interconnections
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`for contact with the active region function as withdrawn
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`electrodes from the source/drain region of the MISFET.
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`Moreover. the individual withdrawn electrodes are electri-
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`cally isolated from each other by the insulating film buried
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`in the first interspaces. while the individual withdrawn
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`electrodes and the first conductive interconnections (gate
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`electrode and gate interconnections) are isolated from each
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`other by the side walls. Consequently. the withdrawn elec-
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`trodes for contact with the active region. which occupy a
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`large area. can be formed by self alignment. so that inter-
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`connections in the semiconductor apparatus can be minia-
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`turized without incurring a defective connection between the
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`electrodes and the active region.
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`In the above basic method of manufacturing a semicon-
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`ductor apparatus. a LOCOS film can be formed in the above
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`first step of forming an isolation. Alternatively. the isolation
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`with trench structure can be formed by forming a trench
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`portion surrounding the above active region in the above
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`semiconductor subst:rate and then burying the above trench
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`portion.
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`In the above basic method of manufacturing a semicon-
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`ductor apparatus. the first conductive interconnections can
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`be formed from a polysilicon film in the above third step.
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`By the method. it becomes possible to utilize general-
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`purpose polysilicon process. thereby facilitating the manu-
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`facturing of semiconductor apparatus and reducing manu-
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`facturing cost.
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`In the above basic method of manufacturing a semicon-
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`ductor apparatus. the first conductive interconnections can
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`be formed from a two—layer film consisting of a lower
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`conductive layer and an upper insulating layer in the above
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`third step.
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`By the method. in the step of forming the side walls. a
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`damage caused by anisotropic etching to the first conductive
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`interconnections can surely be prevented.
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`The above basic method of manufacturing a semiconduc-
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`tor apparatus further comprises the step of. prior to the above
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`fifth step. forming side walls for LDD at least on the side
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`faces of the first conductive interconnection serving as the
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`gate electrode. wherein the side walls formed in the above
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`second step can function only as side walls for isolation.
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`By the method. there is formed an active element having
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`LDD structure and miniaturized interconnections.
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`In the above basic method of manufacturing a semicon-
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`ductor apparatus. after the above fifth step. the above side
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`4
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`walls can be partially processed by dry etching. thereby
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`electrically connecting the above first conductive intercon-
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`nections to the above second conductive interconnections.
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`By the method. it becomes possible to electrically isolate
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`the first conductive interconnections from the second con-
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`ductive interconnections by the side walls. While electrically
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`connecting the first conductive interconnections to the sec-
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`ond conductive interconnections in a desired area without
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`forming an additional interconnection. Consequently. the
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`manufacturing process is simplified and the circuit area is
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`further reduced.
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`In the above basic method of manufacturing a semicon-
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`ductor apparatus. in the above third step. the first conductive
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`interconnections which consist of an upper layer composed
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`of an insulating film with a high etching rate and a lower
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`layer composed of a conductive film are formed. the above
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`method further comprising the step of. after the above fifth
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`step. selectively removing only the insulating film with a
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`high etching rate composing the upper layer of the above
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`first conductive interconnections. wherein in the above
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`seventh step. the above metal film is composed of a metal
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`material with a low resistance and in the above eighth step.
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`the metal film over the above active region is isolated from
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`the metal film over the first conductive interconnections by
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`the above side walls and the above second conductive
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`interconnections are composed only of the above metal film.
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`while chemical mechanical polishing can be performed so as
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`to compose the above first conductive interconnections of a
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`multi-laya film of the above first conductive film and the
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`above metal film.
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`By the method. the resistance of the active region. i.e.. the
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`resistance of the region of the diffusion layer of the active
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`element can be reduced without performing high-
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`temperature thermal
`treatment such as salicide process.
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`Moreover. the underlying semiconductor substrate is not
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`consumed. so that an active element with minimum junction
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`leakage can be obtained.
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`To reduce the capacitance of a gate electrode. there are
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`also provided the following second and third methods of
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`manufacturing semiconductor apparatus. The second
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`method of manufacturing a semiconductor apparatus com-
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`prises the steps of: forming a circumferential
`isolation
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`region which surrounds an active region of a semiconductor
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`substrate in which a MISFET is to be formed; introducing an
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`impurity for controlling a threshold of the above MISFEI‘
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`into the above active region; forming a stepped insulating
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`film consisting of a portion which is sufliciently thin to
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`enable the function of the above MISFET and a portion
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`which is sufliciently thick to disenable the function of the
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`MISFEF and a gate electrode; forming side walls from an
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`insulating material on both sides of the above gate electrode;
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`forming two impurity diffusion layers which serve as a
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`source/drain region of the above MISFET in those regions of
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`the above active region which are located on both sides of
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`the above gate electrode; depositing a metal film over the
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`entire surface of the substrate after forming the above gate
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`electrode. the above side walls. and the above circumferen-
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`tial isolation region; partially removing the above metal
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`film. the above circumferential isolation region. the above
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`gate electrode. and the above side walls by chemical
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`mechanical polishing such that. in a plane when the chemi-
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`cal mechanical polishing is completed. two remaining por-
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`tions of the above metal film on the above respective
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`impurity diffusion layers are surrounded by the above gate
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`electrode and the above circumferential isolation region and
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`electrically isolated from each other.
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`The third method of manufacturing a semiconductor
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`apparatus comprises the steps of: forming a circumferential
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`20
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`25
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`30
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`35
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`45
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`50
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`55
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`65
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`Page 30 of 41
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`Page 30 of 41
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`5.733.812
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`5
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`isolation region which surrounds an active region of a
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`semiconductor substrate in which a MISFET is to be formed;
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`introducing an impurity for controlling a threshold of the
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`above MISFEI‘ into the above active region so as to form.
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