`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`Taiwan Semiconductor Manufacturing Company, Ltd.
`
`Petitioner
`
`v.
`
`Godo Kaisha IP Bridge 1
`
`Patent Owner
`
`
`
`Patent No. 7,126,174
`Filing Date: November 24, 2004
`Issue Date: October 24, 2006
`
`Title: SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING
`THE SAME
`
`
`
`Inter Partes Review No. IPR2016-01246
`
`
`
`CORRECTED DECLARATION OF DR. SANJAY KUMAR BANERJEE,
`PH.D. IN SUPPORT OF PETITION FOR INTER PARTES REVIEW OF
`UNITED STATES PATENT NO. 7,126,174
`
`
`
`
`
`
`
`Page 1 of 204
`
`TSMC Exhibit 1004
`
`CORRECTED
`
`

`

`TABLE OF CONTENTS
`
`I.
`
`II.
`
`INTRODUCTION ......................................................................................... 1
`
`SUMMARY OF OPINIONS......................................................................... 2
`
`III. BACKGROUND AND QUALIFICATIONS .............................................. 2
`
`A.
`
`B.
`
`C.
`
`Background ........................................................................................... 2
`
`Previous Expert Witness Experience .................................................... 6
`
`Compensation ........................................................................................ 6
`
`IV. MATERIALS REVIEWED .......................................................................... 7
`
`V.
`
`LEGAL STANDARDS .................................................................................. 9
`
`A. Anticipation .........................................................................................10
`
`B. Obviousness .........................................................................................11
`
`VI. TECHNOLOGICAL BACKGROUND .....................................................15
`
`A.
`
`B.
`
`1.
`
`2.
`
`C.
`
`Integrated Circuits ...............................................................................15
`
`Isolation Structures ..............................................................................18
`
`LOCOS ................................................................................................19
`
`Shallow Trench Isolation ....................................................................20
`
`Insulating Sidewalls ............................................................................22
`
`VII. THE ’174 PATENT ......................................................................................25
`
`A. Disclosed “Conventional” Devices .....................................................25
`
`B.
`
`C.
`
`Representative Embodiment ...............................................................27
`
`Japanese Application No. 7-192181 Does not Disclose All the
`Features of the Challenged Claims......................................................27
`
`VIII. LEVEL OF ORDINARY SKILL ...............................................................30
`
`
`
`
`
`Page 2 of 204
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`

`

`IX. ANALYSIS ...................................................................................................31
`Lee (U.S. Patent No. 5,153,145) .........................................................31
`
`A.
`
`B.
`
`Noble (U.S. Patent No. 5,539,229) ......................................................32
`
`C. Ogawa (U.S. Patent No. 4,506,434) ....................................................33
`
`D.
`
`The combined teachings of Lee and Noble .........................................35
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`7.
`
`8.
`
`9.
`
`Claim 1 is obvious over Lee and Noble ....................................43
`
`Claim 2 is obvious over Lee and Noble ....................................57
`
`Claim 3 is obvious over Lee and Noble ....................................58
`
`Claim 5 is obvious over Lee and Noble ....................................59
`
`Claim 6 is obvious over Lee and Noble ....................................62
`
`Claim 7 is obvious over Lee and Noble ....................................63
`
`Claim 9 is obvious over Lee and Noble ....................................65
`
`Claim 10 is obvious over Lee and Noble ..................................67
`
`Claim 11 is obvious over Lee and Noble ..................................70
`
`10. Claim 12 is obvious over Lee and Noble ..................................72
`
`11. Claim 14 is obvious over Lee and Noble ..................................74
`
`12. Claim 15 is obvious over Lee and Noble ..................................76
`
`13. Claim 16 is obvious over Lee and Noble ..................................78
`
`14. Claim 17 is obvious over Lee and Noble ..................................82
`
`15. Claim 18 is obvious over Lee and Noble ..................................84
`
`E.
`
`The combined teachings of Lee and Ogawa .......................................85
`
`1.
`
`2.
`
`Claim 1 is obvious over Lee and Ogawa ..................................91
`
`Claim 2 is obvious over Lee and Ogawa ..................................94
`
`
`
`ii
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`Page 3 of 204
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`

`

`3.
`
`4.
`
`5.
`
`6.
`
`7.
`
`8.
`
`9.
`
`Claim 3 is obvious over Lee and Ogawa ..................................94
`
`Claim 5 is obvious over Lee and Ogawa ..................................95
`
`Claim 6 is obvious over Lee and Ogawa ..................................95
`
`Claim 7 is obvious over Lee and Ogawa ..................................96
`
`Claim 9 is obvious over Lee and Ogawa ..................................96
`
`Claim 10 is obvious over Lee and Ogawa ................................97
`
`Claim 11 is obvious over Lee and Ogawa ................................98
`
`10. Claim 12 is obvious over Lee and Ogawa ................................99
`
`11. Claim 14 is obvious over Lee and Ogawa ................................99
`
`12. Claim 15 is obvious over Lee and Ogawa ................................99
`
`13. Claim 16 is obvious over Lee and Ogawa ..............................100
`
`14. Claim 17 is obvious over Lee and Ogawa ..............................100
`
`15. Claim 18 is obvious over Lee and Ogawa ..............................101
`
`X. CONCLUSION ..........................................................................................101
`
`
`I.
`
`INTRODUCTION ......................................................................................... 1
`
`II.
`
`SUMMARY OF OPINIONS......................................................................... 2
`
`III. BACKGROUND AND QUALIFICATIONS .............................................. 2
`
`A.
`
`B.
`
`C.
`
`Background ........................................................................................... 2
`
`Previous Expert Witness Experience .................................................... 6
`
`Compensation ........................................................................................ 6
`
`IV. MATERIALS REVIEWED .......................................................................... 7
`
`V.
`
`LEGAL STANDARDS .................................................................................. 9
`
`
`
`iii
`
`Page 4 of 204
`
`

`

`A. Anticipation .........................................................................................10
`
`B. Obviousness .........................................................................................11
`
`VI. TECHNOLOGICAL BACKGROUND .....................................................15
`
`A.
`
`B.
`
`1.
`
`2.
`
`C.
`
`Integrated Circuits ...............................................................................15
`
`Isolation Structures ..............................................................................18
`
`LOCOS ................................................................................................19
`
`Shallow Trench Isolation ....................................................................20
`
`Insulating Sidewalls ............................................................................22
`
`VII. THE ’174 PATENT ......................................................................................25
`
`A. Disclosed “Conventional” Devices .....................................................25
`
`B.
`
`C.
`
`Representative Embodiment ...............................................................27
`
`Japanese Application No. 7-192181 Does not Disclose All the
`Features of the Challenged Claims......................................................27
`
`VIII. LEVEL OF ORDINARY SKILL ...............................................................30
`
`IX. ANALYSIS ...................................................................................................31
`Lee (U.S. Patent No. 5,153,145) .........................................................31
`
`A.
`
`B.
`
`Noble (U.S. Patent No. 5,539,229) ......................................................32
`
`C. Ogawa (U.S. Patent No. 4,506,434) ....................................................33
`
`D.
`
`The combined teachings of Lee and Noble .........................................35
`
`1.
`
`2.
`
`3.
`
`4.
`
`Claim 1 is obvious over Lee and Noble ....................................43
`
`Claim 2 is obvious over Lee and Noble ....................................57
`
`Claim 3 is obvious over Lee and Noble ....................................58
`
`Claim 5 is obvious over Lee and Noble ....................................59
`
`
`
`iv
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`Page 5 of 204
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`5.
`
`6.
`
`7.
`
`8.
`
`9.
`
`Claim 6 is obvious over Lee and Noble ....................................62
`
`Claim 7 is obvious over Lee and Noble ....................................63
`
`Claim 9 is obvious over Lee and Noble ....................................65
`
`Claim 10 is obvious over Lee and Noble ..................................67
`
`Claim 11 is obvious over Lee and Noble ..................................70
`
`10. Claim 12 is obvious over Lee and Noble ..................................72
`
`11. Claim 14 is obvious over Lee and Noble ..................................74
`
`12. Claim 15 is obvious over Lee and Noble ..................................76
`
`13. Claim 16 is obvious over Lee and Noble ..................................78
`
`14. Claim 17 is obvious over Lee and Noble ..................................82
`
`15. Claim 18 is obvious over Lee and Noble ..................................84
`
`E.
`
`The combined teachings of Lee and Ogawa .......................................85
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`7.
`
`8.
`
`9.
`
`Claim 1 is obvious over Lee and Ogawa ..................................91
`
`Claim 2 is obvious over Lee and Ogawa ..................................94
`
`Claim 3 is obvious over Lee and Ogawa ..................................94
`
`Claim 5 is obvious over Lee and Ogawa ..................................95
`
`Claim 6 is obvious over Lee and Ogawa ..................................95
`
`Claim 7 is obvious over Lee and Ogawa ..................................96
`
`Claim 9 is obvious over Lee and Ogawa ..................................96
`
`Claim 10 is obvious over Lee and Ogawa ................................97
`
`Claim 11 is obvious over Lee and Ogawa ................................98
`
`10. Claim 12 is obvious over Lee and Ogawa ................................99
`
`11. Claim 14 is obvious over Lee and Ogawa ................................99
`
`
`
`v
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`Page 6 of 204
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`

`

`12. Claim 15 is obvious over Lee and Ogawa ................................99
`
`13. Claim 16 is obvious over Lee and Ogawa ..............................100
`
`14. Claim 17 is obvious over Lee and Ogawa ..............................100
`
`15. Claim 18 is obvious over Lee and Ogawa ..............................101
`
`X. CONCLUSION ..........................................................................................101
`
`
`
`vi
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`Page 7 of 204
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`

`

`I, Dr. Sanjay Kumar Banerjee, Ph.D., declare as follows:
`
`I.
`
`Introduction
`
`1. My name is Dr. Sanjay Kumar Banerjee. I have been asked to submit
`
`this declaration on behalf of Taiwan Semiconductor Manufacturing Company, Ltd.
`
`(“TSMC” or “Petitioner”) in connection with a petition for inter partes review of
`
`U.S. Patent No. 7,126,174 (“the ’174 patent”), which I have been told is being
`
`submitted to the Patent Trial and Appeal Board of the United States Patent and
`
`Trademark Office by TSMC.
`
`2.
`
`I have been retained as a technical expert by TSMC to study and
`
`provide my opinions on the technology claimed in, and the patentability or non-
`
`patentability of, claims 1–3, 5–7, 9–12, and 14–18 in the ’174 patent (“the
`
`Challenged Claims”).
`
`3.
`
`I understand the ’174 patent is related to U.S. Patent Nos. 6,967,409
`
`(the ’409 patent), 6,709,950 (the ’950 patent), and 6,281,562 (the ’562 patent) and
`
`also claims the benefit of priority to two Japanese applications, JP 7-192181,
`
`which was filed on July 27, 1995, and JP 7-330112, which was filed on December
`
`19, 1995.
`
`
`
`
`
`Page 8 of 204
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`

`

`II.
`
`Summary of Opinions
`
`4.
`
`This declaration is directed to the Challenged Claims of the ’174
`
`patent, and sets forth certain opinions I have formed, the conclusions I have
`
`reached, and the bases for each.
`
`5.
`
`Based on my experience, knowledge of the art at the relevant time,
`
`analysis of prior art references, and the understanding a person of ordinary skill in
`
`the art would have of the claim terms in light of the specification, it is my opinion
`
`that all of the Challenged Claims of the ’174 patent are unpatentable as being
`
`obvious over the prior art references discussed below.
`
`6.
`
`Based on my experience, knowledge of the art at the relevant time,
`
`and the plain and ordinary meaning of the claims as they would have been
`
`understood by a person of ordinary skill in the art, it is further my opinion that the
`
`Challenged Claim features that do not appear in Japanese Patent Application No.
`
`7-192181.
`
`III. Background and Qualifications
`A. Background
`I am currently the Cockrell Family Chair Professor of Electrical and
`7.
`
`Computer Engineering at the University of Texas at Austin. At UT Austin, I am
`
`also the director of the Microelectronics Research Center. I have been a faculty
`
`member at UT Austin since 1987.
`
`
`
`2
`
`Page 9 of 204
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`

`

`8.
`
`I have also been active in industries related to the relevant field of art.
`
`As a Member of the Technical Staff, Corporate Research, Development and
`
`Engineering of Texas Instruments Incorporated from 1983–1987, I worked on
`
`polysilicon transistors and dynamic random access trench memory cells used by
`
`Texas Instruments in the world’s first 4-Megabit DRAM, for which I was co-
`
`recipient of the Best Paper Award, IEEE International Solid State Circuits
`
`Conference, 1986.
`
`9.
`
`I received a B.Tech from the Indian Institute of Technology,
`
`Kharagpur, an M.S. and Ph.D. from the University of Illinois at Urbana-
`
`Champaign, all in Electrical Engineering.
`
`10.
`
`I am a leading researcher and educator in various areas of transistor
`
`device fabrication technology, including the fabrication, characterization and
`
`applications of memory devices, transistors, and nanotechnology. My research has
`
`been funded by the Texas Advanced Technology Program (ATP), the Texas
`
`Higher Education Coordinating Board, the National Science Foundation, the
`
`SEMATECH (Semiconductor Manufacturing Technology) consortium, the SRC
`
`(Semiconductor Research Corporation) consortium, DARPA, and the Department
`
`of Energy, among others.
`
`11. At the University of Texas, I am the director of the Microelectronics
`
`Research Center, comprised of faculty colleagues, graduate, and undergraduate
`
`
`
`3
`
`Page 10 of 204
`
`

`

`students. I also serve as the director of the South West Academy of
`
`Nanoelectronics, one of three centers in the United States to develop a replacement
`
`for MOSFETs.
`
`12.
`
`I have published over 1,000 technical articles, many related to
`
`semiconductor fabrication technology, most at highly competitive refereed
`
`conferences and rigorously reviewed journals. I have also published 8 books or
`
`chapters on transistor device physics and fabrication, and have supervised over 50
`
`Ph.D. and 60 MS students.
`
`13.
`
`I have been a member of scientific organizations and committees,
`
`including the IEEE Dan Noble Award Committee from 2010–2013, serving as
`
`Chair from 2012–2013, the International Technology Roadmap for
`
`Semiconductors, the International Conference on MEMS (Microelectromechanical
`
`Systems) and Nanotechnology, the IEEE International Conference on
`
`Communications, Computers, Devices, the International Electron Devices
`
`Meeting, the International Conference on Simulation of Semiconductor Processes
`
`and Devices, and the IEEE Symposium on VLSI (Very-Large-Scale Integration)
`
`Technology.
`
`14.
`
`I have served as the Session Chair for the “Device Technology”
`
`Session conducted at the IEEE International Electron Devices Meeting in 1989–
`
`1990. I have also served as the General Chairman for the IEEE University
`
`
`
`4
`
`Page 11 of 204
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`

`

`Government Industry Microelectronics Symposium in 1994–1995, and Chair of the
`
`IEEE Device Research Conference.
`
`15.
`
`I have served on the Technical Advisory Boards of AstroWatt, DSM
`
`Semiconductors, Cambrios, Nanocoolers Inc., BeSang Memories, Organic ID and
`
`ITU Ventures; Gerson Lehmann Group, NY; Austin Community College; Asia
`
`Pacific IIT; Rochester Institute of Technology, and HSMC Foundry.
`
`16.
`
`I received the Engineering Foundation Advisory Council Halliburton
`
`Award (1991), the Texas Atomic Energy Fellowship (1990–1997), Cullen
`
`Professorship (1997–2001) and the Hocott Research Award from UT Austin
`
`(2007). I also received the IEEE Grove Award (2014), Distinguished Alumnus
`
`Award, IIT (2005), Industrial R&D 100 Award (2004), ECS Callinan Award,
`
`2003, IEEE Millennium Medal, 2000, NSF Presidential Young Investigator Award
`
`in 1988, and several SRC Inventor Recognition and Best Paper Awards.
`
`17.
`
`I was a Distinguished Lecturer for IEEE Electron Devices Society,
`
`and am a Fellow of the Institute of the Electrical and Electronics Engineers (IEEE),
`
`the American Physical Society (APS) and the American Association for the
`
`Advancement of Science (AAAS).
`
`18.
`
`I am the inventor or co-inventor of over 30 United States patents in
`
`various areas of transistor device fabrication technology.
`
`
`
`5
`
`Page 12 of 204
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`

`

`19. Additional details about my employment history, fields of expertise,
`
`and publications are further included in my curriculum vitae (attached as Appendix
`
`A).
`
`B.
`20.
`
`Previous Expert Witness Experience
`
`I have served as an expert witness since the mid 1990’s. In the last ten
`
`years or so, I have testified at the International Trade Commission three times, and
`
`the Northern District of California once. In addition, I have been deposed six times
`
`on patents related to CMOS and semiconductor memories such as flash and
`
`DRAMs. Several of these have been IPR cases.
`
`C. Compensation
`I am being compensated for services provided in this matter at my
`21.
`
`usual and customary rate of $500 per hour plus travel expenses. My compensation
`
`is not conditioned on the conclusions I reach as a result of my analysis or on the
`
`outcome of this matter. Similarly, my compensation is not dependent upon and in
`
`no way affects the substance of my statements in this declaration.
`
`22.
`
`I have no financial interest in Petitioner or any of its subsidiaries. I
`
`also do not have any financial interest in Patent Owner Godo Kaisha IP Bridge 1. I
`
`do not have any financial interest in the ’174 patent and have not had any contact
`
`with any of the named inventors of the ’174 patent (Mizuki Segawa, Isao
`
`
`
`6
`
`Page 13 of 204
`
`

`

`Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita,
`
`Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, and Michikazu Matsumoto).
`
`IV. Materials Reviewed
`
`23.
`
`In forming my opinions, I have reviewed the following references:
`
`• The ’174 patent (which I have been told is Exhibit 1001 to TSMC’s
`
`petition);
`
`• U.S. Patent No. 5,153,145 to Lee et al. (“Lee,” which I have been told
`
`is Exhibit 1002 to TSMC’s petition);
`
`• U.S. Patent No. 3,617,824 to Shinoda et al. (“Shinoda,” which I have
`
`been told is Exhibit 1003 to TSMC’s petition);
`
`• J.A. Appels et al., Some Problems of MOS Technology, Philips Tech.
`
`Rev. vol. 31 nos. 7–9, pp. 225–36 (1970) (“Appels,” which I have been
`
`told is Exhibit 1005 to TSMC’s petition);
`
`• U.S. Patent No. 4,110,899 to Nagasawa et al. (“Nagasawa,” which I
`
`have been told is Exhibit 1006 to TSMC’s petition);
`
`• U.S. Patent No. 3,787,251 to Brand et al. (“Brand,” which I have been
`
`told is Exhibit 1007 to TSMC’s petition);
`
`• B.B.M. Brandt et al., “LOCMOS, a New Technology for
`
`Complementary MOS Circuits,” Philips Tech. Rev. vol. 34 no. 1, pp.
`
`
`
`7
`
`Page 14 of 204
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`

`

`19–23 (1974) (“Brandt,” which I have been told is Exhibit 1008 to
`
`TSMC’s petition);
`
`• U.S. Patent No. 5,702,976 to Schuegraf et al. (“Schuegraf,” which I
`
`have been told is Exhibit 1009 to TSMC’s petition);
`
`• U.S. Patent No. 4,506,434 to Ogawa et al. (“Ogawa,” which I have
`
`been told is Exhibit 1010 to TSMC’s petition);
`
`• U.S. Patent No. 4,957,590 to Douglas (“Douglas,” which I have been
`
`told is Exhibit 1011 to TSMC’s petition);
`
`• U.S. Patent No. 5,976,939 to Thompson et al. (“Thompson,” which I
`
`have been told is Exhibit 1012 to TSMC’s petition);
`
`• U.S. Patent No. 6,165,826 to Chau et al. (“Chau,” which I have been
`
`told is Exhibit 1013 to TSMC’s petition);
`
`• U.S. Patent No. 5,733,812 to Ueda et al. (“Ueda,” which I have been
`
`told is Exhibit 1014 to TSMC’s petition);
`
`• U.S. Patent No. 5,539,229 to Noble, Jr. et al. (“Noble,” which I have
`
`been told is Exhibit 1015 to TSMC’s petition);
`
`• U.S. Patent No. 5,521,422 to Mandelman et al. (“Mandelman” which I
`
`have been told is Exhibit 1016 to TSMC’s petition);
`
`• U.S. Patent No. 5,021,353 to Lowrey et al. (“Lowrey,” which I have
`
`been told is Exhibit 1017 to TSMC’s petition);
`
`
`
`8
`
`Page 15 of 204
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`

`

`• U.S. Patent No. 4,638,347 to Iyer (“Iyer,” which I have been told is
`
`Exhibit 1018 to TSMC’s petition);
`
`• Japanese Patent Application No. 7-192181 to Segawa et al. (which I
`
`have been told is Exhibit 1019 to TSMC’s petition);
`
`• Certified Translation of Japanese Patent Application No. 7-192181 to
`
`Segawa et al. (which I have been told is Exhibit 1020 to TSMC’s
`
`petition);
`
`• File History of U.S. Patent No. 7,126,174 to Segawa et al. (which I
`
`have been told is Exhibit 1021 to TSMC’s petition); and
`
`• File History of Japanese Patent Application No. 7-330112 to Segawa et
`
`al. (which I have been told is Exhibit 1022 to TSMC’s petition).
`
`• Certified Translation of the File History of Japanese Patent Application
`
`No. 7-330112 to Segawa et al. (which I have been told is Exhibit 1023
`
`to TSMC’s petition).
`
`V. Legal Standards
`
`24.
`
`I am not an attorney and have not been asked to offer my opinion on
`
`the law. However, as an expert offering an opinion on whether the claims in the
`
`’174 patent are patentable, I have been told that I am obliged to follow existing
`
`law. I have been told the following legal principles apply to analysis of
`
`patentability pursuant to 35 U.S.C. §§ 102 and 103.
`9
`
`
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`Page 16 of 204
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`

`

`25.
`
`I also understand that, in an inter partes review proceeding, patent
`
`claims may be deemed unpatentable if it is shown by preponderance of the
`
`evidence that they were anticipated and/or rendered obvious by one or more prior
`
`art patents or publications.
`
`26. Further, I have been told that, in an inter partes review proceeding,
`
`patent claims cannot claim the benefit of priority to a domestic or a foreign
`
`application, if the domestic or the foreign application does not adequately describe
`
`or enable those claims.
`
`A. Anticipation
`I have been told that for a claim to be anticipated under § 102, every
`27.
`
`limitation of the claimed invention must be found in a single prior art reference.
`
`28.
`
`I have been told that a claim is unpatentable as anticipated
`
`under § 102(a) if the claimed invention was “known or used by others in this
`
`country, or patented or described in a printed publication in this or another country,
`
`before the invention thereof by the applicant for patent.”
`
`29.
`
`I have been told that a claim is unpatentable as anticipated under
`
`§ 102(b) if the claimed invention was “patented or described in a printed
`
`publication in this or a foreign country or in public use or on sale in this country,
`
`more than one year prior to the date of the application for patent in the United
`
`States.”
`
`
`
`10
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`Page 17 of 204
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`

`

`30.
`
`I have been told that a claim is unpatentable as anticipated under
`
`§ 102(e) if “the invention was described in (1) an application for patent, published
`
`under section 122(b), by another filed in the United States before the invention by
`
`the applicant for patent or (2) a patent granted on an application for patent by
`
`another filed in the United States before the invention by the applicant for patent,
`
`except that an international application filed under the treaty defined in section
`
`351(a) shall have the effects for the purposes of this subsection of an application
`
`filed in the United States only if the international application designated the United
`
`States and was published under Article 21(2) of such treaty in the English
`
`language.”
`
`B. Obviousness
`I have been told that under 35 U.S.C. § 103(a), “[a] patent may not be
`31.
`
`obtained although the invention is not identically disclosed or described as set forth
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`in section 102, if the differences between the subject matter sought to be patented
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`and the prior art are such that the subject matter would have been obvious at the
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`time the invention was made to a person having ordinary skill in the art to which
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`said subject matter pertains.”
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`32. When considering the issues of obviousness, I have been told that I
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`am to do the following:
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`a.
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`Determine the scope and content of the prior art;
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`b.
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`Ascertain the differences between the prior art and the claims at
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`issue;
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`c.
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`d.
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`Resolve the level of ordinary skill in the pertinent art; and
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`Consider evidence of secondary indicia of non-obviousness (if
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`available).
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`33.
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`I have been told that the relevant time for considering whether a claim
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`would have been obvious to a person of ordinary skill in the art is the time of
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`alleged invention, which I have assumed is shortly before the ’174 patent was filed.
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`34.
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`I have been told that obviousness is a determination of law based on
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`underlying determinations of fact. I have been told that these factual
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`determinations include the scope and content of the prior art, the level of ordinary
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`skill in the art, the differences between the claimed invention and the prior art, and
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`secondary considerations of non-obviousness.
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`35.
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`I have been told that any assertion of secondary indicia must be
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`accompanied by a nexus between the merits of the invention and the evidence
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`offered.
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`36.
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`I have been told that a reference may be combined with other
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`references to disclose each element of the invention under § 103. I have been told
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`that a reference may also be combined with the knowledge of a person of ordinary
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`skill in the art and that this knowledge may be used to combine multiple
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`references. I have also been told that a person of ordinary skill in the art is
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`presumed to know the relevant prior art. I have been told that the obviousness
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`analysis may take into account the inferences and creative steps that a person of
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`ordinary skill in the art would employ.
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`37.
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`In determining whether a prior art reference could have been
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`combined with another prior art reference or other information known to a person
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`having ordinary skill in the art, I have been told that the following principles may
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`be considered:
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`a. A combination of familiar elements according to known methods is
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`likely to be obvious if it yields predictable results;
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`b. The substitution of one known element for another is likely to be
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`obvious if it yields predictable results;
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`c. The use of a known technique to improve similar items or methods in
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`the same way is likely to be obvious if it yields predictable results;
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`d. The application of a known technique to a prior art reference that is
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`ready for improvement, to yield predictable results;
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`e. Any need or problem known in the field and addressed by the
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`reference can provide a reason for combining the elements in the
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`manner claimed;
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`f. A person of ordinary skill often will be able to fit the teachings of
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`multiple references together like a puzzle; and
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`g. The proper analysis of obviousness requires a determination of
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`whether a person of ordinary skill in the art would have a “reasonable
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`expectation of success”—not “absolute predictability” of success—in
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`achieving the claimed invention by combining prior art references.
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`38.
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`I have been told that whether a prior art reference renders a patent
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`claim unpatentable as obvious is determined from the perspective of a person of
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`ordinary skill in the art. I have been told that there is no requirement that the prior
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`art contain an express suggestion to combine known elements to achieve the
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`claimed invention, but a suggestion to combine known elements to achieve the
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`claimed invention may come from the prior art, as filtered through the knowledge
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`of one skilled in the art. In addition, I have been told that the inferences and
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`creative steps a person of ordinary skill in the art would employ are also relevant to
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`the determination of obviousness.
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`39.
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`I have been told that, when a work is available in one field, design
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`alternatives and other market forces can prompt variations of it, either in the same
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`field or in another. I have been told that if a person of ordinary skill in the art can
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`implement a predictable variation and would see the benefit of doing so, that
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`variation is likely to be obvious. I have been told that, in many fields, there may
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`be little discussion of obvious combinations, and in these fields market demand—
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`not scientific literature—may drive design trends. I have been told that, when
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`there is a design need or market pressure and there are a finite number of
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`predictable solutions, a person of ordinary skill in the art has good reason to pursue
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`those known options.
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`40.
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`I have been told that there is no rigid rule that a reference or
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`combination of references must contain a “teaching, suggestion, or motivation” to
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`combine references. But I also understand that the “teaching, suggestion, or
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`motivation” test can be a useful guide in establishing a rationale for combining
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`elements of the prior art. I have been told that this test poses the question as to
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`whether there is an express or implied teaching, suggestion, or motivation to
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`combine prior art elements in a way that realizes the claimed invention, and that it
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`seeks to counter impermissible hindsight analysis.
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`VI. Technological Background
`Integrated Circuits
`A.
`41. A transistor functions like a valve for controlling electric current
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`through it according to a control signal. In a digital circuit, the valve is either open
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`or closed, so the transistor acts more like a switch. One type of transistor is a
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`MOSFET, which stands for metal-oxide-semiconductor (MOS) field-effect
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`transistor (FET).
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`42. As the name suggests, the MOS structure is a layered stack, the
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`bottom of which is a semiconductor, the middle of which is a gate oxide, and the
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`top of which is a conductive gate. Often, when the gate insulator is not an oxide,
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`this will be abbreviated MIS, rather than MOS, but they are effectively the same
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`structures. In addition, the “metal” may be polysilicon or a metal silicide, rather
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`than a true metal.
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`43. A field-effect transistor (FET) is named after its principle of
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`operation. In particular, the MOS gate structure modulates an electric field near
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`the semiconductor-gate insulator interface. This electric field adjusts a “channel”
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`through which the current can traverse the transistor.
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`44. A MOSFET includes several basic elements: a source (an inlet for
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`current), a drain (an outlet for current), and a gate (for controlling current flow
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`through the channel beneath the gate from the source to the drain). Electrodes on
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`top of the source and drain allow current to flow into and out of the transistor.
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`45. The gate of a MOSFET comprises two basic parts: a gate insulator
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`(“gate oxide” or “gate dielectric”) and a gate electrode (“gate electrode” or “gate”).
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`The gate electrode allows the MOSFET to switch on and off. The ga