United States Patent [19J
`Clay
`
`I lllll llllllll Ill lllll lllll lllll lllll lllll 111111111111111111111111111111111
`US005465338A
`[11] Patent Number:
`[ 45] Date of Patent:
`
`5,465,338
`Nov. 7, 1995
`
`[54] DISK DRIVE SYSTEM INTERFACE
`ARCHITECTURE EMPLOYING STATE
`MACHINES
`
`Primary Examiner-Jack B. Harvey
`Assistant Examiner-John Travis
`Attorney, Agent, or Firm-Fliesler, Dubb, Meyer & Lovejoy
`
`[75]
`
`Inventor: Donald W. Clay, Louisville, Colo.
`
`[73] Assignee: Conner Peripherals, Inc., San Jose,
`Calif.
`
`[21] Appl. No.: 110,883
`
`[22] Filed:
`
`Aug. 24, 1993
`
`Int. Cl.6
`•••••••••••••.••••.•.••••••.•••••••••••••••••••.•••••• G06F 13/00
`[51]
`[52] U.S. CI ........................... 395/310; 395/439; 395/894;
`395/404
`[58] Field of Search ..................................... 395/325, 425,
`3951500, 275
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`[57]
`
`ABSTRACT
`
`In a disk drive storage system, an interface apparatus for
`controlling the transfer of sectors of data between a host
`processor and a buffer within the storage system in response
`to READ and WRITE command issued by the host proces(cid:173)
`sor. The apparatus comprises a Byte Count State Machine
`for controlling the transfer of a sector of data between the
`host processor and the buffer, an Update Task File State
`Machine for counting the sectors transferred by the Byte
`Count State Machine and generating the sector address of
`the next sector to be transferred by the Byte Count State
`Machine, a Read State Machine for controlling the process(cid:173)
`ing of all READ commands and a Write State Machine for
`controlling the processing of all WRITE commands.
`
`5,276,662
`
`111994 Shaver, Jr. et al ........................ 369/32
`
`7 Claims, 18 Drawing Sheets
`
`HOST
`t
`
`16
`
`DATA REGISTER 2
`
`8
`
`8
`
`MULTIPLEXER
`
`3
`
`.----s---- BUFFER
`8---1
`11
`
`8----'
`
`BUFFER
`CONTROLLE
`9.__ ___ __,
`13
`
`COMPRESSOR
`25
`
`24
`
`AT REGISTERS..--•
`.& COUNTERS
`25
`
`BYTE COUNT
`STATE MACHINE
`4
`
`UPDATE TASK
`FILE STATE
`MACHINE
`
`5
`
`READ
`STATE
`MACHINE
`6
`
`WRITE
`STATE
`MACHINE
`7
`
`1
`
`KINGSTON 1007
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 1 of 18
`
`5,465,338
`
`I
`
`BUFFER
`-
`11
`' - - - - - - - '
`
`-
`
`____ ..,..- STATE MACHINES 10w--..af
`; BUFFER 13
`'--------____.•-
`rt CONTROL & ~
`_ _ -------------.~ REGISTER
`DATA
`-
`MULTIPLEXOR 12 ..,-------.
`I
`FIFO
`16
`'
`'~
`
`FIFO
`14
`
`._
`~7 ECC
`DETECTOR
`15
`
`-
`
`READ
`SEQ 1--
`
`17
`
`•
`
`I
`
`- FLASH
`-~ CONTROLLER
`21
`
`' •
`
`za
`
`"
`• r
`
`'
`
`' • ' l
`v-74
`
`r76
`
`75-.._
`r
`'r. r
`
`FLASH
`MEMORY
`51
`27
`
`HOST
`' .
`·~ r9
`.•
`• ,.65~ 144 SEL a . - - - - - - - - .
`-
`18 11111- - - - - - ,
`INTERFACE
`-
`CONTROL
`
`- - - - -
`
`1'
`
`64
`
`~ - COMPRESSOF -t:,
`
`19
`
`20
`
`22
`~ CRC
`GENERATOR.__
`
`r.f RAM 31 ~
`CRC
`CHECKER
`2_3
`- J . __ DECOMPRESSOA,,.-~~
`24
`
`L......r--
`
`,.
`• •
`
`AT
`- REGISTER~
`25
`
`- - - - - 69--._,
`ECC
`,,
`GENERATOR.._--',~ .•
`26 ... ..:--1--1, •
`
`' .
`~Q
`ROM RAM ..__.i- MICRO
`28
`29
`~ PROCESSOR.._-_ ___,
`QQ
`,L__ __ ~-~~~--~~
`t
`~ "..:--~
`L . . . - - - - - - - - ' FIG. 1
`
`2
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 2of18
`
`5,465,338
`
`READ
`
`INPUT CHS (CYCLINDER, HEAD AND
`SECTOR) AND SECTOR COUNT
`
`TRANSLATE CHS TO LSN
`(LOGICAL SECTOR NUMBER)
`
`SEND STATUS
`INVALID CHS
`
`YES
`READ NEXT SECTOR HEADER AFTER
`LAST STORED READ HEADER
`
`A
`
`READ HEADER
`ATTRIBUTE WORD
`
`READ OFFSET WORD
`
`NO
`
`.READ SECTOR
`TRANSLATION
`TABLE FOR LSN
`PFA (PARTIAL .
`FLASH ADDRESS)
`
`SEND STATUE
`SECTOR BAD
`
`SEND STATUS
`LSN NOT FOUNl"'\l ... 1--<
`
`FIG . . 2A
`
`3
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 3of18
`
`5,465,338
`
`FA (FLASH ADDRESS)
`• PFA +APPENDED
`SCAN COUNT
`
`SCAN COUNT • 0
`
`WRITE A SECTOR
`OF ZEROS INTO
`BUFFER
`
`F
`
`WRITE A SECTOR
`OF COMPRESSED
`ZEROS INTO BUFFER
`
`ADD 1 TO
`SCAN COUN
`
`FIG. 28
`
`4
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 4of18
`
`5,465,338
`
`READ SECTOR FROM FLASH
`MEMORY INTO BUFFER AND
`TO ECC DETECTOR
`
`SLOW DOWN ACCES
`AND RETRY READ
`
`NO
`
`YES
`TRY ERROR CORRECTION
`
`NO
`
`F i------t
`
`ROUTE SECTOR DAT
`DIRECTLY TO HOST
`
`.ROUTE SECTOR DATA
`THROUGH DECOMPRESSO
`TO THE HOST
`
`NO
`FLAG ERROR TO HOS
`
`ROUTE SECTOR DATA
`TO CRC CHECKER
`
`END
`
`FIG. 2C
`
`5
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 5of18
`
`5,465,338
`
`WRITE
`
`INPUT CHS (CYCLINDER, HEAD AN
`SECTOR) AND SECTOR COUNT
`
`TRANSLATE CHS TO LSN
`(LOGICAL SECTOR NUMBER)
`
`ROUTE
`YES SECTOR
`THROUGH
`COMPRESSO
`TO BUFFER
`
`ROUTE SECTO
`THROUGH CRC
`GENERATOR
`CRC BYTE TO
`BUFFER
`
`SEND STATUS
`INVALID CHS
`
`ROUTE SECTOR
`DIRECTLY TO
`.______ __
`BUFFER
`
`YES
`
`ROUTE SECTOR YES
`BACK THROUGH.------(cid:173)
`DECOMPRESSOR
`TO BUFFER
`
`NO
`
`SET SECTOR
`ATTRIBUTE AS
`UNCOMPRESSED
`
`SET SECTOR
`ATTRIBUTE AS
`COMPRESSED
`
`FIG. 3A
`
`6
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 6of18
`
`5,465,338
`
`A
`
`READ NEXT SECTOR HEADER AFTE
`LAST SECTOR MARKED AS DIRTY
`
`YES
`
`MARK
`HEADER
`DIRTY
`
`.READ SECTOR
`NO TRANSLATION
`~ .. TABLE FOR LSN
`PFA (PARTIAL
`FLASH ADDRESS)
`
`NO
`
`FA (FLASH ADDRESS
`• PFA + APPENDED
`SCAN COUNT
`
`.____.,
`NO
`
`ADD 1 TO
`SCAN COUNT
`
`SEND STATUS
`STANDBY
`
`FIG. 38
`
`7
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 7of18
`
`5,465,338
`
`WRITE HEADER AT
`NEXT AVAILABLE
`ADDRESS IN BLOC
`
`UPDATE TRANSLATION TAB
`WITH NEW PFA FOR SECTO
`
`TOP
`
`POINT FLASH WRITE
`WINDOW TO THE
`BEGINNING OF THE
`DATA AREA AS
`INDICATED BY THE
`OFFESET IN HEADER
`
`CHANNEL SECTOR
`THROUGH ECC
`GENERATOR TO
`FORM ECC DATA
`
`WRITE SECTOR
`FROM BUFFER
`AND ECC DATA
`TO FLASH
`
`YES
`
`ALLOCATE INTO NEXT
`AVAILABLE BLOCK
`
`FIG. 3C
`
`8
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 8of18
`
`5,465,338
`
`IN ITIAUZA TION
`
`SET PFA FOR ALL SECTORS
`IN THE TRASLATION TABLE
`TO ADDRESS FFFF
`
`SET FREE, DIRTY, AND NUMBER
`OF SECTORS REGISTERS TO 0
`
`READ BAD BLOCK DATA FROM ROM
`
`UPDATE TOTAL FREE
`FLASH IN BLOCK,
`CHIP AND ARRAY
`
`GO TO NEXT BLOCK
`
`YES
`
`READ NEXT HEADE
`
`MAINTAIN MAXIMUM
`CYCLE COUNT
`
`FIG. 4A
`
`9
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 9of18
`
`5,465,338
`
`A
`
`STORE PFA I
`TRANSLATION
`TABLE FOR
`HEADER LSN
`
`.MARK OL
`HEADER
`DIRTY
`
`YES
`
`MARK
`HEADER
`DIRTY
`
`UPDATE TOTAL
`DIRTY IN
`BLOCK & ARRA
`
`UPDATE TOTAL
`DIRTY IN
`BLOCK & ARRAY
`
`c
`
`FIG. 48
`
`10
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 10 of 18
`
`5,465,338
`
`HOST
`t
`16
`~
`DATA REGISTER 2
`HIGH BYTE
`LOW BYTE
`f
`f
`8
`8
`
`•
`
`•
`
`MULTIPLEXER
`
`.
`-
`
`8
`8
`
`..-8
`
`COMPRESSOR
`25
`
`•
`
`BUFFER
`11 ~
`
`' l
`
`8
`
`BUFFER
`CONTROLLER
`13
`
`1
`
`,
`DECOMPRESSOF
`24
`
`' '" . '"
`
`-
`--
`- 8
`3 14-8
`
`UPDATE TASK
`FILE STATE
`MACHINE
`
`5
`4 •
`
`f ' •
`
`4.
`
`' l
`
`' .
`. BYTE COUNT
`AT REGISTERS -
`- STATE MACHINE
`4
`.& COUNTERS
`25 ~
`
`h4
`-
`
`j
`
`READ
`__,. STATE
`MACHINE
`6
`
`WRITE
`STATE
`MACHINE
`7
`
`FIG. 5
`
`11
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 11 of 18
`
`5,465,338
`
`- NAN ....
`.
`.
`NA
`!':I 101
`'. ·NAN~
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`: 102
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`'.
`-- 104"""
`
`100 ....
`
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`
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`:i105
`JNAN J--
`!".1106
`
`FIG. 6
`-
`AW
`• OFF
`
`-
`
`:
`:
`
`RW
`
`HOS
`T -
`NOT
`REA RX
`DYRW
`
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`SEC
`CNT
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`BU<
`CNT
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`
`RX
`
`AZ
`
`RY
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`
`RY
`
`NOT
`END
`y
`DELA
`
`AZ
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`131
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`RS
`-+
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`RB
`H
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`RC
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`RF
`
`NA~
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`-RX
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`~ OFF
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`128 ::
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`:J 109
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`129 ,_
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`:i 11s
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`:i111 r
`ffiTI:J
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`1118
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`126 -
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`y NA~ ::>-I
`---: ""
`~ --~ AZ
`130 -
`• 120
`'
`
`••
`
`,.
`,.
`, .
`,.
`
`,
`
`BYTE
`CNT
`NOT
`-o
`
`I
`
`NOT
`DATA
`,,,
`READ
`BU<
`CNT
`-o
`
`SEC -o T CNT
`
`:J 121
`·'NAN
`~122 i-.
`"""'
`
`-
`
`._RESET
`...._CLOCK
`
`12
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 12 of 18
`
`5,465,338
`
`I tJ r STATE o
`9READ MODE?
`lv
`
`STATE 1
`LO BYTE CNT
`LO BLK CNT
`UPDATE TASK
`FILE
`• .L ~
`
`I__
`l!!
`
`N
`-
`
`·.1rY
`STATE B
`DATA READY?
`GATE 1 ST WORD
`.. .Ir
`. J. y
`STATE A
`HOST READY?
`CLK COMPRESSOR
`
`lv
`
`STATE E
`RST LONG
`LO BYTE CNT
`GATE 1 ST WORD
`
`y
`
`STATE 2
`SET DRQ
`AST BSY
`SET IRQ
`.. l ~
`~ STATE 6
`·~ BYTE CNT• O?
`lY
`STATE 4
`STATE 8
`STATE C
`SECT CNT• O?
`N AST RD MODE
`LONG ?
`SET XFER DONE Y
`DEC BLK CNT i--___.; EN ECC XFER ..:..:...e RST ECC XFEF
`AST 1016
`INC XFER REL
`AST DRQ
`lN
`SET BUSY
`f STATE 5 l
`l
`STATE D
`STATE F
`N
`LOAD SECT DEIJ\ Y _. rl DEIJ\Y
`STATE 7
`AST DAQ
`• ~
`ENDED ?
`Y
`..._ BLK CNT • 0 ?
`UPDATE TASK FILE~ LO BLK CNT
`IN
`LO BYTE CNT
`SET BUSY
`CLK COMPRESSOR
`FIG . . 7
`
`!__
`
`13
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 13 of 18
`
`5,465,338
`
`- ~ . .
`--
`.
`-.
`.
`. .
`.
`..
`
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`
`L_
`,___
`
`1.
`
`,.
`
`...
`
`FIG. 8
`
`.....-
`
`OFF WA;
`.
`r;::i 228 -
`-
`•
`._____
`WA
`
`n 200 :;
`'.•NAN
`:201 ~
`NAN
`NA1'
`202
`224 :.
`--
`NAi-,
`203 . -
`.
`......_
`~NA~_
`.
`n204 -
`206 -
`
`NANh
`207
`L
`
`NAfl
`,_
`
`225 -E"~ 229 :
`·15FF WB:
`.
`..___
`we
`
`......_
`
`'
`
`WC
`
`WD
`
`WB
`WBWA
`WDWC
`SECT CNT
`NOT•O
`
`END DELA~.·
`...
`...
`
`SECT CN7
`-o
`
`WA
`
`OK TOXF"':
`
`SECT CN7
`-o
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`
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`
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`
`NANP-
`205
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`
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`232
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`~ 214
`
`1
`
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`212
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`t
`
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`226
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`n217
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`218 -
`
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`
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`
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`NOT•O
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`NOT•O
`LONG
`
`BLK CNT
`-o
`SECT CN-
`-o
`
`NA~
`"NAN ----
`P-
`219
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`... ~ :1221
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`222 ...,-
`-
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`
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`.-WD.
`227 '::.
`•
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`' ... • 231 :.
`.
`..___
`WO
`
`----
`
`-RESET
`CLOCK
`
`....
`
`14
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 14 of 18
`
`5,465,338
`
`L
`
`~
`
`I
`
`L
`
`•
`
`N
`
`-
`
`~ J.,
`STATE 0
`WRITE MODE?
`!Y
`STATE 2
`SET WRITE START
`~
`~ .L.
`STATE 3
`OK TO XFERll
`.I
`1Y
`STATE 7
`LO BYTE CNT
`LO BLK CNT
`SET DRQ
`RST BUSY
`SET IRQ
`L J. ~
`• J.,
`STATE 6
`BYTE CNT-0
`1v
`STATE 4
`SET XFR DONE
`UPDATE TASK FILE
`DEC BLK CNT
`INC XFR REL
`
`N
`STATE E
`
`1 J SECT CNT •O
`LO BYTE CNT
`y !
`I
`STATE F
`
`N
`
`STATE C
`BLCK CNT • O?
`RST 1ST WRITE
`y~
`
`, '.
`
`STATE D
`SECT CNT•O?
`SET BUSY
`RST DRQ
`y
`
`N
`
`STATE 9
`.. LD DELAY
`
`L
`
`y
`STATE B
`
`' ... END DELAY?
`
`L
`
`N
`
`STATE 5
`LONG?
`y RSTLONG
`RST 1016
`EN ECC XFR
`
`-
`
`STATE 1
`~ RST DRQ
`RST WRITE MODE
`RST ECC XFR
`
`FIG. 9
`
`15
`
`

`

`RF~
`~~LO BLKCNT
`
`RE~
`ws~RSTLONG
`
`R4*
`W4*
`
`~~RSTI016
`
`R7--f0Rl-+ CLK CMPRS
`RA~
`
`UPDATE
`TASK FILE
`
`o-----. INC XFER REL
`
`U.S. Patent
`
`Nov.7, 1995
`
`Sheet 15 of 18
`
`5,465,338
`
`R1~
`w1~RSTWM
`
`DEC BU< CNT
`
`~~~O
`
`700
`
`R7
`W7
`WE
`
`EN E~NW7*
`
`-ET_D_R_Q
`
`LO BYTE CNT W7 ~ NO
`R2-708
`W4*
`OR
`---110
`
`~~~ LONG,-(cid:173)
`
`712
`
`AST DRQ WD
`
`WO*
`W1
`
`SET BUSY
`
`~~~XFER DONE
`
`W2
`
`- - - -WR START
`
`GATE 1ST
`WORD
`
`1STOP
`
`~~~EN ECC XFER
`
`~~~AST ECC XFER
`
`R1
`
`«fe ~LO SECT DELAY CNT RS
`FIG. 10
`
`16
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 16 of 18
`
`5,465,338
`
`RESET-(cid:173)
`CLOCK----.
`
`DECR
`,...---.... SECT
`CNT
`
`A ~~r;;;;:;i
`B --+--
`.UPDATE
`TASK ____ ...,__..
`FILE
`......___.
`
`SECT CNT • 0 - - (cid:173)
`FIRST OP-----~~
`
`SECT
`AT
`MAX
`
`HEAD
`AT
`MAX
`RESET-
`
`OFF SECT MAX
`312
`
`SECT MAX
`OFF HEAD MAX
`313
`
`HEAD MAX
`
`FIG. 11
`
`17
`
`CLR HEAD
`INC CYL
`
`INC HEAD
`
`CLR SECT
`
`INC SECT
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 17 of 18
`
`5,465,338
`
`CLOCK---------+--(cid:173)
`BLK CNT • 1 ---. ..
`BYTE CNT •0-----11
`GATE
`1ST
`WORD
`
`HIOR-----1...t~;::;i
`
`WRITE
`--DATA
`
`DECR
`BYTE
`CNT
`D * t - - - - . ARD
`
`.r«>---1--... CU< HIGH BYTE
`-+tt...:.::...r----r---. CLK HIGH BYTE
`
`CLK
`
`RSTPr-----t~-----tt=~
`
`FIG. 12
`
`18
`
`

`

`U.S. Patent
`
`Nov. 7, 1995
`
`Sheet 18 of 18
`
`5,465,338
`
`~
`
`~
`
`"1,
`STATE 0
`UPDATE TASK FILE?
`!Y
`STATE 1
`DECR SECT CNT
`SECT CNT•O?
`
`.!!.
`....
`
`y
`
`-
`
`STATE 2
`LATCH HD AND
`SECT COMPARE
`·~
`
`N
`
`. STATE 3
`• INC TASK FILE
`
`FIG. 13
`
`_N_ STATE 0
`I OW /I OR?
`y
`
`STATE 1
`DECR BYTE CNT
`CLK LOW BYTE
`
`STATE 3
`
`STATE 2
`GATE HIGH BYT
`
`STATE 4
`
`STATE 5
`DECR BYTE CNT
`CLK HIGH BYTE
`
`STATE 7
`
`STATE 6
`
`FIG. 14
`
`19
`
`

`

`5,465,338
`
`1
`DISK DRIVE SYSTEM INTERFACE
`ARCHITECTURE EMPLOYING STATE
`MACHINES
`
`BACKGROUND OF THE INVENTION
`
`15
`
`2
`To have a solid state drive emulate a magnetic disk drive,
`the solid state storage media must be transparent to the host.
`Ideally, the solid state drive would accept the same com(cid:173)
`mands and data formats as the magnetic disk drive such that
`no change in programming or system configuration need be
`done within the host. A disadvantage associated with most
`solid state memories is the time necessary to write into the
`memory. The slow write speed is a major reason why the
`solid state drives emulating magnetic disk drives have not
`10 been more widely accepted and marketed within the indus(cid:173)
`try.
`At present, both in magnetic disk drives and in flash disk
`drives, a microcontroller is employed for controlling the
`operation of the storage system. One of the functions of the
`microcontroller is to control the transfer of data across the
`host interface between the host processor and the storage
`media within the drive system. This requires that the micro(cid:173)
`processor dedicate resources to transfer data between the
`host computer and the storage system across the interface in
`response to READ and WRITE commands. This require(cid:173)
`ment limits the microprocessor's availability to perform
`other functions and, therefore, results in a limitation on the
`overall system performance of the storage system. In mag(cid:173)
`netic disk drive storage systems, some attempts have been
`made to unburden the microprocessor by transferring some
`of the functions of the microprocessor to state machines or
`to have a two microprocessors involved in performing the
`functions thereby reducing the workload on each micropro(cid:173)
`cessor and allowing two functions to be in process at the
`same time. In particular, the flash solid state drive system
`requires the microprocessor to be involved in housekeeping
`operations with regard to . the flash memory, as well as
`controlling the reading and writing of data from the memory
`buffer to the flash memory itself. This increased responsi(cid:173)
`bility on the microprocessor further reduces the system
`performance due to the time necessary to perform the
`increased functions allocated to the microprocessor.
`
`20
`
`1. Field of the Invention
`The present invention relates generally to digital data
`storage systems and more particularly to an AT interface
`architecture employing state machines for use in a digital
`data storage system. More particular still, the invention
`relates to a flash solid state memory system that employs the
`AT interface architecture comprising state machines.
`2. Description of the Related Art
`Magnetic disk drives have been widely accepted in the
`computer industry and are used for storing large amounts of
`data. Over the years, magnetic disk drives have decreased in
`size while increasing in operational speed and in the amount
`of data that can be stored on the magnetic media. Magnetic
`disk drives have associated with them a seek latency time
`which is associated with the time necessary to move the
`desired transducer to the desired track or cylinder on the
`magnetic media for the purpose of recovering or writing data
`to and from the magnetic media. In addition, there is a 25
`rotational latency associated with waiting for the desired
`data sector to pass underneath the transducer once the
`transducer is located on the desired track. Magnetic disk
`drives also have the associated problems of relying on
`mechanical hardware for locating the transducer at a specific 30
`location with regards to the magnetic media and for main(cid:173)
`taining the rotational speed of the magnetic media at some
`constant value. The mechanical hardware is affected by the
`normal wear and tear associated with mechanical devices.
`Further, magnetic disk drives have employed various track 35
`following servo systems for maintaining the transducer on a
`desired track once the transducer reaches that desired track.
`Finally, the magnetic disk drive tracks are divided into a
`fixed number of sectors where each sector stores a fixed
`number of data bytes. As a rule, magnetic disk drive systems 40
`will write a complete sector each time a sector is written.
`Where the data is less than a full sector the data is padded
`with zeros to fill up the sector. This is to say that if the sector
`length is 512 bytes, whenever a sector is written 512 bytes
`of data will be written into that sector. The requirements of 45
`writing a full sector every time a sector is written means that
`a substantial portion of the magnetic surface may be allo(cid:173)
`cated to contain filler data rather than useful data. Finally, it
`can readily be realized that the data would also be recovered
`from the magnetic disk drive in sector lengths and, therefore,
`a full sector must be read from the disk regardless of the
`actual amount of useful data that was recorded in that sector.
`With the advent of solid state memories, attempts have
`been made to elTilllate the magnetic disk drives by use of
`solid state memories in place of the magnetic media. 55
`Examples of such emulations are found in U.S. Pat. No.
`4,642,759 entitled "Bubble Memory Disk Emulation Sys(cid:173)
`tem" and U.S. Pat. No. 5,131,089 entitled "Solid State Disk
`Drive Emulation".
`The ideal system would use a solid state memory that is 60
`nonvolatile such as the above-referenced bubble memory or
`the solid state memory with its own power supply to
`maintain the stored data even though power is turned off to
`the drive. However, each of these solid state memories each
`have their own advantages and disadvantages which must be 65
`weighed in selecting which solid state memory should and
`could be used in a specific design.
`
`SUMMARY OF THE INVENTION
`
`Accordingly, it is an object of the invention to provide an
`AT interface architecture comprised of state machines such
`that the microprocessor is not involved in the transfer of data
`between the host and the buffer within the storage system.
`Another object of the invention is to provide a Read State
`Machine, a Write State Machine, a Byte Count State
`Machine and an Update Task File State Machine which
`perform and control the transfer of data between the system
`and the host across the host interface.
`Another object of the invention is the coaction between
`the Read State Machine, the Byte Count State Machine and
`the Update Task File State Machine for controlling the
`transfer of data during a READ operation, that is the transfer
`of data from the buffer within the storage system to the host.
`Still another object of the invention is the coaction
`between the Write State Machine, the Byte Count State
`Machine and the Update Task File State Machine during a
`WRITE operation, that is the transfer of data from the host
`to the buffer within the storage system.
`Briefly, there are four state machines in the AT interface
`architecture that are used to control the overall operation of
`data transfer to and from the host. A Write State Machine
`controls the overall operation of write commands, ie write
`sectors, write sector long, write multiple, write buffer, or
`write DMA. A Read State Machine controls the operation of
`the read commands, ie read sectors, read sector long, read
`
`50
`
`20
`
`

`

`3
`multiple, read buffer, or read DMA. An Update Task File
`State Machine tracks the number of sectors processed and
`then generates; a signal to increment the sector address. A
`Byte Count State Machine controls the conversion of words
`to bytes and the transfer of data between the host and the 5
`storage system.
`The operation of the four state machines are intertwined.
`The Read and Write State Machines control the overall
`operation of the data transfer and are mutually exclusive. At
`the point of the transfer for either a READ or WRITE IO
`operation where the task file needs to be updated, the Read
`or Write State Machine will initiate a cycle of the Update
`Task File State Machine. When either the Read or Write
`State Machines are started, the Byte Count State Machine is
`activated. The Byte Count State Machine generates pulses to 15
`decrement the byte counter every time that a byte of data is
`transferred to or from the data register to control the transfer
`of data during a READ or WRITE operation. The Read and
`Write State Machines hold in their cycle awaiting for the
`byte count to go to zero as controlled by the Byte Count 20
`State Machine. The Read State Machine issues a gate first
`word signal to tell the byte count machine to stage the first
`two bytes into the data register so that the first two bytes will
`be ready when the host starts reading data.
`The state machines interact with the AT registers. The task 25
`file count register is used to keep the number of sectors
`transferred. The head and sector configuration registers are
`used to tell when the task file and sector registers should be
`wrapped. The byte count register, which is fed from the ECC
`size register and the transfer size register, is used to count the
`number of bytes in the sector or the number of ECC bytes
`to be transferred. The block count register is loaded with a
`one for all but the read multiple command and for a read
`multiple command with the number of sectors to be trans(cid:173)
`ferred in each block. The byte count register generates 35
`signals when the byte count register contains either a zero or
`a one.
`An advantage of the AT interface employing state
`machines is that the microprocessor within the storage
`system is relieved of the task of controlling the transfer of
`data to and from the host processor from the memory buffer
`within the storage system, thereby increasing system per(cid:173)
`formance.
`
`30
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`50
`
`The invention will be described with respect to the
`particular embodiments thereof and references will be made
`to the drawings, in which:
`FIG. 1 is a logic diagram of the flash solid state drive;
`FIGS. 2A through 2C is a flow chart setting forth the
`operation of the flash solid state drive for a read operation;
`FIGS. 3A through 3C is a flow chart setting forth the
`operation of the flash solid state drive for a write operation; 55
`FIGS. 4A and 4B is a flow chart setting forth the operation
`of the flash solid state drive to initialize the sector translation
`table during the power up sequence;
`FIG. 5 is an overall logic diagram of the major compo(cid:173)
`nents of the ATA interface including the four state machines. 60
`FIG. 6 is a logic diagram of the Read State Machine;
`FIG. 7 is a flow chart of the operation of the Read State
`Machine;
`FIG. 8 is a logic diagram of the Write State Machine;
`FIG. 9 is a flow chart of the operation of the Write State
`Machine;
`
`21
`
`5,465,338
`
`4
`FIG. 10 is the control logic controlled by both the Read
`and Write State Machines for providing control signals to
`the storage system during a read and write operation and to
`the host processor during a read and write operation;
`FIG. 11 is a logic diagram of the Update Task File State
`Machine;
`FIG. 12 is a logic diagram of the Byte Count Stale
`Machine;
`FIG. 13 is a flow chart of the operation of the Update Task
`File State Machine; and
`FIG. 14 is a flow chart of the operation of the Byte Count
`State Machine.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`SYSTEM ARCHITECTURE
`
`FIG. 1 is a logic diagram showing the components of the
`flash solid state drive. The flash solid state drive is 100%
`hardware and software compatible with ATA/IDE lnterface
`standards and will support all mandatory AT-Attachment
`standard commands.
`Flash memory 27 is comprised of thirty Intel 28F008 flash
`chips 51 where the chip data size is 8 Mb and 8 bits of data
`are simultaneously written into or read from the flash chip.
`Two flash chips are paired together and addressed at the
`same time such that 16 bits may be written or read simul(cid:173)
`taneously into or from the flash memory. To accomplish this
`flash controller 21 is dual ported so as to provide both
`address and data to each flash chip of a chip pair by means
`of lines 73 through 76. The flash solid state drive is con(cid:173)
`trolled by microprocessor 30 in conjunction with an oper-
`ating program stored in ROM 28. Microprocessor 30 is also
`connected to RAM 29 to allow the dynamic storing of data
`necessary for controlling the operation of the drive. Micro(cid:173)
`processor 30 is connected to AT registers 25, to interface
`control circuitry 19, to flash control 21, to data multiplexer
`40 12, to ECC generator 26, to buffer control and registers 13
`and to ECC detector 15.
`For a write operation, data for a sector is received from the
`host on bus 9 to interface control 19. If the sector data is to
`be compressed, the sector data is transferred via line 64 to
`45 compressor 20 for data compression and through CRC
`generator 22 for generating CRC data. Data compressor 20
`is a LEMPAUZIV type data compressor. The compressed
`sector data, after being compressed, is stored in buffer 11.
`After the compressed sector data has been stored in buffer 11
`the CRC data byte is stored in buffer 11 and made part of the
`data associated with the sector being stored.
`If the sector data was not to be compressed, then the sector
`data would leave interface control 19 on line 65 and pass
`directly through selector 18 , FIFO 14 and data multiplexer
`12 into buffer 11. State machines 10 contains a Write State
`Machine which controls the sequence of operations during a
`write operation. Once the data for the sector, either com(cid:173)
`pressed or uncompressed, has been stored in buffer 11, the
`Write State Machine will then transfer the sector data from
`data multiplexer 12 to microprocessor 30. Microprocessor
`30 acts as a dual port microprocessor where the ports are
`connected to data multiplexer 12 by means of buses 57 and
`69. When sector data is transferred from buffer 11 to
`microprocessor 30 the sector data is also passed through
`65 ECC generator 26 to generate the ECC data. The ECC data
`is also provided to microprocessor 30. Microprocessor 30
`transfers the sector data and ECC data as data words, where
`
`

`

`5,465,338
`
`5
`each data word consists of two bytes of data,to flash con(cid:173)
`troller 21. Microprocessor 30 performs the task of taking
`two sequential bytes of sector data from buffer 11 or ECC
`data and forming data words for flash controller 21. Flash
`controller 21 then writes the data word into the flash memory
`27.
`During a read operation, the read command is received
`from the host on bus 9 by interface control 19. State machine
`10 includes a Read State Machine which controls the
`sequence of operation during the read procedure. The data is 10
`read from flash memory 27 by flash controller 21 in data
`word format. Read sequencer 17 receives the data word and
`provides sequentially each of the two bytes of data making
`up the received data word to speed matching buffer FIFO 16.
`Read sequencer 17 also routes the data bytes to ECC 15
`detector 15 for the detection of an error in the read data. The
`output of FIFO 16 is routed through multiplexer 12 to buffer
`11. When the data for a sector has been stored in buffer 11
`and no data error was detected by ECC detector 15, the
`sector data is then directed from buffer 11 through data 20
`multiplexer 12 and speed matching buffer FIFO 14 to
`selector 18. If the sector data was compressed, then the
`sector data is routed from selector 18 through decompressor
`24. The decompressed sector data from decompressor 24 is
`routed to CRC checker 23 and to interface control 19 for 25
`transmission to the host. If CRC checker 23 detects a CRC
`error, a flag is raised to the host indicating that an error exists
`in the sector data that was transmitted for that sector. If the
`read sector data was not compressed, selector 18 will route
`the sector data via line 65 to interface control 19 which will
`then route the data to the host via bus 9.
`State machines 10 also contains a between sector state
`machine for updating the task file registers and a Byte Count
`State Machine for maintaining of the number of bytes of data
`transfer during a read or write operation.
`AT registers 25 and buffer control registers 13 are used to
`control the sequence of operation in conjunction with the
`microprocessor performing the operation program as stored
`in ROM 28 and the operation of the various state machines. 40
`Buffer control and registers 13 include a tie breaking state
`machine to resolve conflicts in the data multiplexer 12 for
`access to buffer 11 and a buffer signal state machine for
`controlling the reading and writing of data into and out of
`buffer 11.
`The function of and description of the AT registers 25 and
`buffer registers 13 are as follows:
`
`35
`
`45
`
`AT REGISTERS
`
`6
`The register is used by the Host to indicate how many
`sectors are to be transferred on a read or write command.
`4. TASK FILE SECTOR REGISTER
`This register contains the logical sector requested by the
`5 host.
`5. TASK FILE SDH REGISTER
`bit 4 - Drive address
`bit 3 - Head bit 8
`bit 2 - Head bit 4
`bit 1 - Head bit 2
`bit 0 - Head bit 1
`6. TASK FILE CYLINDER LOW REGISTER
`This register and the following register contain the cyl(cid:173)
`inder requested by the Host.
`7. TASK FILE CYLINDER HIGH REGISTER
`8. COMMAND REGISTER
`This register is used by the Host to communicate the
`desired command. When either the Host or the drive write
`this register, the drive will become busy. When the drive is
`busy, only the drive may write the task file. When the drive
`is not busy, only the Host may write the Task File unless the
`drive writes OD bit 3 to enable the microprocessor access to
`the Task File registers.
`9. SECTOR CONFIGURATION REGISTER
`This is a 8 bit register used to determine the sector wrap
`point for the Host values.
`10 HEAD CONFIGURATION REGISTERS
`This is a 4 bit register used to determine the head wrap
`30 point for the Host values.
`bit 3 - Head bit 8
`bit 2 - Head bit 4
`bit 1 - Head bit 2
`bit 0 - Head bit 1
`11. DIGITAL ADDRESS REGISTER
`This register is the same as that read at 3F7 by the Host
`with the exception that bit 7 is a one instead of tristate as it
`is to the interface.
`bit 7 - Always 1
`bit 6 - Always 1
`bit 5 - Head bit 3-
`bit 4 - Head bit 2-
`bit 3 - Head bit 1-
`bit 2 - Head bit O(cid:173)
`bit 1 - Drive 1-
`bit 0 - Drive 0-
`12. AT CONTROL REGISTER
`This register contains status bits for use by the microcode.
`It is read only.
`bit 7 - Sector>maximum logical sector
`This bit contains the result of a comparison of the Task
`File Sector Number register and the Sector configura(cid:173)
`tion register.
`bit 6 - Head>maximum logical head
`This bit contains the result of a comparison of the Task
`File SDH register head value and the Head configura(cid:173)
`tion register.
`bit 5 - Count equal to 0
`This bit is 1 when the Task File Count Register is equal
`to 0.
`bit 4 - ECC Error
`This bit is 1 when an ECC error is detected. The ECC
`should be reset by toggling AT Res 1 in the Micropro(cid:173)
`cessor's reset register before continuing.
`
`50
`
`1. TASK FILE ERROR REGISTER
`This register is the error indicating register to the Host. It
`has bit significance except at power on or during the
`diagnostic command. It is a read only register to the Host.
`bit 7 - Bad Block
`bit 6 - ECC Data Check
`bit 4 - ID Not Found
`bit 2 - Aborted Command
`bit 1 - Track 0 Not Found
`bit 0 - Address Mark Not Found
`2. TASK FILE PRECOMP REGISTER
`This register is a write only register to the Host. It was
`previously used to indicate at what cylinder to begin pre(cid:173)
`compensation. It is used for other commands at this point in 65
`time.
`3. TASK FILE COUNT REGISTER
`
`55
`
`60
`
`22
`
`

`

`5,465,338
`
`8
`7
`This register is setup to allow bit operations to be done.
`bit 3 - Byte count equal to 0
`When it is read, it always returns FFh. To pulse any of these
`This bit is one when the transfer count register that counts
`bits, a zero is written.
`the number of bytes to be transferred on the interface
`bit 7 - Set Host IRQ.
`is=O.
`bit 2 - IOR & IOW equal to 0
`This bit sets the Host interrupt which is gated by the Host
`interrupt enable.
`This bit is for use in PCMCIA inter