Proceedings of the
`
`'on
`I ern
`T hno gy
`
`Int rconnect
`onference
`
`/"
`
` June I -3, I998
`
`Hyatt Regency Airport Hotel,
`San Francisco, California
`
`The HTC is sponsored by the IEEE Electron
`
`Deuicw Society.
`
`Its goal is to
`
`a forum
`
`for professionals in semiconductor processing,
`
`academia and equipment development to present
`
`and discuss exciting new science and technology.
`
`.
`Sponsored by the
`IEEE Electron Devices Society
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`0
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`Proceedings of the
`IEEE 1998
`"INTERNATIONAL
`fNTERCONNECT TECHNOLOGY
`
`\k\":-
`
`_
`
`CON FER ENCE
`
`‘
`
` “If!
`b”
`
`Hyatt Regency Hotel
`San Francisco, CA
`
`June 1 - 3, 1998
`
`Its goal is to provide a forum for professionals
`The IITC is sponsored by the IEEE Electron Devices Society.
`in semiconductor processing, academia and equipment development to present and discuss exciting new
`science and technology.
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`1998 International Interconnect Technology Conference
`Digest of Technical Papers
`
`Papers have been printed without editing as received from the authors.
`
`Copyright and Reprint Permissions: Abstracting is permitted with credit to the source. Libraries are
`permitted to photocopy beyond the limit of U.S. Copyright law for private use of patrons those articles in
`this volume that carry a code at the bottom of the first page, provided the per-copy fee indicated in the
`code is paid through the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923. For
`other copying, reprint or republication permission, write to IEEE Copyrights Manager,
`IEEE Service
`Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-1331. All rights reserved.
`Copyright © 1998 by the Institute of Electrical and Electronics Engineers, Inc.
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`PRINTED IN THE UNITED STATES OF AMERICA
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`Additional copies may be ordered from:
`IEEE Order Dept.
`445 Hoes Lane
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`IEEE Catalog Number: 98EX102
`ISBN: 0-7803-4285-2 (Softbound)
`ISBN: 0-78034286-0 (Microfiche)
`Library of Congress: 97-80205
`
`0/7 - 3 02 6 at
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`INORGANIC LOW K DIELECTRIC INTEGRATION
`SESSION 4:
`Co-chairs: Michael Thomas and Nobuo Hayasaka
`
`A Manufacturable Embedded Fluorinated SiO, for Advanced 0.25 pm
`4:00
`CMOS VLSI Multilevel Interconnect Applications
`C.S. Pai, A.N. Ve|aga", W.S. Lindenberger, W.Y.-C. Lai, K.P. Cheung, F.H.
`Baumann, C.P. Chang, C.T. Liu, R. Liu, P.W. Diodato, J.|. Colonell, H. Vaidya,
`S.C. Vitkavage*, J.T. Clemens and F. Tsubokura“, Lucent Technologies, Murray
`Hill, NJ, *Orlando, FL and **NEC Corporation, Kanagawa, Japan
`
`Highly Reliable Low-s (3.3) Si0F HDP-CVD for Subquarter-Micron CMOS
`Applications
`T. Fukuda, T. Hosokawa, E. Sasaki, and N. Kobayashi, Hitachi. Ltd., Tokyo,
`Japan
`
`Integration of Unlanded Via in a Non-Etchback SOG Direct-on-Metal
`Approach in 0.25 Micron CMOS Process
`T. Gao*, B. Coenegrachts*, J. Waeter|oos*, G. Beyer’, H. Meynen*, M. Van Hove‘
`and K. Maex*>**, IMEC, Leuven, Belgium and **lNSYS, K.U., Leuven, Belgium
`
`Suppressing Oxidization of Hydrogen Silsesquioxane Films by Using H20
`Plasma in Ashing Process
`E. Tamaoka, T. Ueda, N. Aoi and S. Mayumi, Matsushita Electronics Corp., Kyoto,
`Japan
`
`Tuesday, June 2
`
`IMPACT ON CIRCUIT PERFORMANCE
`SESSION 5:
`Co-chairs: Krishna Saraswat and Genda Hu
`
`Invited - Impact of Interconnect on Circuit Design Performance
`J-P. Schoellkopf, SGS-Thomson, Crolles, France
`
`8:55 Minimum Repeater Count, Size, and Energy Dissipation for
`Gigascale Integration (GSI) Interconnects
`J.C. Eble, V.K. De*, D.S. Wills and J.D. Meindl, Georgia Institute of Technology,
`Atlanta, GA and *|ntel Corp., Hillsboro, OR
`
`Low-k Dielectrics Influence on Crosstalk: Electromagnetic Analysis and
`Characterization
`
`C. Cregut, G. Le Carva|* and J. Chilo, PFT-CEM, St Martin d'Heres. France and
`*LET|/CEA, Grenoble, France
`
`Advanced Wiring RC Delay Issues for sub-0.25-micron Generation CMOS
`A.K. Stamper, M.B. Fuselier and X. Tian, IBM Microelectronics, Essex Junction VT
`
`4:00
`4.1
`
`4:25
`4.2
`
`4:50
`4 3
`
`5:15
`4.4
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`8:30
`5.1
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`8:55
`5.2
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`9:20
`5.3
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`9:45
`5.4
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`39
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`42
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`45
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`48
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`53
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`56
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`59
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`62
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`4:10
`12.4
`
`4:35
`12.5
`
`5:00
`12.6
`
`5:25
`12.7
`
`P1.1
`
`P1.2
`
`P1.3
`
`P1.4
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`P1.5
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`P1.6
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`P1.7
`
`P1.8
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`P1.9
`
`P1.10
`
`Impact of Low Pressure Long Throw Sputtering Method on Submicron Copper
`Metallization
`
`T. Saito, N. Ohashi, J. Yasuda, J. Noguchi. T. Imai, K. Sasajima, K. Hiruma, H.
`Yamaguchi and N. Owada, Hitachi Ltd., Tokyo. Japan
`
`CVD Cu Process Integration for Sub-0.25 pm Technologies
`J. Zhang, D. Denning, G. Braeckelmann, R. Venkatraman, R. Fiordalice and E.
`Weitzman, Motorola lnc., Austin, TX
`
`Self-Annealing of Electrochemically Deposited Copper Films in Advanced
`Interconnect Applications
`T. Ritzdorf, L. Graham, S. Jin*, C. Mu’ and D. Fraser’, Semitool, lnc., Kalispell, MT and
`*lntel Corp., Santa Clara, CA
`
`A Novel Cu-Plug Formation Using High Pressure Reflow Process
`K. Maekawa, T. Yamamura*, T.Fukada, A. Ohsaki and H. Miyoshi, Mitsubishi Electric
`Corp., Hyogo, Japan and *Ryoden Semiconductor System Engineering Corp., Japan
`
`POSTER SESSION I
`
`Effects of PECVD Deposition Fluxes on the Spatial Variation of Thin Film Density
`of As-Deposited SlO2 Films in Interconnect Structures, K. Lee, M. Deal, J. Mcvittie,
`J. Plummer and K. Saraswat, Stanford University, Stanford, CA
`
`Modeling of Metal-over-Silicon Microstrip interconnections: The Effect of SiO2
`Thickness on Slow-Wave Losses, L. Wang, Y.L. Le Coz, R.B. Iverson and J.F.
`McDonald, Rensselaer Polytechnic Institute, Troy, NY
`
`Application of Charge Based Capacitance Measurement (CBCM) Technique in
`Interconnect Process Development, S. Bothra, G.A. Rezvani, H. Sur, M. Farr, and
`J.N. Shenoy, VLSI Technology, lnc., San Jose, CA
`
`Stochastic Interconnect Network Fan-Out Distribution Using Rent's Rule, P.
`Zarkesh-Ha, J.A. Davis, W. Loh* and J.D. Meindl, Georgia Institute of Technology,
`Atlanta, GA and *LSI Logic Corp., Milpitas, CA
`
`Robustness of Self-Aligned Titanium Silicide Process: Improvement in Yield of
`Silicided Devices with APM Cleaning Step, C.W. Lim*-**, K.H. Lee**, K.L. Pey**, H.
`Gong‘, A.J. Bourdi||on*, S.K. Lahiri*, *National University of Singapore and "Chartered
`Semiconductor Manufacturing Ltd., Singapore
`
`The Effects of Stress on the Formation of Titanium Silicide, S.L. Cheng, H.Y.
`Huang, Y.C. Peng L.J. Chen, B.Y. Tsui*, C.J. Tsai", S.S. Guo** and K.H. Yu**, National
`Tsing Hua University, ‘ERSO/ITRI, and "National Chung Hsing University, Taiwan,
`ROC
`
`Correlation of Film Thickness and Deposition Temperature with PAI and the
`Scalability of Ti-SALICIDE Technology to Sub-0.18pm Regime, C. S.Ho, R.P.G.
`Karunasiri, S.J. Chua, K.L. Pey*, S.Y. Sch‘, K. H. Lee‘, and L. H. Chan*, National
`University of Singapore and ‘Chartered Semiconductor Manufacturing Ltd., Singapore
`
`Interconnect Material and CMP Process Change Effects on Local Interconnect
`Planarity, J. Mendonca, C. Dang, C. Pettinato, J. Cope, H. Garcia, J. Saravia, J.
`Farkas, D. Watts, and J. Klein, Motorola, lnc., Austin, TX
`
`One Step Effective Planarization of Shallow Trench Isolation, H-W. Chiou and L-J.
`Chen, ERSO/ITRI, Taiwan, ROC
`
`Nitrogen Effect on Post-Nucleation Tungsten CVD Film Growth, R. Petri, H. Hauf*,
`D. Berenbaum*, J.C. Favreau*, P. Mazet, ATMEL and ‘Applied Materials, Rousset,
`France
`
`160
`
`163
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`166
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`169
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`175
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`178
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`181
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`
`P1.11
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`P1.12
`
`P1.13
`
`P1.14
`
`P1.15
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`P1.16
`
`P1.17
`
`P1.18
`
`P1.19
`
`P1.20
`
`P1.21
`
`P2.1
`
`P2.2
`
`P2.3
`
`P2 .4
`
`Laser Programmable Metallic Vias, J.B. Bernstein, W. Zhang and C.H. Nicholas,
`University of Maryland, College Park, MD
`
`New Via Formation Process for suppressing the Leakage Current Between
`Adjacent Vias for Hydrogen Silicate Based Inorganic SOG lntermetal Dielectric, N.
`Oda, T. Usami, T. Yokoyama, A. Matsumoto, K. Mikagi, H. Gomi, and I. Sakai, NEC
`Corp., Kanagawa, Japan
`
`Study on the Stability of HDP-SiOF Film and IMD Application for 0.25pm LSI
`Device, H.J. Shin, S.J. Kim, B.J. Kim, H.K. Kang and M.Y. Lee, Samsung Electronics
`Co., Kyungki, Korea
`
`Chemical Vapor Deposition and Physical Vapor Deposition of Metal/Barrier Binary
`Stacks on Polytetrafluorethylene Low-k Dielectric, R. Talevi, S. Nijsten, H.
`Gundlach, A. Knorr, K. Kumar. 2. Bian, T. Rosenmayer*, A.E. Kaloyeros and R.E. Geer,
`State University of New York, Albany, NY and *W.L. Gore and Assoc., Eau Claire, WI
`
`Integration of Low k Spin-on Polymer (SOP) Using Electron Beam Cure for Non-
`Etch-Back Application, J.C.M. Hui, Y. Xu, C.Y. Foong, L. Marvin, L. Charles, L.Y.
`Shung, A. lnamdar*, J. Yang‘, J. Kennedy‘, M. Ross‘ and S.-Q. Wang, Chartered
`Semiconductor Manufacturing Ltd., Singapore and *AI|iedSigna|, Inc., Santa Clara, CA
`
`A Novel Wholly Aromatic Polyether as an lnterlayer Dielectric Material, T. Tanabe,
`K. Kita, M. Maruyama, K. Sanechika, M. Kuroki and N. Tamura, Asahi Chemical Industry
`Co., Ltd., Shizuoka, Japan
`
`A Method for Improving the Adhesion of PE-CVD SiO, to Cyclotenem 5021
`Polymeric lnterlayer Dielectric, E.O. Shaffer ll, M.E. Mills, D.D. Hawn, J.C. Liu* and
`J.P. Hummel‘, The Dow Chemical Co., Midland, MI and ‘IBM, Hopewell Junction, NY
`
`Twostep Planarized Al-Cu PVD Process Using Long Throw Sputtering
`Technology, T.-K. Ku, H.-C. Chen, Y. Mizusawa*, N. Motegi", T. Kondo*, S. Toyoda*,
`C. Wei", J. Chen" and L.-J. Chen, ERSO/ITRI, Taiwan, ROC, *ULVAC Japan, Ltd.,
`Japan, and **ULVAC Taiwan Branch, Taiwan, ROC
`
`0.60 pm Pitch Metal Integration in 0.25pm Technology, J.R.D. DeBord, V.
`Jayaraman, M. Hewson, W. Lee, S. Nair, H. Shimada, V.L. Linh, J. Robbins, A.
`Sivasothy, Texas Instruments lnc., Dallas. TX
`
`Study of Cu Contamination During Copper lntegraton in a Dual Damascene
`Architecture for Sub-Quarter Micron Technology. J. Torres, J. Palleau, P. Motte*, F.
`Tardif“ and H. Bernard‘, FT/CNET, Meylan, France, *SGS-Thomson Microelectronics.
`Crolles. France and “CEA/LETI, Grenoble, France
`
`Development of Cu Etch Process for Advanced Cu Interconnects, Y. Ye, D. Ma, A.
`Zhao, P. Hsieh, W. Tu, X. Deng, G. Chu, C. Mu’, J. Chow‘, P. Moon’ and S. Sherman‘.
`Applied Materials lnc., Santa Clara, CA and *lnte| Corp., Santa Clara, CA
`
`POSTER SESSION ll
`
`Measurement and Modeling of High-Speed Interconnect-Limited Digital Ring
`Oscillators: The Effect of Dielectric Anisotropy, A. Garg, Y. L. Le Coz, H.J. Greub.
`J.F. McDonald, and R.B. |verson', Rensselaer Polytechnic Institute, Troy, NY and
`‘Random Logic Corporation, Fairfax, VA
`
`A Case Study of RC Effects to Circuit Performance, C.S. Pai, P.W. Diodato and R.
`Liu, Bell Laboratories, Lucent Technologies, Murray Hill, NJ
`
`Modeling Microstructure Development in Trench-Interconnect Structures, J.
`Sanchez. Jr. and P. R. Besser*. The University of Michigan. Ann Arbor, MI and
`*Advanced Micro Devices. Sunnyvale, CA
`
`SAP — A Program Package for Three-Dimensional Interconnect Simulation, R.
`Sabelka and S. Selberherr, Institute for Microelectronics, Vienna, Austria
`
`205
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`208
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`211
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`214
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`

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`Comparison of Barrier Materials and Deposition Processes for Copper Integration
`
`M. Moussavi, Y. Gobil, L. Ulmer, L. Perroud, P. Motte"‘**, J. Torres*, F. Romagna*,
`M. Fayolle, J. Palleau* and M. Plissonnier**
`
`LETI (CEA Technologies Avancées). DMEL-CEA/G - 17, rue des Martyrs - 38054 Grenoble cedex 9 France
`*FR:ANCE TELECOM , CNETT/CNS, BP 98, 38243 Meylan cedex, France
`**Applied Materials France 11B, chemin de la Dhuy, 38246 Meylan cedex, France
`***SGS Thomson Microelectronics 850 rue Jean Monnet, 38926 Crolles cedex, France
`
`Abstract
`
`Experimental
`
`This paper reports the investigation of MOCVD (Metal
`Organic Chemical Vapor Deposition) TiN. and IMP
`(Ionized Metal Plasma) Ta and TaN thin films as barrier
`layers
`for
`copper metallization. Evaluation of both
`deposition
`techniques
`including
`step
`coverage, Cu
`adhesion, Cu diffusion and selectivity regarding Cu-CMP
`_process have been performed. Successful
`implementation
`with copper metallization in high aspect ratio line and via
`patterns is reported.
`
`A. Barrier Materials
`
`An Applied Materials Endura system using IMP (Ionized
`Metal Plasma) was used to deposit Ta and TaN barriers.
`Prior to film deposition, wafers were degassed at 350°C
`and sputter cleaned using a standard AMAT PCII reactor.
`CVD TiN was performed in P5000 reactor using TDMAT
`precursor with successive steps of deposition and plasma
`treatments.
`
`Introduction
`
`B. Copper Deposition Equipment
`
`integration density continuously increases,
`As circuit
`interconnection size is predicted to decrease both in vertical
`and lateral dimensions. Unfortunately,
`intrinsic properties
`of the materials currently used for interconnection such as
`resistivity and electromigration performance do not allow
`an optimal scaling. This explains the growing interest in
`copper
`for overcoming limitations of the conventional
`aluminium based alloys (1,2). The two most critical aspects
`for
`integration of copper metallization are the optimal
`choice of diffusion barrier material — the Cu diffusion in the
`active areas resulting into degradation of the devices- and
`diffusion bam'er material and copper deposition techniques.
`The barrier layer should meet stringent requirements: the
`thickness has to be small enough to not impact interconnect
`resistance while still acting as a good barrier against Cu
`diffusion. Several barrier materials have been reported as
`good candidates. TiN barrier, currently used with Al-based
`metallization, has shown convenient results (3). However
`other papers suggest that Tantalum and Tantalum nitride
`could be the best choice.
`In this work a comprehensive
`comparison of the TiN, Ta and TaN perfonnance was
`carried out with regards to Cu integration. A variety of
`solutions have been developed to deposit copper : Ionized
`Metal Plasma, CVD, combination of these techniques and
`the new electroplating method.
`
`IMP copper used as a seed layer was deposited on an
`Endura system. The Chemical Vapor Deposition of copper
`was performed in a Precision 5000 AMAT cluster tool.
`Two CVD chambers
`are
`available, one
`for copper
`deposition and the second for TiN-CVD. Copper was
`therefore deposited on TiN barrier, without vacuum break
`between TiN. The cluster equipment allows a clean and
`reproducible TiN/Cu interface. Copper Electroplating on
`various seed layers was perfonned on a Semitool Equinox
`system using pulsed current in order to achieve uniform
`films with high deposition rates up to 400 nm/min.
`
`C. Chemical Mechanical Pulisluhg
`
`Polishing experiments were carried out on a PRESI
`MECAPOL 550 polisher, using a RODEL ICIOOO pad
`stacked on a SUBA IV pad. The sluny is alumina—based
`and has to be mixed with hydrogen peroxide oxidizer prior
`to use (5).
`_
`Copper and barrier removal rates (RR) were deterrmned by
`polishing respectively Cu, TiN, Ta and TaN blanket wafers.
`Barrier layer selectivities were calculated by the following
`formula: Selectivity = Copper RR / Barrier RR.
`Planarization performance was investigated on topological
`wafers with copper line widths and oxide spaces varying
`from 03pm to 100nm.
`
`o1’7%S§—l383f2lé‘8/$10.00 © 1998 IEEE
`
`IITC 98-295
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`
`
`Figure 4. Copper CMP with Ta barrier
`(0.3 pm line width / 0.3 pm oxide space)
`
`Conclusion
`
`A variety of solutions for 0.25pm copper interconnect
`technology have been developed. Complete via filling was
`achieved by combination of CVD and IMP techniques, and
`by electroplating deposition. A comprehensive comparison
`of TiN, Ta and TaN materials as barrier layers for copper
`metallization has been carried out, as these three materials
`proved to block copper difiiision. TiN was suitable for
`usual CMP process, involving removal of the entire metal
`stack during polishing. Ta and TaN barriers
`showed
`excellent CMP stop layer capabilities. Therefore, these new
`materials can lead to a novel CMP approach, in which the
`barrier layer is used to prevent from oxide erosion.
`
`Acknowledgment
`
`This work has been carried out within the GRESSI
`Consortium between CEA-LETI and France Telecom-
`CNET. The authors would like to thank B. Chin, T-Y Yao,
`
`L. Chen and M. Bakli from Applied Materials for their
`active contribution.
`
`References
`
`l. D.Edelstein et al, "Full copper wiring in a sub-0.25pm CMOS ULSI
`technology", Proc. IEEE IEDM, 1997, pp. 773-776
`2. S.Venkatesan et al, "A high perfonnance 1.8V, 0.20mm CMOS
`technology with copper metallization", Proc. IEEE IEDM, 1997, pp.
`769-772
`3. C. Marcadal et al, "OMCVD TiN difiusion barrier for copper contact
`an via and line", Proc. VMIC, 1997, pp. 405-410
`4. C. Marcadal et al, "OMCVD Copper process for dual damascene
`metallization", Proc. VMIC, 1997, pp. 93-98
`_
`_
`5. M. Fayolle and F. Romagna, "Copper CMP evaluation zplanarrzatron
`issues", Proc. Materials for Advanced Metallization Conference,
`Villard de Lans France, 1997, pp. 135-141
`
`Figure3b. Electroplated Copper Film afier CMP
`
`C. Chemical Mechanical Polishing
`
`Barrier versus copper selectivity determined on full sheet
`wafers are reported on table I. Unlike TiN, Ta and TaN
`removal rates are much lower than copper removal rate.
`The elimination of these barrier layers was investigated on
`topological wafers. The 40nm TiN layer was entirely
`removed while keeping acceptable copper dishing and
`oxide erosion effects. The high selectivity of Ta and TaN
`barrier layers was confirmed on topological wafers. To
`quantitatively determine this effect, a thick Ta barrier layer
`(l00nm) was used. After polishing using the same
`conditions than for the TiN barrier layer, the remaining Ta
`barrier thickness was measured by SEM. As shown on
`figure 4, less than 5nm of the barrier layer were removed,
`demonstrating the excellent CMP stop layer capability of
`Ta material.
`
`Page 14 of 14
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`IITC 98-297
`
`Page 14 of 14