United States Patent [19]
`Zhang et a].
`
`[54] PROCESS FOR FORMING A
`SEMICONDUCTOR DEVICE
`
`[75] Inventors: Jiming Zhang. Austin; Dean J.
`De?ning. Del Valle. both of Tex.
`
`[73] Assignee: Motorola, Inc.. Schaumburg. Ill.
`
`[21] Appl. No.: 08/996,000
`[22] Filed:
`Dec. 22, 1997
`
`[51] Int. Cl.6 ................................................... .. H01L 21/00
`[52] US. Cl. ........................ .. 438/687; 438/687: 438/627;
`438/628; 438/643
`[58] Field of Search ............................ .. 438/653. 627-28.
`438/654. 656. 643. 644. 645. 648. 680.
`681. 658. 687
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,206,187
`5,231,053
`5,289,035
`
`4/1993 Doan et a1.
`7/1993 Bost et a1.
`2/1994 Bostet a1.
`
`..
`
`.... .. 437/192
`.... .. 437/190
`.... .. 257/750
`
`5,323,047
`
`6/1994 Nguyen . . . . . . . . .
`
`. . . . .. 257/384
`
`438/643
`2/1995 Gelatos et a1.
`5.391.517
`438/607
`5/1995 Fiordalice et al.
`5,420,072
`216/67
`5,468,339 11/1995 Gupta et a1. .... ..
`437/140
`5,614,437
`3/1997 Choudhury
`438/653
`5,677,238 10/1997 Gn et a1 ...... ..
`5,747,360
`5/1998 Nulman ......................................... .. 1/1
`
`FOREIGN PATENT DOCUMENTS
`
`O 163 830 A2 12/1985 European Pat. Off. ...... .. H011. 23/52
`0 673 063 A2 9/1995 European Pat. Off.
`H01L 21/768
`
`OTHER PUBLICATIONS
`
`Wolf et a1. Silicon Processing for the VLSI Era vol. 2. pp.
`273-276. 1990. no month.
`Han Sin Lee et al.. An Optimized Densi?cation of the Filled
`Oxide for Quarter Micro Shallow 'Il'ench Isolation (S11).
`1996 Symposium on VLSI Technology. Digest of Technical
`Papers. International Electron Devices Meeting. pp.
`158-159 (1966).
`
`USO05893752A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,893,752
`Apr. 13, 1999
`
`Torres. Advanced copper Interconnections for silicon
`CMOS technologies. Applied Surface Science 91 (1995) pp.
`112-123.
`Wang. Barriers Against Copper Di?usion into Silicon and
`Drift Through Silicon Dioxide. MRS Bulletin/Aug. 1994.
`pp. 30-39.
`Reid et al.. Evaluation of amorphous (Mo. Ta W)—Si-N
`diffusion barriers for <Si>/Cu metallizations. Elsevier
`Sequoia (1993). pp. 319-324.
`Wang et al.. Ditfusion barrier study on TaSi" and TaSirNy.
`Elsevier Sequoia (1993) pp. 169-174.
`Smolinsky et al.. Material Properties of Spin-on Silicon
`Oxide (SOX) for Fully Recessed NMOS Field Isolation. J.
`Electrochem. Soc.. vol. 137. No. 1. Jan. 1990. The Electro
`chemical Society. Inc.. pp. 229-234.
`Selective Oxidation of Titanium while forming Titanium
`Silicide at Polysilicon and Di?usions. IBM Technical Dis
`closure Bulletin vol. 27 No. 10A Mar. 1985.
`Frisa et 31.: US. appl. No. 8/804.589. ?led Feb. 26. 1997.
`Frisa et al.; US. appl. No. 08/887654 ?led Jul. 3. 1997.
`
`Primary Examiner—Charles Bowers
`Assistant Examiner—Thanh Nguyen
`Attorney, Agent, or F irm-George R. Meyer
`
`[57]
`
`ABSTRACT
`
`A semiconductor device comprises a substrate (100). ?rst
`conductive ?lm (22 and 32) over the substrate (100). and a
`second conductive ?lm (54 and 64) over the ?rst conductive
`?lm (22 and 32). The ?rst conductive ?lm includes a
`refractory metal and nitrogen. The ?rst conductive ?lm has
`a ?rst portion (22) that lies closer to the substrate and a
`second portion (32) that lies further from the substrate. The
`nitrogen percentage for the second portion (32) is lower than
`the nitrogen atomic percentage for the ?rst portion (22). The
`second conductive ?lm (54 and 64) includes mostly copper.
`The combination of portions (22 and 32) Within the ?rst
`conductive ?lm provides a good dilfusion barrier (?rst
`portion) and has good adhesion (second portion) with the
`second conductive ?lm (54 and 64).
`
`22 Claims, 5 Drawing Sheets
`
`964
`
`/ 922
`914
`
`/
`
`.
`
`34 / l/ //912,
`.32 1' /
`
`a
`
`932
`
`/
`
`//
`
`4&6 I
`
`u,
`
`/
`
`.
`/
`/
`
`I,
`/
`
`I, /1//
`
`.ll41—/ .
`
`m4 106 10a
`10;
`
`TSMC Exhibit 1004
`
`Page 1 of 10
`
`

`
`US. Patent
`
`Apr. 13, 1999
`
`Sheet Inf 5
`
`5,893,752
`
`/12
`
`12 f
`</
`/ / WA
`?? 114\
`11 / —
`
`\\ \ \\\’ / / L23 7 116/ \\\ \ \\ \j\\ \LJ
`
`
`
`116
`
`109
`
`109 110
`
`—
`
`J/ KL
`{L
`104 105 108
`107
`
`\I
`‘\ \\\\2/
`\r/ \\~
`104 W 10 M
`w
`
`FIG.J
`
`/
`/ 109
`
`104 106 108
`107
`
`FIG. 2
`
`Page 2 of 10
`
`

`
`US. Patent
`
`Apr. 13, 1999
`
`Sheet 2 of 5
`
`5,893,752
`
`F]G.3
`
`1k
`100-‘
`
`CONCENTRATION
`(ATOMIC %)
`
`50
`
`DISTANCE (A)
`
`FIG. 4
`
`Page 3 of 10
`
`

`
`US. Patent
`
`Apr. 13, 1999
`
`Sheet 3 of 5
`
`5,893,752
`
`12
`f
`
`22
`
`12
`f
`32
`
`54
`
`i i/
`109
`
`11
`
`104 106 108
`107
`
`FIG.5
`
`11
`
`/_ / 109
`
`»
`
`10
`
`104 106 108
`107
`
`FIG. 6
`
`Page 4 of 10
`
`

`
`US. Patent
`U.S. Patent
`
`Apr. 13, 1999
`Apr. 13, 1999
`
`Sheet 4 of 5
`Sheet 4 of 5
`
`5,893,752
`5,893,752
`
`54
`54
`
`22 32 54
`22 32 54
`
`
`
`1 1
`
`
`
`
`
`
`
`
` E 7////:7////.
`
`
`
`ICCCCCCCCCCQCKCCCCV
`
`3C§C§CCCCCCC§§V
`
`109
`
`V
`
`V
`
`104 106 108
`107
`
`E?
`
`FIG. 7
`FIG. 7
`
`82
`[8232
`22 54
`22 54 P/ 32
`
`a4
`’/8432
`22 54
`22 54 2/ 32
`
`
`
`31111111111133‘
`
`110
`.:;.a\‘\\‘n\n\\\\\V
`
`
`
`L\\\\\\un\\\§‘5..‘.E
`
`104 106 108
`107
`
`
`
`64
`
`114
`
`
`
`
`
`
`
`
`
`
`F] G. 8
`FIG’. 8
`
`Page 5 of 10
`
`Page 5 of 10
`
`

`
`US. Patent
`U.S. Patent
`
`Apr. 13, 1999
`Apr. 13, 1999
`
`Sheet 5 of 5
`Sheet 5 0f 5
`
`5,893,752
`5,893,752
`
`954
`954
`932
`932 ,
`
`82
`32
`
`22 54
`
`
`
`L
`/ 109
`n\‘u\\\\“\‘8 5.9!i§\V: .=-__—‘.a\\\\‘\‘\\\\‘\s
`/
`102
`
`104 106 108
`107
`
`FIG. .9
`FIG. .9
`
`Page 6 of 10
`
`964
`922
`914
`
`910
`
`
`
`3’??? iffiiitfifi
`
`%@|LEJdJMLJ
`i
`
`‘CC CCCC§CCCCCC§CCCV
`
`
`
`
`
`Page 6 of 10
`
`

`
`5.893.752
`
`1
`PROCESS FOR FORMING A
`SEMICONDUCTOR DEVICE
`
`RELATED APPLICATIONS
`
`This is related to US. patent application Ser. No. 08/804.
`589 ?led Feb. 26. 1997. and Ser. No. 08/887654 ?led Jul.
`3. 1997. both of which are assigned to the current assignee
`hereof.
`
`FIELD OF THE INVENTION
`
`This invention relates in general to semiconductor devices
`and processes for forming semiconductor devices. and more
`particularly. to semiconductor devices and processes for
`forming those devices having metal interconnects.
`
`BACKGROUND OF THE INVENTION
`
`10
`
`2
`the substrate surface after forming the tantalum-rich tanta
`lum nitride ?lm;
`FIG. 5 includes an illustration of a cross-sectional view of
`the substrate of FIG. 3 after forming a copper seed ?lm;
`FIG. 6 includes an illustration of a cross-sectional view of
`the substrate of FIG. 5 after electroplating a copper ?lm over
`the copper seed ?lm:
`FIG. 7 includes an illustration of a cross-sectional view of
`the substrate of FIG. 6 after polishing the substrate to
`remove those portions of the copper ?lms that overlie the
`tantalum-rich tantalum nitride ?lm outside interconnect
`trenches and contacts;
`FIG. 8 includes an illustration of a cross-sectional view of
`the substrate of FIG. 7 after polishing the tantalum-rich
`tantalum nitride and tantalum nitride ?lms to form wirings
`for the semiconductor device; and
`FIG. 9 includes an illustration of a cross-sectional view of
`a substantially completed semiconductor device.
`Skilled artisans appreciate that elements in the ?gures are
`illustrated for simplicity and clarity and have not necessarily
`been drawn to scale. For example. the dimensions of some
`of the elements in the ?gures may be exaggerated relative to
`, other elements to help to improve understanding of embodi»
`25
`ments of the present invention.
`
`Typically metalization schemes require barrier or adhe
`sion ?lms in order for a metal ?lm to properly adhere to and
`20
`make good contact resistance with underlying layers. A
`common metalization scheme for aluminum interconnects
`uses a combination of a titanium ?lm followed by a titanium
`nitride ?lm. over which. an aluminum or an aluminum alloy
`?lm is deposited. Aluminum suffers from several problems.
`such as its relative high resistance compared to copper and
`electromigration problems.
`Attempts have been made to use tantalum and tantalum
`related compounds in forming interconnect structures. For
`example. either a pure tantalum ?lm or a tantalum nitride
`?lm is used as a barrier/adhesion ?lm for a copper inter
`connect. However. tantalum can be very dii?cult to remove
`using a polishing process. and tantalum nitride has adhesion
`problems with some types of copper ?lms.
`Other barrier/adhesion ?lms could be used for the inter
`connect schemes. In one. a titanium ?lm is deposited fol
`lowed by a titanium nitride film that is followed by a
`titanium-rich titanium nitride ?lm. Following the deposition
`of the titanium-rich titanium nitride ?lm. an oxygen plasma
`is then used to convert that ?lm to a titanium oxynitride
`compound. Unfortunately. titanium oxynitride can be too
`resistive. Although tantalum can be used in place of titanium
`in the oxynitn'de compound. the problems with the relatively
`high resistance is expected to continue to be a problem.
`In another interconnecting scheme. an aluminum or alu
`minum alloy ?lm can be capped with a titanium-rich tita~
`nium nitride compound followed by a stoichiomctric tita
`nium nitride compound. As previously discussed. copper
`does not adhere to titanium nitride very well. Even if
`tantalum is used to replace the titanium. the adhesion
`problem still exists with tantalum nitride.
`
`30
`
`35
`
`45
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The present invention is illustrated by way of example
`and not limitation in the accompanying ?gures. in which like
`references indicate similar elements. and in which:
`FIG. 1 includes an illustration of a cross-sectional view of
`a portion of a semiconductor device substrate after forming
`interconnect trenches and contact openings;
`FIG. 2 includes an illustration of a cross-sectional view of
`the substrate of FIG. 1 after forming a tantalum nitride ?lm;
`FIG. 3 includes an illustration of a cross-sectional view of
`the substrate of FIG. 2 after forming a tantalum-rich tanta
`lum nitride ?lm;
`FIG. 4 includes an illustration of a plot illustrating the
`change in concentration of various elements with depth from
`
`55
`
`65
`
`DETAILED DESCRIPTION
`
`A semiconductor device comprises a substrate. ?rst con
`ductive ?lm over the substrate. and a second conductive ?lm
`over the ?rst conductive ?lm. The ?rst conductive ?lm
`includes a refractory metal and nitrogen. The ?rst conduc
`tive ?lm has a ?rst portion that lies closer to the substrate and
`a second portion that lies fru'ther from the substrate. The
`nitrogen percentage for the second portion is lower than the
`nitrogen atomic percentage for the ?rst portion. The second
`conductive ?lm includes mostly copper. The combination of
`portions within the ?rst conductive ?lm provides a good
`diffusion barrier (?rst portion) and has good adhesion
`(second portion) with the second conductive ?lm. The
`present invention is better understood after reading the
`embodiments described below.
`FIG. 1 includes a portion of a semiconductor device
`substrate 100. ?eld isolation regions 102. and doped regions
`104. As used in the speci?cation. the semiconductor device
`substrate 100 includes a monocrystalline semiconductor
`wafer. a semioonductor-on-insulator wafer or any other
`substrate used in forming semiconductor devices. A gate
`dielectric layer 106 is formed over the substrate 100 fol
`lowed by a silicon ?lm 107 and a silicide ?lm 108. The
`silicide ?lm 108 and silicon ?lm 107 are patterned to form
`a gate electrode as illustrated in FIG. 1. Sidewall spacers 109
`are formed adjacent to the gate electrode that includes the
`silicon ?lm 107 and the silicide ?lm 108. Although not
`shown. silicide regions may overlie the doped regions 104.
`A ?rst interlevel dielectric layer 11 overlies the substrate
`100 and gate electrode. The ?rst ILD layer 11 includes a ?rst
`etch-stop ?lm 110. a ?rst planarized insulating film 112. a
`second etch-stop ?lm 114. and a second planarization insu
`lating ?lm 116. All the ?lms 110 through 116 typically are
`insulators. In one particular embodiment. the etch-stop ?lms
`include nitride films. such as silicon nitride. and the pla
`narized insulating ?lms 112 and 116 include oxides.
`Although not shown. an antire?ective ?lm including silicon
`rich silicon oxynitride could be formed as part of the ILD
`layer 11 and would be formed over the second planarized
`insulating ?lm 116 but is not shown. The ?rst ILD layer 11
`
`Page 7 of 10
`
`

`
`5.893.752
`
`3
`is then patterned to form openings 12. which include inter
`connect trench portions 122 and Contact portions 124. The
`interconnect trench portions 122 are formed within layer or
`?lm 116 and are generally wider than the contact portions
`124. which extend through the ?rst and second etch-stop
`?lms 110 and 114 and the ?rst planarized insulating ?lm 112.
`The structure up to this point in time is formed using
`conventional methods.
`A tantalum nitride ?lm 22 is then deposited over the
`substrate and Within the openings 12. The tantalum nitride
`?lm 22 typically includes 33 to 50 atomic percent nitrogen
`with the balance essentially being tantalum. This layer is
`formed and can contact the doped regions 104 as illustrated
`in FIG. 2. The substrate is then further processed to form a
`tantalum-rich tantalum nitride ?lm 32 that overlies the
`tantalum nitride ?lm 22 as shown in FIG. 3. The combina
`tion of the ?lms 22 and 32 are a ?rst conductive ?lm that is
`an adhesion/barrier ?lm for the wirings being formed. The
`?rst conductive ?lm is in a range of approximately 10 to 500
`angstroms. and typically is in a range of approximately 100
`to 300 angstroms.
`The formation of the tantalum nitride and tantalum-rich
`tantalum nitride ?lms 22 and 32 are formed as follows. The
`substrate is placed on a susceptor within a processing
`chamber. such as a deposition apparatus. The susceptor is
`heated to a temperature in a range of approximately 50 to
`250° C. The pressure during the deposition of the two ?lms
`is generally in a range of approximately 15 to 40 millitorr.
`The pressure is dependent on the aspect ratio and geometry
`of the structure being deposited The direct current (DC)
`power used to sputter material is usually in a range of 0.5 to
`3 kilowatts. and more speci?cally. is typically in a range of
`1.2 to 1.8 kilowatts. The radio frequency (RF) power used to
`create a plasma within the sputtering chamber is usually in
`the range of 1 to 2 kilowatts. and more speci?cally. is
`typically 1.3 to 1.7 kilowatts.
`The deposition of the two ?lms 22 and 32 is typically
`performed as one sequence during a single evacuation cycle.
`During the ?rst portion of the deposition. where the tantalum
`nitride ?lm 22 is close to the stoichiometric composition
`(T aN). there is no biasing of the substrate. During this time.
`a nitrogen-containing gas and an inert gas. such as argon. are
`directed toward a sputtering target. The nitrogen-containing
`gas includes nitrogen. ammonia or the like. In forming ?lm
`32. the nitrogen-containing gas is terminated while the inert
`45
`gas continues to flow. and the substrate becomes biased at
`approximately negative 75 to negative 80 volts.
`During this sputter deposition. the atomic percent of
`tantalum within the layer increases while the atomic percent
`of the nitrogen decreases as illustrated in FIG. 4. FIG. 4
`includes a plot of concentration (in atomic percent) as a
`function of the distance from the exposed surface to the ?rst
`lLD layer 11. The tantalum-rich tantalum nitride ?lm has a
`range of approximately 0-30 atomic percent nitrogen. In this
`particular embodiment. the upper surface of the tantalum
`rich tantalum nitride ?lm is substantially pure tantalum and
`has essentially no nitrogen atoms. A lower atomic percent
`nitrogen at the upper surface typically gives better adhesion
`to copper ?lms. At the upper surface. the atomic percent
`tantalum may be at least 95% and the atomic percent
`nitrogen may be less than 5% if copper adhesion is particu
`larly problematic. In an alternate embodiment. the nitrogen
`containing and inert gases can be terminated and the cham
`ber evacuated before ?owing just the inert gas. A ?rst
`conductive ?lm with discrete portions will be formed. unlike
`a previous embodiment that does not evacuate between the
`steps of forming the ?lms 22 and 32.
`
`65
`
`50
`
`55
`
`25
`
`30
`
`35
`
`4
`In one particular embodiment. the time period when the
`nitrogen-containing gas ?ows and biasing is o? (?lm 22) is
`approximately equal to the time period when the nitrogen
`containing gas ?ow is terminated and the biasing is on (?lm
`32). However. time periods may be di?erent. In some
`embodiments. the tantalum nitride ?lm 22 is thicker than the
`tantalum-rich tantalum nitride ?lm 32. The combined thick
`ness of the two ?lms 32 and 22 is in a range of approxi
`mately 10 to 500 angstroms. and typically is in a range of
`approximately 100 to 300 angstroms.
`A copper seed ?lm 54 is then deposited over the tantalum
`rich tantalum nitride ?lm 32 as shown in FIG. 5. The copper
`seed ?lm 54 can be deposited by a number of methods
`including physical vapor deposition. chemical vapor
`deposition. or the like. If metal-organic chemical vapor
`deposition used. the copper precursor can be any one or
`more of the following: copper hexa?uoroacetyl vinyltrim
`ethylsilane (Cu(hfac)(VTMS)); copper hexa?uoroacetyl
`3-hexyne (Cu(hfac)(3-hexyne)); or the like. Additionally
`copper (11) B-diketonate compounds could be used. After the
`copper seed ?lm 54 has been deposited. an electroplated
`copper ?lm 64 is then formed over all the substrate as shown
`in FIG. 6. The thickness of the electroplated copper ?lm 64
`is sul?ciently thick to ?ll the interconnect trench portions of
`the openings 12. The combination of the ?lms 54 and 64 are
`a second conductive ?lm. which is mostly copper. for the
`wirings being formed.
`A ?rst chemical-mechanical polishing step is performed
`to remove all of the copper ?lms 54 and 64 that overlie the
`tantalum-rich tantalum nitride ?lm 32 as shown in FIG. 7.
`The ?rst conductive ?lm (?lms 22 and 32) is a polish-stop
`when polishing the second conductive ?lm (?lms 54 and
`64'). A second polishing step is performed to remove the
`tantalum-rich tantalum nitride ?lm 32 and the tantalum
`nitride ?lm 22 overlying the second planarized insulating
`?lm 116 outside the openings 12 as shown in FIG. 8. At this
`point in the process. interconnect wirings 82 and 84 are
`formed as shown in FIG. 8. Wiring 84 includes an intercon
`nect portion and a contact portion that contacts one of the
`doped regions 104. Electrical connections using contacts are
`made to the interconnect 82 but are not illustrated in FIG. 8.
`Processing continues to form a substantially completed
`device as illustrated in FIG. 9. At this point a third etch-stop
`?lm 910 is formed over the wirings 82 and 84. a third
`planarized insulating ?lm 912 is formed over the third
`etch-stop ?lm 910 and a fourth etch-stop film 914 is formed
`over the third planarized insulating ?lm 912. Although not
`shown. a fourth planarized insulating ?lm is also formed.
`The ?lms making up the second ILD layer that includes
`?lms 910. 912 and 914 is patterned to form interconnect
`trenches and contact openings where required using a con
`ventional process. Although not shown in FIG. 9. the open
`ings are formed that extend through the ?lms 910. 912 and
`914.
`After forming the opening. a tantalum nitride ?lm 922 is
`deposited followed by tantalum-rich tantalum nitride ?lm
`932 followed by a copper seed ?lm 954 and an electroplated
`copper ?lm 964. After performing the appropriate polishing
`steps. a passivation layer 98 is then formed to form the
`substantially completed device. Although not shown. addi
`tional interlevel dielectric layers. wiring layers. and other
`electrical connections can be made but are not illustrated in
`FIG. 9.
`Other alternatives to the present invention could be used.
`In addition to using tantalum. other refractory metals could
`be used in forming the barrier/adhesion ?lm. The tantalum
`
`Page 8 of 10
`
`

`
`5.893.752
`
`10
`
`15
`
`20
`
`25
`
`35
`
`5
`can be replaced by another refractory metal. such as
`tungsten. molybdenum. or the like. In still other
`embodiments. semiconductor atoms can be incorporated in
`either or both of the ?lms 32 and 22. For example. tantalum
`silicon nitride and tantalum-rich tantalum silicon nitride
`could be formed. Alternatively. germanium atoms or both
`silicon and germanium atoms can be present. In forming a
`refractory metal-semiconductor-nitrogen compound. typi
`cally a target used for sputtering includes the refractory
`metal and semiconductor atoms.
`In one speci?c environment. tantalum silicide can be used
`and tantalum silicon nitride can be formed by sputtering the
`tantalum silicide target with a combination of argon and
`nitrogen gases. The tantalum-rich tantalum silicon nitride
`?lm can be formed similar to the tantalum-rich tantalum
`nitride ?lm wherein the nitrogen gas is terminated and the
`argon layer is directed toward the target to remove the
`remaining tantalum silicon nitride skin left on the target
`surface from the prior sputtering.
`In yet another embodiment. a substantially pure tantalum
`?lm. a tantalum-rich tantalum nitride ?lm. or a tantalum
`silicon nitride ?lm can be formed before forming the tan
`talum nitride ?lm 22. In one embodiment. a tantalum target
`can be sputtered for a short period of time to form an initial
`tantalum ?lm followed by a tantalum nitride ?lm and a
`tantalum-rich tantalum nitride ?lm. This embodiment may
`allow better contacts to be formed to substrates and silicides
`because the tantalum ?lm may react with native oxide
`present on those surfaces.
`In other structures. a single inlaid wirings can be formed
`In this particular case. the thickness of the tantalum nitride
`?lm 22 and tantalum-rich tantalum nitride ?lm 32 can be
`increased compared to the dual inlaid structure as illustrated
`in FIGS. 1-9.
`In still another embodiment. the combination of the
`copper seed ?lm 54 and the electroplated copper ?lm 64 can
`be replaced by a single copper ?lm formed by chemical
`vapor deposition or physical vapor deposition. When form
`ing this ?lm. the substrate can be heated such that copper can
`flow into the openings as required. In this case. the substrate
`or susceptor temperature is typically in a range of approxi
`mately 350—450° C. Care should be exercised as the integ
`rity of the tantalum nitride barrier ?lm may be jeopardized
`if the temperature is taken too high. The temperature during
`the deposition is high enough to allow the copper to ?ow but
`not so that the integrity of the tantalum nitride barrier ?lm
`is jeopardized These copper-?owing embodiments achieve
`bene?ts. such as reducing polishing time and dishing.
`Embodiments of the present invention do offer bene?ts
`that are not seen with prior art methods. The tantalum nitride
`?lm is a good barrier. but the use of tantalum-rich tantalum
`nitride in conjunction with the tantalum nitride allows for a
`better adhesion. particularly in the case of chemical vapor
`deposited copper ?lms. The inventors believe that if the
`nitrogen content in the film 32 is too high. a cyanide
`compound may be formed that adversely affects the adhe
`sion. By keeping the nitrogen concentration at the surface
`that contacts copper relatively low. better adhesion can be
`achieved.
`A further bene?t is that the improved adhesion should also
`achieve better contact resistance. Further. embodiments of
`the present invention reduce the effects of electromigration.
`Still another bene?t is that embodiments can use presently
`existing equipment without the use of exotic materials or
`having to develop marginal processes.
`In the foregoing speci?cation. the invention has been
`described with reference to speci?c embodiments. However.
`
`50
`
`55
`
`65
`
`6
`one of ordinary skill in the art appreciates that various
`modi?cations and changes can be made without departing
`from the scope of the present invention as set forth in the
`claims below. Accordingly. the speci?cation and ?gures are
`to be regarded in an illustrative rather than a restrictive
`sense. and all such modi?cations are intended to be included
`within the scope of present invention. In the claims. means
`plus-function clause(s). if any. cover the structures described
`herein that perform the recited function(s). The mean-plus
`function clause(s) also cover structural equivalents and
`equivalent structures that perform the recited function(s).
`We claim:
`1. A process for forming a semiconductor device com
`prising the steps of:
`placing a substrate in a processing chamber;
`forming a ?rst conductive ?lm that includes a refractory
`metal and nitrogen over the substrate. wherein:
`the ?rst conductive ?lm includes a ?rst portion and a
`second portion;
`the ?rst portion lies closer to the substrate and has a ?rst
`nitrogen atomic percentage;
`the second portion lies further from the substrate has a
`second nitrogen atomic percentage that is lower than
`the ?rst nitrogen atomic percentage; and
`a change between the ?rst nitrogen atomic percent and
`the second atomic percent within the ?rst conductive
`?lm is essentially continuous; and
`forming a second conductive ?lm over the ?rst conductive
`?lm. wherein the second conductive ?lm includes
`mostly copper.
`2. The process of claim 1. wherein the ?rst nitrogen
`atomic percentage is in a range of approximately 33-50
`atomic percent nitrogen.
`3. The process of claim 1. wherein the second nitrogen
`atomic percentage is in a range of approximately 0-30
`atomic percent nitrogen.
`4. The process of claim 1. wherein the refractory metal is
`selected from a group consisting of tantalum. tungsten. and
`molybdenum.
`5. The process of claim 1. wherein the second portion
`further comprises semiconductor atoms.
`6. The process of claim 1. wherein the ?rst conductive
`?lm includes an uppermost surface that is furthest from the
`substrate. and. wherein the ?rst conductive ?lm at the
`uppermost surface has essentially no nitrogen atoms.
`7. The process of claim 1. wherein the step of forming the
`?rst conductive ?lm is performed in the processing chamber
`and includes steps of:
`depositing the ?rst portion while a nitrogen-containing
`gas ?ows into the processing chamber; and
`depositing the second portion on the ?rst portion. wherein
`the nitrogen-containing gas has a lower ?owrate com
`pared to the step of depositing the ?rst portion.
`8. The process of claim 7. further comprising a step of
`depositing a third portion of the ?rst conductive ?lm before
`the step of depositing the ?rst portion.
`9. The process of claim 7. wherein the nitrogen
`containing gas is reduced to zero ?ow during the step of
`depositing the second portion.
`10. The process of claim 7. wherein the ?rst portion is
`thicker than the second portion.
`11. The process of claim 1. wherein the ?rst conductive
`?lm has a thickness in a range of approximately 10 to 500
`angstroms.
`12. The process of claim 1. wherein the step of forming
`the second conductive ?lm includes a step of depositing at
`
`Page 9 of 10
`
`

`
`5.893.752
`
`7
`least a portion of the second conductive ?lm by metal
`organic chemical vapor deposition.
`13. The process of claim 1. wherein the step of forming
`the second conductive ?lm includes a step of depositing at
`least a portion of the second conductive ?lm using physical
`vapor deposition. wherein:
`the substrate is placed on a susoeptor; and
`at least one of the substrate and the susceptor is at a
`temperature in a range of approximately 350—450° C.
`during the step of depositing.
`14. The process of claim 1. further comprising a step of
`forming a passivation layer over the ?rst and second con
`ductive ?lms.
`15. The process of claim 5. wherein the second portion
`comprises semiconductor atoms selected from a group con
`sisting silicon and germanium.
`16. The process of claim 1. further comprising forming an
`insulating layer prior to forming the ?rst conductive ?lm.
`wherein the ?rst portion contacts the insulating layer.
`17. The process of claim 16. wherein the ?rst portion
`consists essentially of tantalum and nitrogen. and wherein
`the ?rst nitrogen atomic percent is in a range of approxi
`mately 33-50 atomic percent.
`18. A process for forming a semiconductor device com
`prising the steps of:
`forming a patterned insulating layer over a substrate.
`wherein the patterned insulating layer includes an
`opening;
`forming a ?rst conductive ?lm that includes tantalum and
`nitrogen. wherein:
`
`10
`
`15
`
`25'
`
`8
`the ?rst conductive ?lm includes a ?rst portion and a
`second portion;
`the ?rst portion lies closer to the substrate and has a ?rst
`nitrogen atomic percentage; and
`the second portion lies further from the substrate and
`has a second nitrogen atomic percentage that is lower
`than the ?rst nitrogen atomic percentage; and
`forming a second conductive film on the ?rst conductive
`?lm. wherein the second conductive ?lrn includes
`mostly copper;
`polishing the second conductive ?lm to remove the sec
`ond conductive ?lrn overlying the patterned insulating
`layer outside of the opening; and
`polishing the ?rst conductive ?lm to remove the ?rst
`conductive ?lm overlyn'ng the patterned insulating layer
`outside of the opening.
`19. The process of claim 18. wherein the step of forming
`the second conductive ?lm includes a step of depositing at
`least a portion of the second conductive ?lm by metal
`organic chemical vapor deposition onto the second portion
`of the ?rst conductive ?lm.
`20. The process of claim 18. wherein the second portion
`further comprises semiconductor atoms selected from a
`group consisting silicon and germanium.
`21. The process of claim 18. wherein the first portion
`contacts the patterned insulating layer.
`22. The process of claim 21. wherein the ?rst nitrogen
`atomic percent is in a range of approximately 33-50 atomic
`percent.
`
`Page 10 of 10