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`
`Advanced Semiconductor
`Manufacturing Conference and Workshop
`
`World Class Manufacturing
`
`THE FAIRMONT COPLEY PLAZA
`
`Boston, Massachusetts USA CONFERENCE SESSIONS
` SEPTEMBER 23 - 25, 1998
`ayaa(15 @ISSN:
`IEEE CATALOG NUMBER 98CH36168
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`> YIELD MODELING & ANALYsIS
`> OVERALL EQUIPMENT EFFICIENCY
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`SPONSOREDBY:
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`Materials International (SEMI)
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`and Manufacturing
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`ASME_proceedimgs ( Teee/sem | Advawced Semicoudector
`‘manufacturing Comfereuce aud WorkShop
`IEEE/SEMI®
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`Advanced Semiconductor
`Manufacturing Conference and Workshop
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`1998
`
`IEEE/SEMI
`Advanced
`Semiconductor
`Manufacturing
`
`Conference
`And Workshop
`
`Theme — Semiconductor Manufacturing: Meeting the Challenges of
`the Global Marketplace
`
`ASMC 98 PROCEEDINGS
`
`The IREE/SEMIAdvanced Semiconductor Manufacturing Conference and Workshopis an
`annual forum that provides a venue for the presentation of methodologies, approaches and
`techniques required to achieve world class semiconductor manufacturing.
`A key role this
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`September 23 — 25, 1998
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`
`1998 PROCEEDINGS
`[EEE/SEMI ADVANCED SEMICONDUCTOR
`MANUFACTURING CONFERENCE AND
`WORKSHOP(ASMC) 1s B71
`
`PERMISSION TO REPRINT OR Copy:
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`beyond thelimit of U.S. copyrightlaw for private use of patrons thosearticles in this volume that
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`Copyright © 1998 by Institute of Electrical & Electronics Engineering, Inc.EEE) and
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`Refer to the IEEE Catalog Number, printed below:
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`0-7803-4380-8
`0-7803-4381-6
`0-7803-4382-4
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`1078-8743
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`Keynote Address: Foundry Industry Update, Don Brooks, UMC
`
`International Session
`
`Yield Management for Development and Manufactureof Integrated Circuits
`Hiroshi Koyama and Masayuki Inokuchi, JEOL Lid.
`
`Statistical Methods for Measurement Reduction in Semiconductor Manufacturing
`Richard Babikian, /ntel Ireland Limited; Curt Engelhard, Intel Corp.
`
`America, Japan and Europe — Which Areas Have the Edge in CustomerSatisfaction and Why
`Christine D. Burgeson, VLSI Research Inc.
`
`Contamination Free Manufacturing
`
`Effects of Process Parameters on Particle Formation in SiH,/N,0 PECVD and WF, CVD Processes
`Z. Wu, S. Nijhawan, S. A. Campbell, N. Rao and P.H. McMurry, University ofMinnesota
`
`Overcoming the Barriers to Cleaning with Bubble-Free Ozonated De-Ionized Water
`Timothy Bush, Steven Hardwick and Michael Wikol, W.L. Gore and Associates, Inc.
`
`In-Situ Particle Monitoring in a Vertical Poly Furnace
`Peter Glass and Joe Kudlacik, JBM Microelectronics Division; Ray Burghard, Pacific Scientific Instruments Group
`
`Advanced Aqueous Wafer Cleaning in Power Semiconductor Device Manufacturing
`RS. Ridley, Sr., T. Grebs, J. Trost, R. Webb, M. Schuler, R.F. Longenberger, T. Fenstemacher and M. Caravaggio, Harris Semiconductor
`
`Residual Gasses Investigation for Elimnating Contamination In LPCVD Si,N, Process
`N. Zhang, G. Magloczki, S. Aumick, G. Chiusano, S. Beckett, G. Nicholls and L. Stearns, MiCRUS
`
`Advantages to Point of Use Filtration of Photoresists in Reducing Contamination on the Wafer Surface
`Dennis Capitanio, Ph.D., Pall Corp.
`
`Advanced Metrology
`
`Matching Automated CD SEMsin Multiple Manufacturing Environments
`John Allgair and Dustin Ruehle, Motorola, Inc.; John Miller and Richard Elliott, KLA-Tencor Corp.
`
`Sidewall Angle Measurements Using CD SEM
`Bo Su, Tony Pan, Ping Li, Jeff Chinn, Applied Materials Inc.; Xuelong Shi and Mircea Dusa, National Semiconductor Corp.
`
`Uses of Corona Oxide Silicon (COS) Measurements for Diffusion Process Monitoring and Troublshooting
`Richard G. Cosway, Kelvin B. Catmull, Janie Shray, Robert Naujokaitis, Meagan Peters and Don Grant, Motorola,Inc.;
`Gregory Horner and Brian Letherer, Keithley Instruments Inc.
`
`Effective Defect Detection and Classification Methodology Based on Integrated Laser Scanning Inspection and
`Automatic Defect Classification
`Yong-Hui Fan, Ph.D. and Yoel Moalem, KLA-Tencor Corp.
`
`The Quantitation of Surface Modifications in 200 and 300 mm Wafer Processing with an Automated Contact Angle System
`Ronald Carpio, SEMATECH, David Hudson, AST Products, Inc.
`
`Correlation of Ellipsonometric Modeling Results To Observed Grain Structure for OPO Film Stacks
`Tod E. Robinson, KLA-Tencor Corp.
`
`Cost Reduction
`
`Beyond Cost-of-Ownership: A Casual Methodology for Costing Wafer Processing
`Stephanie Miraglia, Peter Miller, Thomas Richardson, Gregory Blunt and Cathy Blouin, JBM Microelectronics Division
`
`A Study in the Continuous Improvement Process: Implementation of an Optimized Scrubber to Replace TEOS Backside
`Etch Post SOG Etchback
`W. Au, D. Parks and P. Esquivel, VLSI Technology,Inc.
`
`Simulation of Test Wafer Consumption in a SemiconductorFacility
`Bryce Foster, Doron Meyersdorf, José Padillo and Rafi Brenner, TEFEN Lid.
`
`+ Not available at time ofprinting
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`Improvement of Silicon Wafer Minority Carrier Lifetime Through the Implementation of a Pre-Thermal Donor Anneal
`Cleaning Process
`;
`;
`a
`Larry Martines, Charley Wang and Tom Hardenburger, UniSil Corporation; Nancie Barker and Brian Sohmers, Siliconix Corporation
`
`Design for Manufacturability: A Key to Semiconductor Manufacturing Excellence
`R. Wilcox, T. Forhan, G. Starkey and D. Turner, JBM Microelectronics Division
`
`Advanced Processing/Photo & Etch
`
`Highly Selective Oxide to Nitride Etch Processes on BPSG/Nitride/Oxide Structures in a MERIE Etcher
`W.Graf and G. Skinner, SJEMENS, D.Basso, J.M. Martin and E. Sabouret, JBM France; F. Gautier, Applied Materials
`
`Overview of Plasma Induced Damage After Dry Etch Processing
`Yuri Karzhavin and Wei Wu, Motorola,Inc.
`
`Wet Chemical Cleaning for Damaaged Layer RemovalInside the Deep Sub-Micron Contact Hole
`Mitsuo Miyamoto, Morita Chemical Industries Co., Lid.; Hideto Gotoh, Texas Instruments, Japan
`Effects of Photoresist Foreshortening on an Advanced Ti/AICu/Ti Metallurgy and W Interconnect Technology (Abstract)
`C. Whiteside, M. Rutten, H. Trombley, H. Landis and M. Boltz, JBM Microelectronics Division
`
`FC2: Off-Axis Focus Control For Critical Level I-Line Photolithography
`Christopher H. Putnam,Jacek K. Tyminski, Sean J. McNamara, Nikon Precision Inc.
`
`Keynote Address: Sub-0.25 micron Interconnection Scaling: Damascene Copper versus Subtractive Aluminum
`Anthony K.Stamper, Sr. T.L. McDevitt and S. L. Luce, IBM MicroelectronicsDivision
`
`Advanced Processing/A New Era of Interconnect Technology
`CopperInterconnect - Technology New Paradigms for BEOL Manufacturing
`Kenneth Rose and Ramon Mangaser, Rensselaer Polytechnic Institute
`
`Developmentofa Production Worthy Copper CMP Process
`K. Wijekoon, S. Mishra, S. Tsai, K. Puntambekar, M. Chandrachood, F. Redeker, R. Tolles, B. Sun, L. Chen, T. Pan, P. Li, S. Nanjangud.
`G.Amico, AppliedMaterials, Inc,; J. Hawkins, T. Myers, R. Kistler, V. Brusic, S. Wang,I. Cherian, L. Knowles, C. Schmidt,
`C. Baker, Cabot Corporation
`
`?
`
`Cu CMPwith Orbital Technology. Summary ofthe Experience
`Y. Gotkis, D. Schey, S. Alamgir, J. Yang, K. Holland, Integrated Process Equipment Corporation (IPEC)
`A Study ofPost-Chemical-Mechanical Polish Cleaning Strategies
`C. Huynh, M. Rutten, R. Cheek and H. Linde, IBM Microelectronics Division
`Process Control and Monitoring with Laser Interferometry Based Endpoint Detection in Chemical MechanicalPlanarization
`David Chan, Bogdan Swedek, Andreas Wiswesser, ManushBirang, Applied Materials, Inc.
`
`Factory Automation — WIP Management
`A Layer Based Layout Approach for Semiconductor Fabrication Facilities
`Chao-Fan Chang and Shao-Kung Chang, Industrial Technology Research Institute
`Quantifying Impact ofWIP Delivery on Operator Schedule in Semiconductor Manufacturing Line
`Allen L. Findley, IBM Microelectronics Division
`Better Dispatch Application — A Success Story
`Anke Giegandt and Gary Nicholson, SIEMENS Microelectronics
`Development and Implementation ofan Automated Wafer TransportSystem
`
`Joe Sikich, Hewlett Packard
`
`A Focuson Cycle Timevs. Tool Utilization “Paradox” with Material Handling Methodology
`George W. Horn and William A. Podgurski, Middlesex GeneralIndustries, Inc.
`
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`Advanced Processing - Isolation and Dielectric Issue at 0.181m
`
`A Manufacturable Shallow TrenchIsolation Process for 0.184m and Beyond-Optimization, Stress Reduction
`and Electrical Performance
`
`F. Nouri, O. Laparra, H. Sur, G.C. Tai, D. Pramanik and M. Manley, VLSI Technology, Inc.
`
`Performance and Productivity Improvements in an Advanced Dielectric Etch Reactor for sub 0.3m Applications
`M. Srinivasan, R. Caple, G. Hills, G. Mueller, T. Nguyen, and E. Wagganer, Lam Research Corp.
`
`A Study of Boron Doping Profile Control for a Low Vt Device Used in the Advanced Low Power, High Speed Mixed Signal IC
`Alec Chen, Kyle Flessner and Farris Malone, Peyman Sana, Robert Dixon, Peter Ying and Lou Hutter, Texas Instruments, Inc.
`
`Silicon Nanoelectronics: 100nm Barriers and Potential Solutions
`Vijay Parihar, R. Singh, K.F. Poole, Clemson University
`
`Onthe Integration of Ta,O, as a Gate Dielectric in sub-0.18nm, CMOSProcesses
`T. Devoivre and C. Papadas, ST Microelectronics; M. Setton, LAM Research; N. Sandler, Formerly with LAM Research;
`L. Vallier, CNET Grenoble; |. Bouras, Integrated System Development
`
`Factory Modeling/Simulation
`
`Batch Size Optimization of a Furnace and Pre-Clean Area By Using Dynamic Simulations
`H.J.A. Rulkens, E.J.J. van CampenandJ. van Herk, Philips Semiconductor; J.E. Rooda, Eindhoven University of Technology
`
`Simulation Analysis of 300mm Intrabay Automation Vehicle Capacity Alternatives
`Gerald T. Mackulak, Ph.D., Arizona State University; Frederick P. Lawrence and John Rayter, PRI Automation, Inc.
`
`Managementof Multiple-Pass Constraints
`J. Bonal, A. Sadai, C. Ortega, S. Aparicio, M. Fernandez, R. Oliva, L. Rodriguez, M. Rosendo, A. Sanchez,
`E. Paule and D. Ojeda, Lucent Technologies
`
`MOSAICI Product Transfer Using Virtual Flow Concept
`Ping Wang, Steve Spivey, Edward Warda, Mark Bowser, Bridgette Cosentino, Ed Zabasajja, Piyush Shah, Salma Imam,
`John Keller and Joe Fulton, Motorola, Inc.
`
`Dynamic Dispatch and Graphical Monitoring System
`Neal Pierce and Tanju Yurtsever, Motorola, Inc.
`
`BIOGRAPHIES OF SPEAKERS
`
`SEMIPublications, Standards, Videos, Network
`
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`Page 8 of 18
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`Boston, MA
`
`Page 8 of 18
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`

`

`Developmentof a Production Worthy Copper CMP Process
`Kapila Wijekoon’, Sourabh Mishra’, Stan Tsai*, Kumar Puntambekar*, Madhavi
`Chandrachood’, Fritz Redeker*, Robert Tolles*, Bingxi Sun’, Liang Chen’, Tony Pan‘, Ping
`Li’, Savitha Nanjangud*, Gregory Amico"
`Applied Materials, 3050 Bowers Avenue, Santa Clara, CA 95054
`and
`Joe Hawkins, Theodore Myers, Rod Kistler, Vlasta Brusic, Shumin Wang,Isaac Cherian, Lisa
`Knowles, Colin Schmidt and Chris Baker
`Cabot Corporation, MMD Division, 500 Commons Drive, Aurora, IL 60504
`
`“CMPDivision;
`
`° Metal Deposition Products Division;
`
`° Equipment Set Solution Division
`
`Abstract
`
`A chemical mechanical polishing (CMP)
`process for copper damascene has been developed
`and characterized
`on
`a
`second generation,
`multiple
`platen
`polishing
`tool.
`Several
`formulations of experimental
`copper
`slurries
`containing alumina
`abrasive
`particles were
`evaluated for their selectivity of copper to Ta,
`TaN and PETEOSfilm. The extent of copper
`dishing and oxide erosion of these slurries is
`investigated with various process parameters
`such as slurry flow rate, platen speed and wafer
`pressure. The amount of dishing and erosion is
`found to be
`largely dependent on process
`parameters as well as the slurry composition.
`It
`is shown that the extent of oxide erosion and
`copper dishing can be significantly reduced by
`using a two slurry copper polish process (one
`slurry to polish copper and another to polish
`barrier layers) in conjunction with an optical end-
`point detection system.
`
`Introduction
`
`industry
`semiconductor.
`trend in
`The
`continues to move towards faster miniaturized
`integrated circuits
`for ever
`increasing device
`packing densities.'’ As device architectures are
`scaled down to submicrometer dimensions, RC
`delay of metal interconnects plays an important
`role on the device performance.
`In order to
`increase the switching speed, RC delay of metal
`interconnects must be
`reduced. Aluminum,
`interconnects widely used in present VLSI
`devices,
`raises
`reliability concerns with the
`shrinking device dimensions which rules out the
`possibility of using Al
`in future submicron
`devices. Because of the superior conductivity
`(resistivity of copper
`is about
`1.7 pQ-cm
`compared to 3.0 uQ-cm for aluminum), higher
`resistance to electromigration (electromigration
`limit
`for copper
`is
`10’ A/cm? and that
`for
`aluminum is
`10° A/cm’)
`and
`reduced
`susceptibility to joule heating, copper is being
`
`the
`for
`considered as a potential candidate
`replacement of aluminum in
`future metal
`interconnects. However, patterning copper via
`traditional dry etch techniques is problematic
`mainly due to lack of volatile copper compound
`formationat low temperatures. This difficulty can
`be overcomeby following an alternative approach
`using metal inlay structures such as single and
`dual damascene in conjunction with chemical
`mechanicalpolishing (CMP). **
`the dielectric
`In a Damascene approach,
`is patterned and etched using standard
`layer
`procedures. Barrier and copper films are then
`deposited on the patterned surface. Next,
`the
`copper surface topography is removed by CMP.
`Another challenge
`in
`copper
`technology is
`developing a good deposition technique for
`copper.
`A good barrier
`layer material
`is
`necessary to prevent diffusion of copper
`into
`silicon. The barrier
`layer must be thin to
`minimize the resistance of contact holes, vias and
`metal lines.
`In addition, the barrier layer must
`be able to be planarized with a CMP process.
`Materials such as Ta, TaN, and TiN are the
`most commonly studied barrier layers for copper
`and
`are
`planarized
`using CMP
`process.
`Although many techniques such as sputtering
`(PVD), chemical vapor deposition (CVD) and
`electro-chemical deposition (ECD) are currently
`being considered as film deposition options,
`further refinements of deposition parameters are
`necessary in order to obtain more uniform copper
`films.
`
`Although CMPoffers an attractive solution
`for implementing copper technology in integrated
`circuits, many challenges exist in developing a
`manufacturable copper CMP process. The key
`process issues which must be taken into account
`in developing a production worthy copper CMP
`process
`include
`control
`of
` within-wafer
`uniformity, wafer-to-wafer uniformity,
`copper
`dishing, oxide erosion, corrosion and post CMP
`
`0-7803-4380-8/98/$10.00
`
`1998 IEEE
`
`354
`
`1998 IEEE/SEMI Advanced Semiconductor Manufacturina Conference
`
`Page 9 of 18
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`velocity, down force, slurry flow rate or pad
`hardness.
`
`The wafersused in this study contained test
`structures with different line widths and spacings.
`Copper deposition was carried out with either
`PVD, CVDand/or ECDtechniques. The barrier
`layers were either Ta or TaN.
`In the case of a
`single slurry process the same slurry was used to
`polish copper and barrier layers.
`In the case of
`two-step copper polish process, one slurry was
`used to polish copper and the other slurry was
`used to polish the remaining barrier
`layers.
`Copper polishing was carried out on the first
`platen andthe barrier layer was polished on the
`second platen.
`The buff and rinse step was
`accomplished on thethird platen.
`In both cases,
`multiple polishing steps were used.
`During
`someofthe single slurry processes, one or more
`polishing steps were carried out on the first
`platen and the rest of the steps were carried out
`on the second platen. Again one buff
`andrinse
`step was done on the third platen. All
`the
`erosion
`and
`dishing measurements were
`performed with
`a Tencor HRP200
`high
`resolution profilometer.
`
`Results and Discussion
`The main contribution to copper dishing
`and oxide erosion comes from over-polishing,
`which is often necessary to assure complete
`removalof copper andbarrier residues across the
`entire wafer. The uniformity variations of the
`copper thickness of the as deposited wafers can
`make the CMP step problematic.
`In the ideal
`case, one wouldlike to fully planarize the copper
`layer
`before
`reaching
`the
`barrier
`layers.
`Depending on the slurry chemistry,
`the same
`slurry or a different slurry can be used to polish
`residual copper and the barrier
`layers
`thus
`creating a
`structure with metal
`inlaid
`in
`dielectric. Large differences in chemical reactivity
`of copper and tantalum result
`in dissimilar
`polishing rates of the two layers.
`In the case of
`single slurry processing, the barrier removal rate
`is significantly lower than that of copper. Hence,
`during barrier polishing,
`the exposed copper
`feature dishes due to continued chemical and
`mechanical action. Table I shows the copper
`removalrates andselectivities of copperto barrier
`layers forthe slurries usedin this study.
`
`this
`In view of space limitations,
`cleaning.”'’
`paper focuses only on the characterization of two
`key CMP process issues namely copperdishing
`and oxide erosion. In general, copper dishing is
`defined as the difference in height between the
`lowest point of a single copper line/bond pad
`(usually at the center of the structure) and the
`surrounding oxide film. Oxide erosion is defined
`as the difference in the oxide layer thickness
`within an array ofline structures before and after
`CMP processing (Therefore, the total copper loss
`of a given feature during CMP is the sum of
`erosion and dishing).
`Both copper dishing and oxide erosion can
`generate a significant amount of surface non-
`planarity which cause various process integration
`problems. They reduce the dielectric spacing and
`amount of copper
`in the interconnects,
`thus
`leading to increased interconnect resistance and
`deterioration of device performance. Hence,it is
`vital to develop a CMP process with minimum
`copper dishing and oxide erosion. The extent of
`copper dishing and oxide erosion is found to be
`heavily dependent on CMP consumables(slurry,
`pad), process parameters (wafer pressure, platen
`speed) as well as device features (line width,
`spacing).
`In this paper, we describe the
`reduction of dishing with the use of multiple
`polishing steps and multiple polishing slurries
`in conjunction with an optical end-point system.
`
`Experimental Procedures
`Copper CMP was carried out on Applied
`Materials Mirra® polisher
`using
`Titan™
`polishing
`heads.
`The
`experiments were
`performed by using polyurethane pads
`and
`several experimental copper CMPslurries which
`use alumina abrasive particles. All slurries were
`provided by Cabot Corporation. Hydrogen
`peroxide oxidizer was added to each slurry and
`mixed well prior to polishing.
`Slurry was
`continuously agitated during the experiments.
`Wafer pressure was varied between 1.0 psi and
`6.0 psi, platen speed was varied between 33 rpm
`to 143 rpm and slurry flow rate was varied
`between 75 ml/min and 220 ml/min.
`In every
`case the end-point was detected with the ISRM
`system.
`The Laser based ISRM module is
`embedded in the polishing platen. When the
`laser beam is incident on the film surface during
`polishing,
`the ISRM system probes the film
`surface, collects and processes data, and displays
`areal time signal. This process continues until
`a pre-set end pointis reached. Data are collected
`only whenthe laser beam is incident on the film
`surface,
`therefore,
`the ISRM signal does not
`depend on process parameters such as platen
`
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`Cu:PETEOSselectivity
`
`Cu Removal Rate A/min
`Cu:Ta selectivity
`Cu:TaN selectivity
`
`Table I. Copper removalrate andselectivity to barrier films for various copper CMP slurries at a platen speed of
`43 rpm and a waferpressure of 4.0 psi.
`
`As shown in Table I, either slurry A or B can be
`usedin the single slurry process since they have
`a high copper removal rate. Slurry C is well
`suited for clearing barrier layers since the copper
`removal rate in this slurry is comparable to
`barrier removalrates. An ideal single step slurry
`would polish Cu and the barrier film at similar
`removal rates (low selectivity to barrier) and
`would also have a very low removal rate for the
`field
`oxide
`(high
`selectivity
`to
`SiOz).
`Additionally, such an ideal slurry would remove
`
`residual Cu and barrier without dishing Cu
`interconnects and eroding the dielectric layer.
`The majority of the single slurry process
`discussed in the present work was carried out
`with slurry A. The dependence of the copper
`dishing and oxide
`erosion on the process
`parameters such as slurry flow rate, platen speed
`and wafer pressure was investigated with this
`slurry. In every case, end-point was detected with
`the ISRM system. All wafers were 10% over-
`polished after the end-point was detected. Figure
`1 shows a end-point trace of a blanket copper
`film containing Ta barrier film.
`
`
`
`Time(s)
`
`_8
`
`ReflectanceIntensity(%) 2s8&B
`
`
`
`
`
`8 s
`
`Figure 1.
`
`ISRM trace of a blanket copperfilm containing Ta barrier. End-point is shown by the dotted line.
`
`Page 11 of 18
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`1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference
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`Page 11 of 18
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`

`

`andErosion ®
` BNormalizedDishing
`
`
`Bo
`
`&
`
`50
`
`10
`
`190
`
`150
`130
`»n +O 10
`Slurry Flow (ml/min)
`Figure 2. Dependence of copper dishing and oxide erosion on slurry (slurry A) flow rate. Platen speed and wafer
`pressure wereheld constant. Dishing was measured on a 50mm thickline (pitch 150mm) while erosion was
`measured at a 0.5mm thickline (pitch 1.0mm).
`As
`shown in Figure
`1,
`different
`interfaces of the film stack can be accurately
`detected with the end-point system. The amount
`of over-polish in a single slurry process
`is
`defined as the percent polish time after the end-
`
`a &
`
` BNormalizedDishingandErosion =
`
`point is reached. Figures 2-4 show the extent of
`copper dishing observed in a 50pm copper line
`and extentofoxide erosion observedin a 0.5m
`feature as process parameters such as slurry flow
`rate, waferpressure andplaten speedare varied.
`
`,
`
`2
`
`ey
`
`&
`
`
`
`en 0 = 5
`
`ar - oo
`
`50
`
`oe @ 3 <n
`
`)
`
`9”
`
`7 10
`
`dishing and oxideerosion on platen speed (slurry A). Slurry flow rate and wafer
`3. Dependence ofcopper
`Fi
`ae warekabt chesonishing. was measuredon a 50mm feature (pitch 150mm) while erosion was
`measured at 0.5mm line(pitch1.0mm).
`
`yn
`
`4998 IEEE/SEMI Advanced Semiconductor Manufacturing Conferenéé
`She sake beware forASM ASF
`;
`
`
`/ :Page 12 of 18 fnthcd
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`Shinenesgnitrciachi irolyitietalent tein
`Page 13 of 18
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`1998IEEE/SEMIAdvancedSemiconductorManufacturingConference
`
`andErosion 8 0
`&&&gs
`NormalizedDishing
`
`0
`
`1
`
`2
`
`4
`3
`Wafer Pressure (psi)
`Figure 4. Dependence of copper dishing andoxide erosion on wafer pressure (slurry A). Platen speed and slurry
`flow rate were held constant. Dishing was measured on 50mm feature (pitch 150mm) while erosion was measured
`at 0.5mm line(pitch 1.0mm).
`
`5
`
`6.
`
`7
`
`aehin
`2 show that co
`Datain Fi
`is somewhathigher at high slunyflow rates,
`This may be caused by continued chemical
`etching of copper. Also,
`the copper dishing is
`relatively high at higher platen speeds and higher
`
`wafer pressures. Both the oxide erosion and
`C0PPer dishing appear to linearly increase: with
`platen speed as well as
`the wafer pressure
`(Figures 3 and4).
`
`---A-- SluryB
`—@—Slury A
`
`---8--SlunyB ||
`
`0500
`
`4
`
`—
`
`5°
`
`4
`
`5
`
`%
`
`5
`
`Figure 5. Comparison of copper dishing and oxide erosion of single slurry process under identical experimental
`conditions (slurry A andslurry B). Copper dishing on slurry B is relatively smaller compared to that of slurry A.
`Both slurries have similar oxide erosion performance.
`
`Page 13 of 18
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`

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`
`
`
`
`0 200
`
`£2S62Bowe
`
`
`
`
`
`AmountEtched(Normalized)
`
`100
`Time (s)
`Figure 6. Static copper etch rate at room temperature (slurry A and Slurry B).
`
`»
`
`Ww mw
`
`In order to improvethe dishing in a |
`shown in Figure 6, static copper etch rate of
`that of slurry
`slurry A isconsiderablyhigher
`single slurry process, another slurry formulation
` B. Therefore, slurry B reduces static etching
`(slurry B) was evaluated. Figure 5 comparesthe
`during the barrier removal and over-polish,
`extent of dishing and erosion observed with
`~
`leadingto lower copper dishinglevels. Because
`single slurry processes (slurry Aand slurry B)
`oftheimproved dishing performance ofslurry B
`under identical polishing conditions. It is seen —
`(comparedto slurry A), slurry B was selected as
`that dishing anderosion performance ofslurry B
`the first step slurry for the two-slurry process
`is somewhat improved as compared to slurry A._«es
`Improved dishinginslurry Bmaybe relatedto a
`low static etchrate ofslurryB (Figure6). As.
`
`ts
`
`
`
`EP+ti
`
`EP +t2
`
`EP + t3
`
`Polish Time(s)
`
`Figure 7. Comparison ofcopper dishing of 100 mm bond pad for oneslurry (slurry A) process and two slurry
`EP is the time to reach end-point andtl, t2, 3
`In the case of one slurry process,
`12,and t3 are the over polish times with slurry
`(slurry B and slurry C) processes.
`In the case of the two slurry process, tl,
`are the over polish times.
`G
`
`2
`ine
`
`ebm
`
`Osiante ek ines
`
`A fare
`
`FS Ee
`
`4998 IEEEISEMIAdvancedSemiconductorManufacturingConference
`
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`
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`
`age14 of 18
`
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`DA
`CT
`ED
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`Page 14 of 18
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`

`

`
`
`
`
`-20
`
`0
`
`in Figure 7, although the extent of dishing
`In the two slurry polish process, copper
`increases as a function of the amount of over
`was polished to the barrier layer with slurry B
`polish for both processes, the two slurry process
`followed by removal of the barrier layer with
`considerably reduces
`the
`amount of copper
`slurry C.
`It is very important to removeall the
`dishing. In the case of the single slurry process,
`copperwith slurry B before using slurry C since
`the extent of dishing significantly increases with
`slurry C has a very low copper removalrate.
`the amountof over-polish.
`Figure 7 compares the copper dishing observed
`in a 100um copperline with one slurry process
`uniformity
`Because of
`the
`significant
`as well as the two slurry process. Slurry A was
`variation of the incoming wafers, in some copper
`used only in the oneslurry process to clear the
`wafers, copper dishing was observed even at a
`film stack all the way down to the oxide layer.
`20% under-polish (Figure 8).|As shown in
`In the case of the two slurry process approach,
`Figure 8 the amount of copper dishing linearly
`slurry B was used to polish copper. With the
`increases with the
`extent of over polish.
`use of ISRM, polishing was
`stopped when
`Therefore, unnecessary over-polishing should be
`copper was cleared to the Ta layer. Slurry C was
`avoided and could be greatly reduced by using a
`used to polish the Ta layer and for evaluation of
`reliable end-point detection system.
`overpolish effects after reaching oxide. As shown
`
`05
`
`i
`
`&NormalizedDishing 5
`
`Figure 8. Effect of over polish on the extent of dishing
`were buffed with oxide slurry.
`
`in 100 m bondpads (slurry A). After polishing the wafers
`
`(%) Over Polish
`
`Furthermore, it was found that manyofthe
`irregularities observedin the single slurry
`process could besignificantly reduced with the
`twoslurry process. Figures 9 and 10 show the
`dependence ofcopper dishing and oxide erosion
`on various copperfeatures for one slurry process
`
`as well as for two slurry process. As shown in
`these figuresit is very clear that two slurry
`processresults in significantly improved copper
`dishing and oxide erosion performances. Figure
`11 comparesthetotal copperloss in various
`copperlines for single and twoslurry processes.
`
`Page 15 of 18
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`1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conferenc:
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`

`SsluryA
`slurry B+C =
`
`Loss
`NormalizedTotalCopper
`
`
`0.5p
`
`4u
`
`on
`
`25
`
`35u
`
`75
`
`Line Width
`
`Figure 11. Comparison of total copper loss (dishing + erosion) for one slurry (slurry A) and twoslurry(slurry B
`+ slurry C) processes in a variety of copperline sizes.
`
`the two slurry process
`As seen in Figure 11,
`significantly reduces the amount of total copper
`loss
`(dishing + erosion)
`in
`copper
`lines
`comparedto the single slurry process. The data
`presented in Figure 11 were derived from the
`
`resolution
`measurements made with a high
`profilometer. These data are in good agreement
`with the electrically measured copper thickness
`for single and two slurry processes (Figure 12)
`measured with a short loop test pattern.
`
` » 0.800
`
`%3B
`
`vaa
`
`aan
`
`0.400
`
`.
`
`°O
`
`o z
`
`Z 0.200
`
`0.000
`
`Slurry B + C, End-
`Slurry A, End-
`Slurry A, 20%
`pointed
`pointed
`overpolish
`Figure 12. Comparison of electrically measured copper thickness for one slurry (slurry A) and twoslurry (slurry
`B + slurry C) processes. Measurements were performed on a 10 m x10m Van der Pauwstructure.
`
`The data displayed in Figure 12 were measured
`on 10ux10p Van der Pauw structures.
`As
`expected,
`the wafers processed with slurry A
`show heavy copperlossin theline structures.
`It
`can be seen that about 40% ofadditional copper
`is lost by performing 20% over-polish after end-
`point detection. However,
`in the case of two
`slurry process, only 10% copper is
`lost when
`polishing was stopped at end-point.
`
`Page 17 of 18
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