US005858873A
`5,858,873
`(11) Patent Number:
`United States Patent 15
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`Vitkavageetal.
`[45] Date of Patent:
`Jan, 12, 1999
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`[54]
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`INTEGRATED CIRCUIT HAVING
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`AMORPHOUS SILICIDE LAYER IN
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`CONTACTS AND VIAS AND METHOD OF
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`MANUFACTURE THEREOF
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`Inventors: Susan C. Vitkavage; Daniel J.
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`Vitkavage, Sailesh M. Merchant,all
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`of Orlando, Fla.
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`73) Assi
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`t Technologies
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`signee NL Seimotognes
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`Inc., M
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`int., Murry
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`[21] Appl. No.: 816,185
`wg.
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`Mar. 12, 1997
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`Filed:
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`[51] Unt, C18ceceeeecceceeereneneee HOIL 21/4763
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`[52] US. Cd ec eeeceeeseeeereeeeeereeeseee 438/626; 438/628
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`[58] Field of Search 00.0eee 438/626-631
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`[56]
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`5,420,074
`5/1995 Ohshima oo...ee 438/630
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`5,451,545
`9/1995 Ramawamietal.
`. 437/200
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`ee tito08 arshnan ‘ al.
`onto
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`:
`‘thien et al.
`504,
`96
`/1¢
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`5,514,908
`5/1996 Liao et al.
`..
`. 257/751
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`een tose Hibino et al.
`» 438/626
`5,585,
`. 438/629
`/1996 Sardella.
`......
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`5,591,671
`1/1997 Kim el ale cecccsssecensenseseeee 438/630
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`~"
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`OTITER PUBLICATIONS
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`us
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`Wolf, Stanley “Silicon Processing for the VLSI Era vol. 1:
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`Process Technology”, Lattice Press, pp. 331-335,384-392,
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`1986.
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`Primary Examiner—ohn |’. Niebling
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`Assistant Examiner—Michael S. Lebentritt
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`ABSTRACT
`[57]
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`An integrated circuit, a contact and a method of manufacture
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`therefor. The integrated circuit has a silicon substrate with a
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`References Cited
`recess formed therein that provides an environment within
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`an
`which the contact is formed. The contact includes: (1) an
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`US. PATENT DOCUMENTS
`adhesion layer deposited on an inner surface of the recess,
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`1/1989 Kakumuet al.ccc 438/626
`4,800,176
`(2) an amorphouslayer, deposited over the adhesion layer
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`9/1990 Iderem et al.
`cscs 437/55
`4,957,777
`within the recess and (3) a central plug, composed of a
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`4,960,732 10/1990 Dixit et al.
`conductive material, deposited al least partially within the
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`-. 438/629
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`4,962,414 10/1990 Liou et al
`+ 438/625
`recess, the silicide layer being amorphous to prevent the
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`oga vit909 pe ows
`” tee conductive material from passing through the amorphous
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`ennng
`re
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`9,
`LU60,
`aes
`a
`Da
`os
`Vries
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`7/1994 Kinoshita et al...
`438/629
`5,332,601
`silicide layerto contact the adhesion layer thereby to prevent
`.....
`12/1994 Liou et al.
`JUneton Keakage.
`. 437/192
`5,371,041
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`» 438/627
`1/1995 Yu etal.
`5,380,678
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`3/1995 Kim
`5,397,742
`438/630
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`7 Claims, 2 Drawing Sheets
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`Page 1 of 6
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`TSMCExhibit 1008
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`TSMC Exhibit 1008
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`Page 1 of 6
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`U.S. Patent
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`Jan. 12, 1999
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`Sheet 1 of 2
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`5,858,873
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`FIG.
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`U.S. Patent
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`Jan. 12, 1999
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`Sheet 2 of 2
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`5,858,873
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`FIG. 8
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`[ALLLLLLLLELLLPTLS
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`PSOEEESAAS
`ELLLEELLEELEe
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`ERLELEE (LLLLLLLLLLLLLLDN
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`PNAAASSASS
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`ILLoLILLE
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`5,858,873
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`1
`INTEGRATED CIRCUIT HAVING
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`AMORPHOUSSILICIDE LAYER IN
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`CONTACTS AND VIAS AND METHOD OF
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`MANUFACTURE THEREOF
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`TECHNICAL FIELD OF THE INVENTION
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`The present invention is directed, in general, to semicon-
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`ductor devices and, more specifically, to an integrated circuit
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`having an amorphoussilicide layer in contacts or vias
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`thereof and a method of manufacture for the integrated
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`BACKGROUND OF THE INVENTION
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`The extensive use of semiconductors, such as integrated
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`circuit (“IC”) devices, in a wide range of electronic appli-
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`cations is well known. A typical semiconductor device is
`comprised of a series of contact openings (“windows”)
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`formedin a substrate material, such as silicon that has doped
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`source and drain regions. The interconnection of these
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`windowsprovides a circuit for the conduction of electrical
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`current through the device. The windows have a metallic
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`“plug” deposited therein, which is tungsten in most appli-
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`cations. The plug is overlaid with a conductive metal trace,
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`such as aluminum-alloy, which includes,
`for example,
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`aluminum-copper, aluminum-silicon or aluminum-copper-
`silicon. The conductive metal
`trace is laid down in a
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`predeterminedpattern that electrically connects the various
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`windowsto achieve the desired electrical circuit configura-
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`Typically, the windows have a barrier layer of titantum
`overlaid with titanium nitride formed over the surface of the
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`interior sides of the window to serve as an adhesion/
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`nucleation layer for tungsten. Various problems, however,
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`have arisen with respect to the metals used to form the plugs
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`and trace patterns between these windows. For example, the
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`titanium and titanium nitride layers are typically deposited
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`by physical vapor deposition (“PVD”), whereas the tungsten
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`is deposited by chemical vapor deposition (“CVD”). These
`different deposition methods use very different
`tools to
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`achieve the deposition. Thus, the semiconductor device is
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`placed in a PVD tool for the formation of the titantum and
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`titanium nitride layers, removed and placed in a CVD tool
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`to form the tungsten plug, and then returned to the PVD tool
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`for the deposition of the aluminum-alloy interconnect. These
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`transfers not only require time, it also subjects the device to
`oxidation and contaminants, which in turn, can affect the
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`quality of the device. Moreover, because tungsten does not
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`have a sufficiently high enough electrical conductivity, the
`excess tungsten that
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`semiconductor device must be etched-back or polished-back
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`prior to its return to the PVD tool, which involves yet
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`another step in the manufacturing process. These inefficien-
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`cies increase the overall manufacturing time and cost of the
`semiconductor device.
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`In view of these disadvantages, it has becomedesirable to
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`use aluminum-alloys for the metal plug. Unfortunately,
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`however, aluminum-alloy also has problemsassociated with
`its use. It is well known that mutual diffusion of aluminum-
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`alloy andsilicon occurs betweenthesilicon substrate and the
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`aluminum-alloy plug when the semiconductor device is
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`subjected to the high temperatures necessary for semicon-
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`ductor manufacturing. The aluminum-alloy can diffuse into
`the silicon substrate to such a depth to cause a short within
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`the semiconductor device. This phenomenon is known as
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`junction leakage. The aluminum-alloy is able to diffuse into
`the silicon substrate because conventional processes pro-
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`duce barrier layers that have crystalline structures with grain
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`boundaries. As such,
`the aluminum-alloy is capable of
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`diffusing through these grain boundaries and into the silicon
`substrate.
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`Attempts have been made to address the problem of the
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`diffusion problem associated with such crystalline struc-
`tures. Two such attempts are disclosed in U.S. Pat. No.
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`4,976,839 and U.S. Pat. No. 5,514,908. Both of these patents
`are directed to processes that are designed to circumvent the
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`problems associated with such crystalline structures and
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`resulting grain boundaries existing within the barrier layers.
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`However,
`they too fall short in providing a satisfactory
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`solution in that they may form grain boundaries that might
`not be adequately stuffed with oxygen as a result of the
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`complex manufacturing processes to achieve a layer bound-
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`ary through which aluminum-alloy will not diffuse.
`Therefore, what is need in the art is a semiconductor and
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`a simple process for manufacturing thereof that avoids the
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`problemsassociated with crystalline barrier layers that allow
`diffusion of the aluminum into the silicon. The semiconduc-
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`tor and the manufacturing process of the present invention
`address these needs.
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`SUMMARYOF THE INVENTION
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`The present invention provides an integrated circuit and a
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`contact that resist junction leakage, and a method of manu-
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`facture therefor. The integrated circuit has a silicon substrate
`with a recess formed therein that provides an environment
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`within which the contact is formed. The contact includes: (1)
`an adhesion layer deposited on an inner surface of the recess,
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`(2) an amorphous layer deposited over the adhesion layer
`within the recess and (3) a central plug, composed of a
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`conductive material, deposited at least partially within the
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`recess. The non-crystalline amorphous layer substantially
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`prevents the conductive material from passing through the
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`amorphous layer to contact the adhesion layer thereby to
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`prevent junction leakage.
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`In a preferred embodiment of the present invention, the
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`adhesion layer is composedoftitanium and titanium nitride
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`and the central plug is comprised of aluminum-alloy. The
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`titanium forms the first
`layer that
`is deposited over the
`silicon substrate.
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`In another aspect of the present invention, the adhesion
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`layer, the central plug and the amorphouslayer are deposited
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`by DO physical vapor deposition.
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`The amorphous layer is preferably a silicide layer that
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`includes an element selected from the group consisting of
`zirconium, molybdenum,
`tantalum or cobalt, and more
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`preferably, the amorphous layer is comprised of tungsten
`silicide.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`For a more complete understanding of the present
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`invention, and the advantages thereof, reference is now
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`made to the following descriptions taken in conjunction with
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`the accompanying drawings, in which:
`FIG. 1 illustrates a cross-sectional view of an exemplary,
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`partially manufactured integrated circuit prior to deposition
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`of any barrier layers;
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`FIG. 2 illustrates a cross-sectional view of the exemplary
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`integrated circuit device of FIG. 1 with the adhesion layer
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`deposited thereon and within the window;
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`FIG. 3 illustrates a cross-sectional view of the exemplary
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`integrated circuit device of FIG. 2 with the amorphouslayer
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`deposited over the adhesion layer and the titanium nitride
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`barrier is layer; and
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`5,858,873
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`FIGS. 4 illustrates a cross-sectional view of the exem-
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`plary integrated circuit device of FIG. 3 with the metallic
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`plug deposited within the window and after etch-back/or
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`planarization formation of the plug.
`DETAILED DESCRIPTION
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`Referring initially to FIG. 1, there is illustrated a cross-
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`section portion of an integrated circuit that has beenpartially
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`fabricated. At this stage of manufacture, the device’s struc-
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`ture is entirely conventional and includesa silicon substrate
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`2 that has a doped diffusion region 4 formed therein, which
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`is of opposite conductivity type from that of substrate 2. For
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`example, substrate 2 may be a lightly doped p-type silicon
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`and diffusion region 4 may be heavily doped n-type silicon.
`Of course, as noted above, other structures knownto those
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`skilled in the art may be used. For instance, the substrate 2,
`instead, may be a well or tub region in a CMOSprocess.
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`Diffusion region 4 is bounded bya field oxide structure 6,
`which is also formed in a conventional manner. In this
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`particular embodiment, diffusion 4 is very shallow, such as
`on the order of 0.15 microns, which is a conventional
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`thickness for modern integrated circuits having sub-micron
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`feature sizes. Thus, diffusion region 4 may be formed by ion
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`implantation of the dopant followed by a high-temperature
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`anneal to form the junctions, as is well known in theart.
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`Alternatively, the ion implantation may be performed prior
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`to the formation of subsequent layers, with the drive-in
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`anneal performed later in the process, if desired.
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`A dielectric layer 8, which may be a deposited oxide or
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`another type of dielectric layer, is formed over the diffusion
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`region 4 andfield oxide 6. The dielectric layer 8 electrically
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`isolates overlying conductive structures from the diffusion
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`region 4, except at locations where contacts therebetween
`are desired. A contact opening 10, which may be a window
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`or via, has been formed through the dielectric layer 8 in a
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`conventional manner, such as by wayofreactive ion etching
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`or another type of known anisotropic etching. Contact
`opening 10 may be as small as less than one micron in width,
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`as is typical for modern sub-micron integrated circuits.
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`Preferably, the contact opening 10 has a width that ranges
`from about 0.3 to about 0.8 microns and an aspect ratio that
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`ranges from about 1.0 to about 3.0. As previously stated,
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`each of the structures illustrated in FIG. 1 may be formed
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`according to conventional processes knownto those of skill
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`in the art of the integrated circuit manufacture, including
`thicknesses of the various structures and methods of forma-
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`tion.
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`Turning now to FIG. 2, after completion of the structure
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`illustrated in FIG. 1, a thin adhesive, but conductive, layer
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`12 is deposited over the inner surface of the contact opening
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`10 and the top portion of the substrate 2. The adhesion layer
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`12 is preferably deposited by sputtering or PVD techniques
`and at pressures and temperatures that are well knownin the
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`art. The thickness of the adhesion layer 12 may range from
`about 10.0 nm to about 100.0 nm.
`In a preferred
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`embodiment, however, the thickness of the adhesion layer
`12 is about 30.0 nm. It will, of course, be appreciated that the
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`thickness of the adhesion layer 12 is selected according to
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`the thickness of the amorphouslayer that is to be formed at
`the contact location, and as such, the thickness may vary,
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`depending on the application. In a preferred embodiment,
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`the adhesion layer 12 is titantum, but other conductive
`metals knownto those skilled in the art may also be used in
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`place of titantum, such as tantalum, zirconium, hafnium,
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`tungsten, or molybdenum. Moreover, the adhesion layer 12
`may also include various stack schemes, such as titanium/
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`titanium nitride/titanium,etc.
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`Page 5 of 6
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`4
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`Turing now to FIG. 3, a layer 14 comprised of a
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`refractory material is deposited over the adhesion layer 12 in
`a conventional manner to a preferred thickness of about
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`100.0 nm. Examples of the refractory material that can be
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`used in the present invention are titantum nitride, titanium
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`carbide, titanium boride, tantalum nitride, tantalum carbide,
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`tantalum boride, zirconium nitride, zirconium carbide, zir-
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`conium boride, hafnium nitride, hafnium carbide, hafnium
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`boride, tungsten nitride, tungsten carbide tungsten boride,
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`molybdenum nitride, molybdenum carbide and molybde-
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`num. Preferably, however, the refractory material is titantum
`nitride. A conventional PVD method at conventional tem-
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`peratures that range from about 25° C. to about 400° C. and
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`pressures that range from about 1 milliTorr to about 10
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`milliTorr are used to deposit the titantum nitride layer 14 in
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`a preferred embodiment. PVD deposition techniques are
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`preferred because the semiconductor device does not have to
`be transferred to a different tool, which decreases manufac-
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`turing time and eliminates particle defects and contamina-
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`tion problems associated with moving the device from one
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`deposition tool to another. As discussed in the art, the PVD
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`deposition of titantum nitride apparently forms a layer 14
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`having a crystalline structure with grain boundaries. As
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`such, this layer 14 does not serve as a good boundary layer
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`to prevent diffusion of aluminum-alloy into silicon.
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`Accordingly, the present invention provides an amorphous,
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`non-crystalline layer that is deposited over the layer 14.
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`Continuing to refer to FIG. 3, an amorphouslayer 16, in
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`accordance with the present invention, is shown deposited
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`over the titantum nitride layer 14. The amorphouslayer 16
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`is preferably deposited by conventional PVD techniquesat
`a temperature that ranges from about 25° C. to about 400°
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`C. and at pressures that range from about 1 milliTorr to about
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`20 milliTorr. More preferably, however, the deposition tem-
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`perature is about 400° C. and the deposition pressure is
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`about 2 milliTorr. The PVD tool used to deposit the amor-
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`phous layer 16 is a conventional PVD tool, well known to
`those skilled in the art and is the same tool used to deposit
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`the previously-discussed adhesive and titanium nitride lay-
`ers.
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`Experimental results indicate that the amorphouslayer 16
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`is non-crystalline, and thus, does not have the grain bound-
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`aries associated with crystalline structures found in the prior
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`art. Thus, the amorphous layer 16 provides a continuous
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`layer through which a metal plug, such as aluminum-alloy
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`cannot diffuse. Moreover, the amorphous layer 16 can be
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`deposited using the same PVD methods used to deposit the
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`adhesion layer 12 and the titanium nitride layer 14. As such,
`the semiconductor device does not haveto be transferred to
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`another deposition tool, such as a CVDtool,as is typically
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`done in conventional processes. In most applications in the
`art, the semiconductor device is removed from the PVD tool
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`following deposition of the titanium nitride layer and trans-
`ferred to a CVD tool wherea tungsten plug is deposited over
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`the titanium nitride layer. As previously discussed, because
`the vacuum on the tool must be brokento transfer the device,
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`this subjects the semiconductor device to possible defects
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`and contamination from the environment during the transfer
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`from one tool to another. Further, manufacturing time, and
`thus, the cost of the device increase with these transfers.
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`Because the amorphouslayer 16 can be deposited with PVD
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`techniques, the problemsofthe prior art are avoided; thatis,
`the vacuum on the tool can be maintained, which greatly
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`reduces the risks of oxidation and environmental contami-
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`nation.
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`In a preferred embodiment, the amorphouslayer 16 is a
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`metal-silicide layer. The silicon is bonded with a metal
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`Page 5 of 6
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`

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`5,858,873
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`5
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`wherein the metal may be, for example, titanium, tungsten,
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`zirconium, molybdenum,
`tantalum or cobalt. More
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`preferably, however, the metal silicide layer is a tungsten
`silicide (WSi,) wherein the value for x ranges between about
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`2 and about 2.5. In a moreis preferred embodiment,the ratio
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`of silicon to tungsten in the molecular structure is about
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`1:2.5. While different methods of deposition can be used to
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`deposit the tungsten silicide over the titanium layer 14,it is
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`preferred that PVD methods are used. The deposition is
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`conducted until a silicide layer having the desired thickness
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`is formed. Preferably, the thickness may range from about
`30.0 nm to about 100.0 nm, and more preferably,
`the
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`thickness of the amorphous layer 16 is about 50.0 nm. The
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`PVD deposition method of the amorphoussilicide provides
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`an excellent amorphous boundarylayer that prevents diffu-
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`sion of the plug metal into the substrate 2. Additionally, it
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`acts as a wetting layer for the in situ formation of the metal
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`plug, which aids the metal’s deposition in the very small
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`opening 10, as opposed to prior art titantum wetting layers
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`for in situ aluminum plug formation.
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`Turning now to FIG. 4, there is illustrated the semicon-
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`ductor device of the present invention in which a metal plug
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`18 has been deposited in the layered contact opening 10. As
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`with the other previously deposited layers, the preferred
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`method of deposition is with a PVD tool. Again, this allows
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`the critical steps of the semiconductor fabrication to take
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`place in a single deposition tool. The metal plug 18 may be
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`comprised of various types of conductive metals, including
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`alloys that are effective conductors of electrical current. For
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`instance, the metal plug 18 maybe of an aluminum-alloy or
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`copper. More preferably, however, the metal plug is com-
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`prised of aluminum-alloys.
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`An aluminum-alloy plug has several advantages over the
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`tungsten plugs of the prior art. For example, after the
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`tungsten’s deposition, the excess tungsten is removed with
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`an etch-back step, followed by a deposition of aluminum
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`interconnect and an etch-back of the aluminum-alloy. When
`a tungsten plug is used in a semiconductor device, the excess
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`deposition of tungsten on the surface of the substrate must
`be etched-back so that an aluminum-alloy trace can be
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`deposited over the tungsten plug. After the tungsten’s etch-
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`back, aluminum-alloy is then deposited and the desired trace
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`pattern in formed by yet another etch-back process. The
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`reason that an aluminum plugis used in place of the already
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`present tungsten is that tungsten has a higherresistivity than
`aluminum-alloy, and thus, is not as good a conductor as
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`aluminum-alloy. Another advantageis that when aluminum-
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`alloy is used for the plug in place of tungsten, the aluminum-
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`alloy plug and the trace pattern can easily be formed in one
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`sequence by conventional etch-back processes.
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`From the above, it is apparent that the present invention
`provides a semiconductor device that has a silicon substrate
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`with a recess formed therein that provides an environment
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`within which the contact is formed. The contact includes: (1)
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`an adhesion layer deposited on an inner surface of the recess,
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`(2) an amorphous layer deposited over the adhesion layer
`within the recess and (3) a central plug, composed of a
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`conductive material, deposited at least partially within the
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`recess, the silicide layer being amorphous to prevent the
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`conductive material from passing through the amorphous
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`silicide layer to contact the adhesion layer thereby to prevent
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`junction leakage. The adhesionlayeris preferably composed
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`of titanium andthe central plug is comprised of aluminum-
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`alloy. Moreover,it is preferred that the adhesion layer, the
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`central plug and the amorphous layer are deposited by
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`physical vapor deposition.
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`10
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`6
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`The amorphous layer is preferably a silicide layer that
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`includes an element selected from the group consisting of
`zirconium, molybdenum,
`tantalum or cobalt, and more
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`preferably, the amorphous layer is comprised of tungsten
`silicide.
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`The method of manufacturing of the present invention
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`also provides distinct advantages overthe art. In the present
`method, the semiconductor device is left in the PVD tool
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`during all steps of layer deposition. The titanium layer, the
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`titanium nitride layer, the amorphous layer and the metal
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`plug are all deposited using PVD methods. As previously
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`explained, this decreases manufacturing time and the costs
`associated therewith because the device does not have to be
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`transferred from one deposition tool to another. Further, it
`decreases the risks of contamination of the device.
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`The foregoing has outlined rather broadly the features and
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`technical advantages of the present invention so that those
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`skilled in the art may better understand the detailed descrip-
`tion of the invention that follows. Additional features and
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`advantages of the invention will be described hereinafter
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`that form the subject of the claims of the invention. Those
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`skilled in the art should appreciate that they may readily use
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`the conception and the specific embodiment disclosed as a
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`basis for modifying or designing other structures for carry-
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`ing out the same purposes of the present invention. Those
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`skilled in the art should also realize that such equivalent
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`constructions do not depart from the spirit and scope of the
`invention in its broadest form.
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`Whatis claimedis:
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`1. A method of manufacturing a contact in an integrated
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`circuit, said integrated circuit having a silicon substrate with
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`a recess formed therein, said method comprising the steps
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`first depositing an adhesion layer on an inner surface of
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`said recess;
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`next depositing an amorphous layer over said adhesion
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`layer within said recess; and
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`subsequently depositing a central plug composed of a
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`conductive material at least partially within said recess,
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`said amorphous layer inhibiting a metal said central
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`plug from diffusing into said silicon substrate.
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`2. The method as recited in claim 1 wherein said step of
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`depositing said adhesion layer comprises the step of depos-
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`iting a layer of titanium.
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`3. The method as recited in claim 1 wherein said step of
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`first depositing comprises the step of first depositing said
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`adhesion layer by physical vapor deposition and said step of
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`subsequently depositing comprises the step of depositing
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`said central plug by physical vapor deposition.
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`4. The methodas recited in claim 1 wherein said step of
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`depositing said amorphous layer comprises the step of
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`depositing a tungsten silicide layer.
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`5. The method as recited in claim 1 wherein said step of
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`depositing said amorphous layer comprises the step of
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`depositing an amorphoussilicide layer including an element
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`selected from the group consisting of zirconium,
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`molybdenum, tantalum or cobalt.
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`6. The method as recited in claim 1 wherein said step of
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`next depositing comprises the step of next depositing said
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`amorphouslayer by physical vapor deposition.
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`7. The method as recited in claim 1 wherein said step of
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`depositing said central plug comprises the step of depositing
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`an aluminum-alloy plug.
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`*
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`*
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`Page 6 of 6
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