United States Patent
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`
`Hong et al.
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`119]
`
`[54] DIFFUSION BARRIER TRILAYER FOR
`
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`MINIMIZING REACTION BETWEEN
`METALLIZATION LAYERS OF
`INTEGRATED CIRCUITS
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`Inventors: Qi-Zhong Hung, Dallas; Shin-Puu
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`Jeng, Plano; Robert H. Havemann.
`Garland. all of Tex.
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`Assignee: Texas Instruments Incorporated,
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`Dallas, Tex.
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`Appl. No.: 685,159
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`
`
`Filed:
`Jul. 23, 1996
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`Related U.S. Application Data
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`
`
`Continuation of Ser. No. 474,286, Jun. 7, 1995, abandoned,
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`
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`
`
`which is a division of Ser. No. 412,473, Mar. 23, 1995,
`abandoned.
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`Int. Cl.5 ............................. H01L 21/44; H01L 29/43
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`U.S. Cl. ........................... 257/751; 257/915; 438/653
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`Field of Search ..................................... 257/751, 915;
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`437/190, 195
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`.
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`.
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`References Cited
`
`
`
`U.S. PATENT DOCUMENTS
`
`
`
`4/1991
`Huang et al.
`
`
`
`3/1992
`Kumar et al.
`6/1992
`
`
`
`
`
`
`4/1993
`Fujii et al.
`
`
`
`Bost et al.
`7/1993
`
`
`
`Hindman et al.
`8/1993
`
`
`Nulman et a1.
`9/1993
`
`
`
`Chen et al.
`12/1993
`
`
`
`1/1994
`
`
`
`5/1994
`Yokoyama et al.
`
`
`
`5/1994
`........
`Fujii et al.
`.
`Ishii et al.
`5/1994
`
`
`
`
`Kikkawa
`9/1994
`5/1995
`Fiordalice et al.
`
`
`7/1995
`Nulman et al.
`
`
`
`9/1995
`6/1996
`
`
`
`Merchant ct a1.
`
`
`
`
`...................
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`
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`
`
`
`
`437/190
`
`
`5,008,216
`
`5,093,710
`
`5,118,385
`
`5,202,579
`
`5,231,053
`
`5,240,880
`
`5,242,860
`
`5,270,254
`
`5,275,973
`
`5,312,772
`
`
`5,312,775
`
`5,313,100
`5,345,108
`5,420,072
`
`5,434,044
`
`5,449,641
`
`5,523,259
`
`
`USO05668411A
`
`[11]
`
`
`
`Patent Number:
`
`
`[45] Date of Patent:
`
`
`
`
`
`
`5,668,411
`
`
`
`
`Sep. 16, 1997
`
`
`
`
`
`
`0 525 637 A1
`
`
`
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`
`.
`2/1993 European Pat. Ofl’.
`
`
`
`
`OTHER PUBLICATIONS
`
`
`Kaizuka T. et al. “AL(1l1)/CVD-TiN(111) Stacked Film
`
`
`
`
`
`
`
`
`
`
`Formation Technique with High Aspect-Ratio Contact Hole
`Filling for Highly Reliable Interconnects”, International
`
`
`
`
`
`Conference on Solid State Devices and Materials, Aug. 29,
`
`
`
`
`
`
`
`1993, pp. 555-557.
`
`
`
`I-Iideki Shibata, et al. “The Effects of AL(111) Crystal
`
`
`
`
`
`
`
`
`
`Orientation on Electromigration in Half-Micron Layered
`
`
`
`
`
`AL Interconnects”, Japanese Journal of Applied Physics,
`
`
`
`
`
`
`
`Oct. 1, 1993, vol. 32, No. 10, Part 1, pp. 4479-4484.
`
`
`
`
`
`
`
`
`
`B. Lee, E.C. Douglas, K. Pourrezaei, and N. Kumar, “Effect
`
`
`
`
`
`
`
`
`of Oxygen on the Diffusion Barrier Properties of T'
`”, VLSI
`
`
`
`
`
`
`
`
`MLLlt1'level Interconnect Conference (VMIC) Proceedings,
`
`
`
`
`
`pp. 344-350, (1987).
`
`
`
`M. Inoue, K. Hashizume, K. Watanabe, and H. Ysuchikawa.
`
`
`
`
`
`
`“The Properties of Reactive Sputtered TiN Films For VLSI
`
`
`
`
`
`
`
`
`Metallization”, VMIC Proceedings, pp. 205-211. (1988).
`
`
`
`
`
`
`H. P. Kattelus, J. Tandon, C. Sala, and M. -A. Nicolet,
`
`
`
`
`
`
`“Bias-induced Stress Transisitions in Sputtered TiN Films”,
`
`
`
`
`
`
`
`
`
`
`
`
`J. Vac. Sci. Technol. A 4, pp. 1850-1854, (1986).
`H. Joswig and W. Palmer, “Improved Performance of
`
`
`
`
`
`
`TiN-Diffusion Barriers After a Post-Treatment”, VNIIC
`
`
`
`
`
`Proceedings, p. 477, (1990).
`
`
`
`W. Sinke, G. Frinjlink, and F. Saris, “Oxygen in Titanium
`
`
`
`
`
`
`
`Nitride Diflusion Barriers”, Appl. Phys. Lett. 47, pp.
`
`
`
`
`
`
`
`
`
`
`471-473, (1985).
`T. Kikkawa, H. Aoki, J. Drynan, “A Quarter-Micrometer
`
`
`
`
`
`Interconnection Technology Using a TiN/Al$i—Cu/'I'iN/
`
`
`
`
`Al—Si—Cu/I'iN/Ti Multilayer Structure”, IEEE Transactions
`
`
`
`
`
`on Electron Devices, vol. 40, No.2, Feb. 1993, pp. 296-302.
`
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`
`
`
`
`
`
`
`
`Primary Examiner—Tom Thomas
`
`
`Assistant Examiner—David B. Hardy
`
`
`Attome); Agent, or Firm—Kay Houston; W. James Brady,
`
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`
`
`111; Richard L. Donaldson
`
`
`ABSTRACT
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`
`[57]
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`A diifusion barrier trilayer 42 is comprised of a bottom layer
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`44, a seed layer 46 and a top layer 48. The diffusion barrier
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`trilayer 42 prevents reaction of rnetallization layer 26 with
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`the top layer 48 upon heat treatment, resulting in improved
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`sheet resistance and device speed.
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`15 Claims, 3 Drawing Sheets
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`20K
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`II
`IIZ
`\\\
`\\
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`§\\\;\\\\\
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`\ I
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`TSMC Exhibit 1009
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`Page 1 of 9
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`U.S. Patent
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`Sep. 16, 1997
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`Sheet 1 of 3
`%
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`5,668,411
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`FIG.
`7
`(PRIOR ART)
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` J'II..ZA
`22
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`FIG. 2
`(PRIOR ART)
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` &\
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`28 .m
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`2_2
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`1.0
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`1.2
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`Energy (Mev)
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`1.4
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`1.5
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`3.8
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`15
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`-—-SiO2/TiN/Al—Cu. As—deposited
`1 cycle at 45D“C
`SE02/TEN/AI-Cu,
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`10
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`Normalized
`Yield
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`(PRIOR ART)
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`FIG. 3
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`5
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`Page 2 of 9
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`Page 2 of 9
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`U.S. Patent
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`Sep. 15, 1997
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`Sheet 2 of 3
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`5,668,411
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`(PRIOR ART)
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`34 a=..-.‘.‘.‘-2:3,: ‘V-n‘““
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`.x\\‘4.‘:J
`5?»
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`32
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`2°“ k\\\\\\\\Vm \
`28
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` .(II'.IIAu'
`I
`34 iiifij w \‘PCT.QCQCV
`
`FIG. 5
`
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`.3
`ir.
`.\\N‘...:,~ I In
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`(PRIOR ART)
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`2.2
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`(PR1OR ART)
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`40
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`40
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`z
`x
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`38
`38
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`2”‘ k\\\\\\\\\\\\\
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`WI'IIZ 43
`&..\\
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`'l 44
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`Page 3 of 9
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`U.S. Patent
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`Sep. 15, 1997
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`Sheet 3 of 3
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`5,668,411
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`40
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`40
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`40
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`m. 8
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`-/48
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`38
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`38
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`Energy (Mev)
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`0.6
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`0.8
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`1.0
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`1.2
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`1.4
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`1.6
`
`——A¥—Cu/TiN/A|—Cu, As—deposited
`
`-----A|—Cu/TiN/A!—Cu,
`
`1 cycle at 450°C
`
`Normalized
`
`field
`
`O
`100
`
`150
`
`200
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`300
`250
`Channel
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`350
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`FIG. 9
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`...
`400
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`450
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`'
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`§%
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`::
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`:5
`34 -3;‘-‘.‘.‘.‘,} \‘.‘,‘-.‘;::-.:-.‘.‘:.-s 32
`«E.
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`'5‘;
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`22
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`Page 4 of 9
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`5,668,411
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`2
`FIG. 2 is a prior art drawing showing the wafer of FIG. 1
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`after heat
`treatment, where the metallization layer has
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`reacted with the diifusion barrier;
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`1
`DIFFUSION BARRIER TRILAYER FOR
`
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`
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`MINIMIZING REACTION BETWEEN
`
`
`
`METALLIZATION LAYERS OF
`
`
`INTEGRATED CIRCUITS
`
`
`
`This is a continuation of application Ser. No. 08/474,286
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`
`
`filed Jun. 2, 1995, now abandoned, which is a division of
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`application Ser. No. 08/412,473, filed Mar, 28, 1995, now
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`abandoned.
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`FIELD OF THE INVENTION
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`This invention relates generally to the fabrication of_
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`semiconductor devices, and more specifically to metalliza-
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`tion layers of integrated circuits.
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`BACKGROUND OF THE INVENTION
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`Semiconductors are widely used in integrated circuits for
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`electronic applications,
`including radios, computers,
`televisions, and high definition televisions. Such integrated
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`circuits typically use multiple transistors fabricated in single
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`crystal silicon. Many integrated circuits now contain mul-
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`tiple levels of metallization for interconnections.
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`Aluminum-copper (AlCu) alloys are typically used in
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`VLSI (very large scale integration) metallization. To
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`enhance the speed of devices, a low and stable sheet
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`resistance is required for AlCu. However, AlCu can react
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`with other metals (e.g. W) thereby increasing its sheet
`resistance. Sheet resistance is a measurement of a conduc-
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`tive material with a magnitude proportional to resistivity and
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`inverse of thickness. TiN has been applied as a difiusion
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`barrier between AlCu and me other metals to suppress their
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`reactions. However, heat treatment of AlCu/I‘iN layered
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`structures at 450° C. induces reactions between the AlCu and
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`TiN, leading to an increase in the sheet resistance of the
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`AlCu.
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`Several attempts have been made to improve the barrier
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`properties of TiN in AlfI‘iN/Si, Al/TiN/silicide/Si and
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`Al/l‘iN/W structures. In the past, the improvement of TiN
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`barriers have mostly been achieved by optimizing the
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`parameters during TiN deposition, such as introducing oxy-
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`gen flow during deposition, changing the substrate
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`temperature, or adding a substrate voltage bias. Other
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`attempts have included post-deposition treatments such as
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`thermal annealing and exposure to air.
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`SUMMARY OF THE INVENTION
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`The present invention is a method and structure for a
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`diifusion barrier trilayer comprising a bottom layer depos-
`ited on a substrate, a seed layer deposited on the bottom
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`layer, a top layer deposited on the seed layer, and a metal-
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`lization layer deposited on the top layer. Reaction of the
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`metallization layer with the top layer, which may occur upon
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`heat treatment, is minimized due to the improved properties
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`of the top layer of the dilfusion barrier trilayer. This results
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`in no degradation of sheet resistance of the metallization
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`layer upon heat treatment, and no loss of integrated circuit
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`device speed.
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`BRIEF DESCRIP'I'ION OF THE DRAWINGS
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`In the drawings, which form an integral part of the
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`specification and are to be read in conjunction therewith, and
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`in which like numerals and symbols are employed to des-
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`ignate similar components in various views unless otherwise
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`indicated:
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`FIG. 1 is a prior art drawing of a cross-sectional View of
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`a semiconductor wafer having a TiN diifusion barrier
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`between the metallization layer and the substrate;
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`Page 5 of 9
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`FIG. 3 is a Rutherford Backscattering Spectroscopy
`(RBS) of a prior art wafer before and after heat treatment;
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`10
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`15
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`25
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`FIG. 4 is a prior art drawing showing a typical via plug
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`structure used to connect a metallization layer to underlying
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`circuitry or metal layers;
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`FIG. 5 shows the wafer of FIG. 4 after heat treatment,
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`with a portion of the metallization layer reacted with the
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`difiusion barrier;
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`FIG. 6 demonstrates the crystal structure of the ditfusion
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`barrier of prior art, having a polycrystalline structure with
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`high-angle grain boundaries;
`FIG. 7 is a cross-sectional view of the present invention,
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`a diffusion barrier trilayer;
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`FIG. 8 demonstrates the crystal structure of the top layer
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`of the difiusion barrier trflayer, having a single-crystal-like
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`appearance;
`"
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`FIG. 9 is a Rutherford Backscattering Spectroscopy
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`(RBS) of an experimental wafer having a dilfusion barrier
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`bilayer, before and after heat treatment; and
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`30
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`FIG. 10 shows the present invention implemented on the
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`structure shown in FIG. 4.
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`35
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`40
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`45
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`50
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`55
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`65
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`DETAILED DESCRIPTION OF PREFERRED
`
`
`EMBODIIVIENTS
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`It has been found that the methods used in the past to
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`improve the barrier properties ofTiN are inadequate. Chang-
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`ing deposition temperature may induce change in other
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`properties of TiN. such as stress and grain size, making it
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`diflicult to optimize these_parameters at the same time.
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`Adding substrate bias induces ion bombardment of the TiN
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`layer, which may result radiation damage to existing
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`devices. Post-deposition treatments involve additional pro-
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`cessing steps, increasing process cycle time. Moreover,
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`thermal annealing (densification) of TiN is possible only at
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`the contact level on the integrated circuitry where AlCu is
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`not present. Dosing with oxygen during deposition is
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`undesirable, since oxygen may contaminate the Ti sputtering
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`target, form oxide particles and increase the sheet resistance
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`of TiN. Exposure of TiN to air for 24 hours has not been
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`found to improve the barrier properties of TiN.
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`The making and use of the presently preferred embodi-
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`ments are discussed below in detail. However, it should be
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`appreciated that the present invention provides many appli-
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`cable inventive concepts which can be embodied in a wide
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`variety of specific contexts. The specific embodiments dis-
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`cussed are merely illustrative of specific ways to make and
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`use the invention, and do not delimit the scope of the
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`invention.
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`The following is a description of a preferred embodiment
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`of the present invention, including manufacturing methods.
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`Corresponding numerals and symbols in the ditferent figures
`refer to corresponding parts unless otherwise indicated.
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`Table 1 below provides an overview of the elements of the
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`embodiments and the drawings.
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`Page 5 of 9
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`

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`5,668,411
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`3
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`TABLE 1
`
`
`Other Alternate Examples or
`
`
`
`Descriptions
`
`
`
`
`Generic
`Term
`
`Semiconductor
`
`wafer
`
`Substrate
`
`
`Tungsten vias, other metal layers
`
`
`
`
`
`or other semiconductor
`
`
`
`elements, (e.g. transistors,
`
`
`
`diodes); compound semi-
`
`
`
`conductors (e.g. GaAs, InP,
`
`
`
`
`Si/Ge, SiC) may be used in
`
`
`
`
`place of Si.
`
`50013.
`Diffusion
`
`
`barrier
`
`Aluminum alloy comprising
`Metallization
`
`
`
`
`0.5—4% copper by weight.
`layer
`
`
`
`
`Reacted portion Aluminum nitride; other com-
`
`
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`
`
`
`of metallization pounds having a higher sheet
`
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`
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`
`
`layer 26
`resistance than the metallization
`
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`
`
`layer 26.
`
`
`Dielectric layer Other dielectric materials.
`
`
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`
`
`Other conductors.
`First via liner
`
`
`
`
`
`Second via
`Other conductors.
`
`
`
`
`liner
`
`Via plug
`Other conductors; stud.
`
`
`
`
`Grain
`
`boundaries
`
`Crystal plane
`
`
`directions
`
`TN/‘Ii/TiN Dilfusion
`
`
`barrier trilayer
`
`
`
`
`
`
`
`400A of
`
`TiN
`
`
`45
`
`
`
`500}. of'I'i
`
`
`
`
`48
`
`
`
`100A of
`
`TiN
`
`
`TiN/AlCuITiN; Other metal
`
`
`
`layers with a top layer having a
`
`
`
`
`
`single-crystal-like structure.
`
`
`Bottom layer of l00—2000A of TiN, other metals
`
`
`
`
`
`
`such as TrW, ’IiWN, TiAlN,
`diffusion
`
`
`
`
`
`barrier trilayer TiSiN, Ta, TaN TaSiN or other
`
`
`
`
`
`
`crystalline or amorphous
`
`
`dilfusion barriers.
`
`
`200-1000}. of Ir; 1oo—5oooA
`Seed layer of
`
`
`
`
`of AlCu alloy with 0.5-4% by
`difiusion
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`
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`barrier trilaycr weight copper solutes; a material
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`with a similar crystal structure
`
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`to that of the top layer 48 of the
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`diifusion barrier trilayer.
`
`
`
`100—2000A of TiN, other metals
`
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`such as 'I'rW, TIWN or other
`
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`crystalline difiusion barriers.
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`Top layer of
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`dilfusion
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`barrier trilayer
`
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`4
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`diffusion barrier 24, where the metallization layer 26 usually
`comprised 6000 A of AlCu, having a sheet resistance of
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`approximately 50-60 m.Q/square.
`In semiconductor manufacturing, heat treatments of sub-
`
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`sequently deposited layers (not shown) are often required
`For example, some dielectric layers are cured at 400°—450°
`
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`C. Also, the final stage of some semiconductor manufactur-
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`ing methods is a sintering step to repair the damage in
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`transistors, in which the wafer is also heated to around 450°
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`C. Rcflow of aluminum conductive layers may be required
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`for some integrated circuits. Heating the wafer 20 causes the
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`atoms in the metallization layer 26 and difi‘usion barrier 24
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`to become more mobile, causing a reaction between the two.
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`This chemical reaction creates a reacted portion 28 of the
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`metallization layer 26. shown in FIG. 2. The reacted portion
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`28 is comprised of an aluminum-titanium andlor alurninum-
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`nitrite compound having a high sheet resistance, which may
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`extend into the metallization layer as much as 500-800 A.
`The reacted portion 28 of the metallization layer 26
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`increases the sheet resistance (for example. up to 15%, or 70
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`mfllsquare) of the metallization layer 26, which has a
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`deleterious effect on device speed, a critical feature of VLSI
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`circuits.
`
`FIG. 3 is a Rutherford Backscattering Spectroscopy
`
`
`
`
`(RBS) of the conventional AlCufFiN layered structure
`
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`
`
`shown in FIGS. 1 and 2 before and after heat treatments at
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`450° C. The tail of the Ti signals indicates reaction has
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`occurred between AlCu and the underlying TiN.
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`FIG. 4 shows another application of a diffusion barrier 24
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`
`
`found in prior art, where a dielectric layer 30 comprising, for
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`example, SiO2 has been deposited and etched so that elec-
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`trical contact may be made to underlying substrate 22. Afirst
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`via liner 32, typically comprised of titanium is deposited,
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`and next a second via liner 34, comprised of TiN, for
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`example, is deposited. The via plug 36 is usually formed
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`from a metal such as tungsten, but may also comprise other
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`metals or alloys. The dilfusion barrier 24 of TiN is deposited
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`next, followed by metallization layer 26, again comprised of
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`AlCu.
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`As with the other prior art example, when the structure is
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`exposed to heat, the metallization layer 26 reacts with the
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`diffusion barrier 24 to leave a reacted portion 28 of the
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`metallization layer 26 as shown in FIG. 5, increasing the
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`sheet resistance of the metallization layer 26.
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`A problem recognized herein with the prior art examples
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`
`discussed is the microstructure of the diffusion barrier 24.
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`TiN deposited on amorphous SiO2 has a randomly oriented
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`polycrystalline structure, as shown in FIG. 6. The crystal
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`structure has many high-angle grain boundaries 38 where
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`atoms can migrate easily when the structure is heated. The
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`crystal plane directions 40 of each crystal are highly irregu-
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`lar and resemble those of a polycrystalline material where
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`the directions of the crystal planes are not all aligned, e.g.
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`parallel. Therefore, the crystal structure of the TiN allows
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`atoms to easily migrate when a wafer is heated. The present
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`invention solves this problem by forming a layer of TiN
`
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`adjacent the metallization layer 26 having single-crystal-like
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`qualities. The terms “single-crystal-like” and “textured” are
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`defined as having a molecular crystalline structure similar to
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`that of a single crystal, where the direction of the crystal
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`planes are aligned substantially in the same direction.
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`The present invention is shown in cross-section in FIG. 7.
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`A ditfusion barrier Irilayer 42 is deposited on the substrate
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`22. upon which metallization layer 26 is deposited. 'I'he
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`dirfusion barrier trilayer 42 is comprised of a bottom layer
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`44, a seed layer 46 and a top layer 48. The layers 44, 46, 48
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`10
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`20
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`25
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`30
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`35
`
`Draw- Preferred
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`or Specific
`ing
`
`
`
`Element Examples
`
`
`20
`
`
`
`SiOZ
`
`
`TiN
`
`AlCu
`
`Aluminum-
`titanium
`
`compound
`
`
`
`
`SiO2
`
`Ti
`
`TiN
`
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`36 W
`
`38
`
`40
`
`22
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`24
`
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`26
`
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`28
`
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`30
`32
`34
`
`
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`42
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`44
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`The present invention is a dilfusion barrier trilayer that
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`minimizes the reaction of a metallization layer with under-
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`lying barrier layers of integrated circuits. The trilayer com-
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`prises a bottom layer similar to the single TiN layer used in
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`the past, a seed layer comprising a material with a similar
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`crystal structure as the top layer, and preferably with a
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`single-crystal-like microstructure, and a top layer grown
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`upon the seed layer, also having a single-crystalline-like
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`rnicrostructure. The top layer of the diffusion barrier trilayer
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`is adjacent the metallization layer. Reaction between the top
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`layer of the dilfusion barrier trilayer and the metallization
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`layer is eliminated or minimized, maintaining the sheet
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`resistance of the metallization layer and enhancing the speed
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`of the integrated circuit. As device size shrinks to quarter
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`micron range, maintaining a low sheet resistance of metal-
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`lization layers used to form conductors becomes increas-
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`ingly important.
`First. problems recognized herein with the prior art wfll be
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`discussed with FIGS. 1-6 used for reference. FIG. 1 shows
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`a cross-sectional view of a semiconductor wafer 20, with a
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`diffusion barrier 24 deposited on a substrate 22. The sub-
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`strate 22 may comprise S102, but may also comprise tung-
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`sten vias. other metal layers or semiconductor elements. The
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`diffusion barrier 24 of the past typically comprised a 500 A
`layer of TiN. A metallization layer 26 was deposited over the
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`45
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`50
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`55
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`65
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`Page 6 of 9
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`Page 6 of 9
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`

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`5
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`are typically deposited by sputtering but also may be depos-
`ited by chemical vapor deposition, or electron beam
`
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`deposition, for example. The TiN of bottom layer 44 and top
`
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`layer 48 is preferably sputtered on at approximately 400° C.
`The seed layer 46 is preferably 500 A of Ti sputtered on at
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`300° C. The bottom layer 44 preferably comprises 100-6000
`
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`A of TiN (more preferably 400 A of TiN), and is used to
`
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`isolate the seed layer 46, top layer 48 and metallization layer
`26 from underlying metals (e.g. W via plugs or studs). The
`
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`seed layer 46 may also be 100-6000 A of AlCu comprising
`0.5—4% by weight of copper, or other metals. The seed layer
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`46 acts as a seed, to alter the crystal structure and properties
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`of the top layer 48. The seed layer 46 is also used as a
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`sacrificial layer to isolate the bottom layer 44 from the top
`layer 48 so that very little interdilfusion occurs between
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`these two TiN layers. The top layer 48 is preferably
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`100-1000 A of TiN (more preferably, 100 A of TiN), grown
`on top of the seed layer 46 in an epitaxial manner. The top
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`layer 48 isolates the metallization layer 26 from the seed
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`layer 46. Due to the improved properties of the crystalline
`structure of the top layer (caused by the existence of the seed
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`layer 46), the TiN does not react significantly with the
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`metallization layer 26 and the sheet resistance of the met-
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`allization layer 26 remains unchanged upon heat treatment.
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`Moreover, the top layer 48 does not react with the seed layer
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`46.
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`In semiconductor technology, when silicon is grown, a
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`seed is used to orient the crystal structure in the desired
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`configuration. Similarly, the seed layer 46 of the trilayer 42
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`orients the crystal structure of the subsequently deposited
`top layer 48. The seed layer 46 of the diffusion barrier
`
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`trilayer 42 is a material such as Ti or AlCu that is chosen for
`
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`its crystal structure, lattice parameters and crystal alignment.
`A crystal structure and lattice parameters are desired that are
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`similar to those of the top layer 48. As a result, the top layer
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`48 has a single-crystal-like structure, as shown in FIG. 8.
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`Experiments have been performed to demonstrate the
`
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`
`
`advantages of the present invention. FIG. 9 shows an RBS
`
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`
`
`of a structure comprising a metallization layer 26 of AlCu,
`
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`
`
`a top layer 48 of TiN, and a seed layer 46 of AlCu, subjected
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`to the same heat treatment of 450° C. as described in FIG.
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`3. In contrast to FIG. 3, no reaction takes place between the
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`AlCu and TiN. In the experiment, the seed layer 46 is
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`comprised of AlCu and the bottom layer 44 is not used The
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`RBS results of the experiment were confirmed by cross-
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`section transmission electron microscopy. X-ray dilfraction
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`
`
`show by using the seed layer 42, the top layer 48 of TiN
`becomes more strongly textured or more single-crystalline-
`
`
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`
`
`
`like compared with polycrystalline TiN deposited on amor-
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`
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`
`
`
`phous SiO2. The (111) X-ray peak intensity of the TiN on
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`
`SiO2 is less than one tenth of that of the TiN on AlCu. The
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`enhanced texture of the TiN top layer 48 on the AlCu seed
`
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`layer 46 is due to the fact that the sputtered AlCu seed layer
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`46 has a strong (111) texture and the crystallographic
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`structure and lattice parameters of TiN top layer 48 are
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`similar to those of Al.
`
`
`
`Preferably, the top layer 48 is thinner than the bottom
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`layer 44, which causes less reaction between the metalliza-
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`tion layer 26 of AlCu. The use of the seed layer 46 allows
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`the top layer 48 of TiN to be thin enough to minimize the
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`reactions with the metallization layer 26, while the bottom
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`layer 44 of TiN may be of suflicient thickness to provide
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`electromigration resistance and suppression of possible
`interdiffusion between the metal stack (metallization layer
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`26/top layer 48/seed layer 46) and underlying metals, for
`example,
`the tungsten via plug 36 shown in FIG. 10.
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`Because of the thinness and improved properties (due to the
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`10
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`35
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`6
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`existence of the seed layer) of the top layer 48, the top layer
`48 does not react significantly with the metallization layer
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`26 and the sheet resistance of the metallization layer remains
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`unchanged upon heat treatment. Moreover, the top layer 48
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`does not react with the seed layer 46, either, which can be
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`seen in the RBS of FIG. 9.
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`Alternates for processes and element materials are appro-
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`priate and will be obvious to those skilled in the art. For
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`example, the top layer 48 may comprise other crystalline
`diifusion barrier materials such as TiW, TiWN, TiAlN,
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`TiSiN, Ta or TaN. The bottom layer 44 may comprise other
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`crystalline or amorphous diifusion barrier materials such as
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`TiW, TiWN, TiAlN, TiSiN, Ta, TaN, or TaSiN. The substrate
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`may be a dielectric (e.g. SiO2, PETEOS, BPSG), a metal
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`(e.g. W, Au) or a semiconductor (e.g. Si, GaAs). The seed
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`layer 46 may comprise other materials having a crystal
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`structure suitable for aligning the crystal structure of the top
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`layer 48. The metallization layer 26 may comprise
`aluminum, copper, alloys thereof, or other metals. The
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`ditfusion barrier trilayer 42 may be configured as continuous
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`films over the entire substrate 22, or patterned after
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`deposition, possibly into features with submicron dimen-
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`sions.
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`The present invention disclosed herein of a diifusion
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`barrier trilayer oifers an advantage over conventional diffu-
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`sion barriers in that reaction of metallization layers upon
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`heat
`treatment with the underlying diffusion barriers is
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`minimized or eliminated, resulting in no increase in sheet
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`resistance of the metallization layer, and thus no detrimental
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`effect on device speed.
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`While the invention has been described with reference to
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`illustrative embodiments, this description is not intended to
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`be construed in a limiting sense. Various modifications and
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`combinations of the illustrative embodiments, as well as
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`other embodiments of the invention, will be apparent to
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`persons skilled in the an upon reference to the description.
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`It is therefore intended that the appended claims encompass
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`any such modifications or embodiments.
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`What is claimed is:
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`1. A diifusion barrier trilayer for semiconductor wafers,
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`comprising:
`a bottom metal layer;
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`a seed metal layer adjacent said bottom layer and having
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`a crystalline structure; and
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`a top metal layer adjacent said seed metal layer and
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`having a crystalline structure;
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`wherein said crystalline structures of said top metal layer
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`and said seed metal layer are sing1e—crystal-like, and
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`wherein said crystalline structure of said top metal
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`layer is aligned to said crystalline structure of said seed
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`metal layer,
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`wherein said bottom layer comprises TiN, said seed metal
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`layer comprises Ti, and said top metal layer comprises
`TiN.
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`2. A diffusion barrier trilayer for semiconductor wafers,
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`comprising:
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`a bottom metal layer;
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`a seed metal layer adjacent said bottom layer and having
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`a crystalline structure; and
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`a top metal layer adjacent said seed metal layer and
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`having a crystalline structure;
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`wherein said crystalline structures of said top metal layer
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`and said seed metal layer are sing1e—crystal-like, and
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`wherein said crystalline structure of said top metal
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`layer is aligned to said crystalline structure of said seed
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`metal layer,
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`wherein said bottom layer comprises TiN, said seed metal
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`layer comprises an aluminum-copper alloy, and said
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`top metal layer comprises TiN.
`3. A semiconductor wafer metallization structure, com-
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`prising:
`a substrate;
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`a bottom layer adjacent said substrate;
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`a seed metal layer adjacent said bottom layer and having
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`a crystalline structure;
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`a top metal layer adjacent said seed metal layer and
`having a crystalline structure; and
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`a metallization layer adjacent said top metal layer;
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`wherein said crystalline structures of said top metal layer
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`and said seed metal layer are single-crystal—like, and
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`wherein said crystalline st