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`«2 United States Patent
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`US 6,887,353 B1
`(10) Patent No.:
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`Dingetal. May3, 2005
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`(45) Date of Patent:
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`US006887353B1
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`(54) TADLORED BARRIER LAYER WHICH
`PROVIDES IMPROVED COPPER
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`INTERCONNECT ELECTROMIGRATION
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`RESISTANCE
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`(75)
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`Inventors: Peijun Ding, San Jose, CA (US); Tony
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`Chiang, Mountain View, CA (US);
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`Barry L. Chin, Saratoga, CA (US)
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`(73) Assignee: Applied Materials, Inc., Santa Clara,
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`CA (US)
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`(*) Notice:
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`Subject to any disclaimer, the term ofthis
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`patent is extended or adjusted under 35
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`U.S.C. 154(b) by 863 days.
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`(21) Appl. No.: 08/995,108
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`(22)
`Filed:
`Dec. 19, 1997
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`(51)
`Int. Ch? oe C23C 14/00; C23C 14/32;
`O11. 21/44
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`(52) US. Chcece 204/192.15; 204/192.17;
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`204/192.22; 204/192.25; 438/656
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`(58) Field of Search 0000. 204/192.15, 192.17,
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`204/192.22, 192.25; 438/652, 656, 660
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`(56)
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`References Cited
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`4,319,264 A
`3/1982 Gangulee et al. o......... 357/71
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`4,985,750 A *
`1/1991 Hoshino ..........
`eee 257/751
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`§,186,718 A
`2/1993 Tepman etal.
`.. 29/25.01
`...
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`5,236,868 A
`8/1993 Nulman...........
`vee 437/190
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`5,240,880 A *
`8/1993 Hindmanet al.
`w+ 438/656
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`5,281,485 A
`1/1994 Colgan ctal.
`ve 428/457
`
`5,320,728 A
`we 204/192
`6/1994 ‘Tcpman........
`5,391,517 A *
`2/1995 Gelatos et al. ow. 438/643
`5/1996 Nulmanetal. ....00.. 438/653
`5,521,120 A *
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`.......
`5,571,752 A * 11/1996 Chen etal.
`v- 438/642
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`5,676,587 A
`10/1997 T.anders et al.
`......00.000.. 451/57
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`5,707,498 A *
`1/1998 Ngan........
`204/192.12
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`5,795,796 A *
`8/1998 Kim occ 438/660
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`FOREIGN PATENT DOCUMENTS
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`EP
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`EP
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`0570 205 Al
`11/1993 we HOIL/21/321
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`0 751 566 A2
`VW/1997 ee HO1L/23/532
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`OTHER PUBLICATIONS
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`Karen Holloway et al., “Tantalum as a Diffusion as a
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`Diffusion Barrier Between Copper and Silicon:
`|'ailure
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`Mechanism and Effect of Nitrogen Additions”, J. Appl.
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`Phys. 71 (11), Jun. 1, 1992, pp. 5433-5444.
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`Katsutaka Sasaki et al., “Stoichiometry of Ta—N Film andIts
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`Application for Diffusion Barrier in the Al, Ta/Ta—N/Si
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`Contact System”, Japanese Journal of Applied Physics, vol.
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`29, No. 6, Jun. 1990, pp. 1043-1047.
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`E. M. Zielinski et al., “The Effects of Processing on the
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`Microstructure of Copper Thin Films on Tantalum Barrier
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`Layers”, Mat. Res. Soc. Symp. Proc. vol. 391, (1995,) pp
`303-308.
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`PCYInternational Search Report dated Mar. 25, 1999.
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`Gang Bai et al., “Copper Interconnection Depostion Tech-
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`niques and Integration”, 1996 Symposium on VLSI Tech-
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`nology, Digests of Technical Papers (0-7803-3342-X/96,
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`TEEE).
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`S. M. Rossnagel and J. Hopwood, “Metal ion deposition
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`from ionized magnetron sputtering discharge”, J. Vac. Sci.
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`Technol. B, vol. 12, No. 1, pp. 449-453 (Jan./Feb. 1994).
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`S. M. Rossnagel et al., “Thin, high atomic weight refractory
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`film deposition for diffusion barrier, adhesion layer, and seed
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`layer applications”, J. Vac. Sci. Technol. B, vol. 14, No. 3,
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`pp. 1819-1827 (May/Tun. 1996).
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`C. Steinbruchel, “Patterning of Copper for Multilevel Met-
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`allization: Reactive Ion Etching and Chemical—Mechanical
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`Polishing”, Applied Surface Science, 91, pp. 139-146
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`(1995).
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`USS. Appl. No. 08/824,911, filed Mar. 27, 1997, of Ngan et
`al.
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`US. Appl. No. 08/863,451, filed May. 27, 1997, of Chiang
`et al.
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`US. Appl. No. 08/924,487,filed Aug. 23, 1997, of Ngan ct
`al.
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`* cited by examiner
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`Primary Examiner—Patrick Ryan
`Assistant Examiner—Julian Mercado
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`(74) Attorney, Agent, or Firm—Shirley L. Church
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`(57)
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`ABSTRACT
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`Disclosed herein is a barrier layer structure useful in forming
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`copper interconnects and electrical contacts of semiconduc-
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`tor devices. The barrier layer structure comprisesa first layer
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`of TaN,, which is applied directly over the substrate, fol-
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`lowed by a second layer of Ta. The TaN,/Ta barrier layer
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`structure provides both a barrier to the diffusion of a copper
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`layer deposited thereover, and enables the formation of a
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`copper layer having a high <111> crystallographic content
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`so that
`the electromigration resistance of the copper is
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`increased. The TaN, layer, where x ranges from about 0.1 to
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`about 1.5, is sufficiently amorphousto preventthe diffusion
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`of copper into the underlying substrate, which is typically
`silicon or a dielectric such as silicon dioxide. The thickness
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`of the TaN,, and Ta layers used for an interconnect depend on
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`the feature size and aspect ratio; typically, the TaN,, layer
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`thickness ranges from about 50 A to about 1,000 A while
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`the ‘la layer thickness ranges from about 20 A to about 500
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`A. For a contact via, the permissible layer thickness on the
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`via walls must be even more carefully controlled based on
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`feature size and aspect ratio;
`typically,
`the TaN,
`layer
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`thickness ranges from about 10 Ato about 300 A,while the
`Ta layer thickness ranges from about 5 A to about 300 A.
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`The copperlayer is deposited at the thickness desired to suit
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`the needs of the device. The copper layer may be deposited
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`using, any of the preferred techniques knownin the art.
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`Preferably, the entire copper layer, or at least a “seed” layer
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`is deposited using physical vapor deposition
`of copper,
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`techniques such as sputtering or evaporation, as opposed to
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`CVDorelectroplating. Since the crystal orientation of the
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`copper is sensitive to deposition temperature, and since the
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`copper may tend to dewet/delaminate from the barrier layer
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`if the temperature is too high,it is important that the copper
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`be deposited and/or annealed at a temperature of less than
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`about 500° C., and preferably at a temperature of less than
`about 300° C.
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`7 Claims, 2 Drawing Sheets
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`Page 1 of 9
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`TSMC Exhibit 1005
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`TSMC Exhibit 1005
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`Page 1 of 9
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`U.S. Patent
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`May 3, 2005
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`Sheet 1 of 2
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`US 6,887,353 B1
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`FANteaWAASWENWAENWLSSSWANANSSOUSNUSSSENNNEA_ASSESSESASNSSRSs
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`Page 2 of 9
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`May 3, 2005
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`Sheet 2 of 2
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`US 6,887,353 B1
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`US 6,887,353 B1
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`1
`TAILORED BARRIER LAYER WHICH
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`PROVIDES IMPROVED COPPER
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`INTERCONNECT ELECTROMIGRATION
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`RESISTANCE
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
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`The present invention pertains to a particular TaN,/Ta
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`barrier/wetting layer structure which increases the degree of
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`{111} crystal orientation in an overlying copper layer,
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`thereby providing improved electromigration resistance of
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`the copper.
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`2. Brief Description of the Background Art
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`As microelectronics continue to miniaturize, interconnec-
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`tion performance, reliability, and power consumption has
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`become increasingly important, and interest has grown in
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`replacing aluminum alloys with lower-resistivity and higher-
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`reliability metals. Copper offers a significant improvement
`over aluminum as a contact and interconnect material. For
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`example, the resistivity of copper is about 1.67 wQQ2cm, which
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`is only about half of the resistivity of aluminum.
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`There are two principal competing technologies under
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`evaluation by material and process developers working to
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`enable the use of copper. The first technology is known as
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`damascene technology.In this technology, a typical process
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`for producing a multilevel structure having feature sizes
`(i.e., width of the aperture) in the range of 0.5 micron (um)
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`or less would include: blanket deposition of a dielectric
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`material; patterning of the dielectric material to form open-
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`ings; deposition of a diffusion barrier layer and, optionally,
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`a wetting layer to line the openings; deposition of a copper
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`layer onto the substrate in sufficient thickness to fill the
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`openings; and removal of excessive conductive material
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`from the substrate surface using chemical-mechanical pol-
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`ishing (CMP)
`techniques. The damascene process is
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`described in detail by C. Steinbruchel in “Patterning of
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`copper for multilevel metallization: reactive ion etching and
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`chemical-mechanical polishing”, Applied Surface Science
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`91 (1995)139-146.
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`The competing technology is one which involves the
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`patterned etch of a copper layer.In this technology, a typical
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`process would include deposition of a copper layer on a
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`desired substrate (typically a dielectric material having a
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`barrier layer on its surface); application of a patterned hard
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`maskor photoresist over the copper layer; pattern etching of
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`the copper layer using wet or dry etch techniques; and
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`deposition of a dielectric material over the surface of the
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`patterned copper layer, to provide isolation of conductive
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`lines and contacts which comprise various integrated cir-
`cuits.
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`Typically, the copper layer can be applied using sputtering
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`techniques well knownin the art. The sputtering of copper
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`provides a much higher deposition rate than evaporation or
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`CVD (chemical vapor deposition) and provides a purer
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`copper film than CVD.
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`In integrated circuit interconnect structures where copper
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`is the material used to form conductive lines and contacts,it
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`is recognized that copper diffuses rapidly into adjacent
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`layers of SiO, and silicon and needs to be encapsulated.
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`Gang Bai et al.
`in “Copper Interconnection Deposition
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`Techniques and Integration”, 1996 Symposium on VLSI
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`Technology, Digests of Technical Papers (0-7803-3342-X/
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`96, IEEE), describe the effectiveness of Ta, TiN, W and Mo
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`as barrier layers for use with copper. They concluded that Ta
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`annealed in UHV(ultra high vacuum) after copper deposi-
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`tion provided the best barrier layer. Sputtered copper
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`appeared to be preferable over CVD copper and over elec-
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`troplated copper, although all
`the data for electroplated
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`copper was not available at the time of presentation of the
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`paper.
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`USS. Pat. No. 4,319,264 of Gangulee et al., issued Mar.9,
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`1982 and titled “Nickel-gold-nickel Conductors For Solid
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`State Devices” discusses the problem of electromigration in
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`solid state devices. In particular, the patent discusses the
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`application of direct current over particular current density
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`ranges which induces motion of the atoms comprising the
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`thin film conductor, the effect known as electromigration.
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`Electromigration is said to induce crack or void formation in
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`the conductor which, over a period of time, can result in
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`conductor failure. The rate of electromigration is said to be
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`dependent on the current density imposed on the conductor,
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`the conductor temperature, and the properties of the con-
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`ductor material. In high current density applications, poten-
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`tial conductor failure due to electromigration is said to
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`severely limit the reliability of the circuit. In discussing the
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`various factors affecting performance of the conductive
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`materials, grain structure is mentioned as being important.
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`(In order to obtain adequate lithographic line width
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`resolution,it is recommendedthatthe film be small grained,
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`with a grain size not exceeding about one-third of the
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`required line width.) Uniformity of grain size and preferred
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`crystallographic orientation of the grains are also said to be
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`factors which promote longer (electromigration limited)
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`conductor lifetimes. Fine grained films are also described as
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`being smoother, which is a desirable quality in semiconduc-
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`tor applications, to lessen difficulties associated with cov-
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`ering the conductor with an overlayer.
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`U.S. Pat. No. 5,571,752 to Chen et al., issued Nov. 5,
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`1996, discloses a method for patterning a submicron semi-
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`conductor layer of an integrated circuit. In one embodiment
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`describing an aluminum contact, titanium or titanium nitride
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`having a thickness of between approximately 300 and 2,000
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`A is formed by sputter deposition to reach the bottom of a
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`contact opening. Finally, a second conductive layer, typi-
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`cally aluminum,is applied over the surface of the conformal
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`conductive layer. The aluminum is sputtered on, preferably
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`at a temperature ranging between approximately 100° C. and
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`400° C. This method is said to make possible the filling of
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`contact openings having smaller device geometry design
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`requirements by avoiding the formation of fairly large grain
`sizes in the aluminum film.
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`As described in U.S. patent application Ser. No. 08/824,
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`911, of Ngan et al., filed Mar. 27, 1997 and commonly
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`assigned with the present invention, efforts have been made
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`to increase the <111> crystallographic content of aluminum
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`as a means of improving electromigration of aluminum. In
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`particular,
`the <111> content of an aluminum layer was
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`controlled by controlling the thickness of various barrier
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`layers underlying the aluminum layer. The underlying bar-
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`rier layer structure was Ti/TiN/TiN,, which enabled alumi-
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`num filling of high aspect vias while providing an aluminum
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`fill exhibiting the high degree of aluminum <111> crystal
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`orientation. The Ti/TiN/TiN,, barrier layer was deposited
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`using IMP (ion metal plasma) techniques, and the barrier
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`layer thicknesses were as follows. The thickness ofthe first
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`layer of Ti ranges from greater than about 100 A to about
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`500 A (the feature geometry controls the upper thickness
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`limit). The thickness of the TiN second layer ranges from
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`greater than about 100 A to less than about 800 A
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`(preferably, less than about 600 A). And,the TiN,, third layer
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`(having a Ti content ranging from about 50 atomic percent
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`Page 4 of 9
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`US 6,887,353 B1
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`3
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`titanium toabout 100 atomic percent titanium) ranges from
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`about 15 A to about 500 A. A Ti/TiN/TIN,, barrier layer
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`having this structure, used to line a contact via, is described
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`as enabling complete filling of via with sputtered warm
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`aluminum, where the feature size of the via or aperture is
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`about 0.25 micron or less and the aspect ratio ranges from
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`about 5:1 to as high as about 6:1.
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`Subsequently, in U.S. Pat. No. 5,882,399, of Nganet al.,
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`issued Mar. 16, 1999, the inventors disclose that to maintain
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`a consistently high aluminum <111> crystal orientation
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`content of an interconnect during the processing of a series
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`of semiconductor substrates in a given process chamber,it is
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`necessary to form thefirst deposited layer of the barrier layer
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`to a minimalthickness of at least about 150 A,to compen-
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`sate for irregularities in the crystal orientation which may be
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`present during the initial deposition of this layer when the
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`process chamberis initially started up (and continuing for
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`the first 7-8 wafers processed). Ngan etal. teach that in the
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`case of a copper conductive layer, it may also be necessary
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`that the first layer of a barrier layer structure underlying the
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`copper layer have a minimalthicknessofat least about 150
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`to enable a consistent crystal orientation within the
`A,
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`copper layer during the processing of a series of wafers in a
`semiconductor chamber.
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`4
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`temperature of the copper either during deposition or during
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`subsequent annealing processes not be higher than about
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`500° C. Preferably, the maximum temperature is about 300°
`C.
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`We havealso developed a method of producing a copper
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`interconnect structure comprising a copper layer deposited
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`over a barrier layer structure of the kind described above,
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`comprising a Ta layer overlying a TaN, layer, where the Cu
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`<111> crystallographic content is at least 70% of the Cu
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`<111> crystallographic content which can be obtained by
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`depositing the copper layer over a pure Ta barrier layer
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`whichis about 500 A thick. The method comprises the steps
`of:
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`a) depositing a first layer of TaN, having a thickness
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`ranging from greater than about 50 A to about 1,000 A;
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`b) depositing a second layer of Ta having a thickness
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`ranging from about 5 A to about 500 A over the surface
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`of the first layer of TaN,; and
`c) depositing a third layer ofcopperoverthe surface of the
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`second layer of Ta, wherein at least a portion of the
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`third layer of copperis deposited using a physical vapor
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`deposition technique, and wherein the substrate tem-
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`perature at which the third layer of copper is deposited
`is less than about 500° C
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`Further, we have developed a method of producing a
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`copper-comprising contact via structure comprising a copper
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`layer deposited over a barrier layer structure of the kind
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`described above, comprising a Ta layer overlying a TaN,,
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`layer; wherein the Cu <111> crystallographic content is at
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`least 70% of the Cu <111> crystallographic content which
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`can be obtained by depositing said copper layer over a pure
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`Ta barrier layer which is about 300 A thick. The method
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`comprises the steps of:
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`a) depositing a first layer of TaN, having a thickness
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`ranging from greater than about 10 A to about 300 A;
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`b) depositing a second layer of Ta having a thickness
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`ranging from about 5 A to about 300 A over the surface
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`of said first layer of TaN,; and
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`c) depositing a third layer of copper overthe surface ofthe
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`second layer of Ta, wherein at least a portion of the
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`third layer of copperis deposited using a physical vapor
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`deposition technique, and wherein the substrate tem-
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`perature at which the third layer of copper is deposited
`is less than about 500° C
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`In the method of producing a copper-comprising contact
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`structure described above, a least a portion of the first layer
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`of TaN,,, or the second layer of Ta, or the third layer of Cu,
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`or at least a portion of more than one of these three layers
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`may be deposited using ion-deposition sputtering, where at
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`least a portion of the sputtered emissionis in the form of ions
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`at the time the emission reaches the substrate surface, and
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`where, typically 10% or more of the sputtered emissionis in
`the form of ions at
`the time the emission reaches the
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`substrate surface.
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`
`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIG. 1 shows a schematic of a cross sectional view of a
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`sputtering chamberof the kind which can be used to deposit
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`the barrier layer of the present invention.
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`FIG. 2 showsa graph representative of the copper <111>
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`crystal orientation on a TaN,,/Ta barrier layer as a function
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`of the thickness of the Ta layer, with the TaN,, layer held
`constant at about 500 A.
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`DETAILED DESCRIPTION OF THE
`
`
`PREFERRED EMBODIMENTS
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`The present disclosure pertains to a TaN,/Ta/Cu structure
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`and a methodof creating that structure. The TaN,/Ta barrier
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`10
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`15
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`20
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`25
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`30
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`35
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`40
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`45
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`50
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`55
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`60
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`65
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`SUMMARYOF THE INVENTION
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`is a
`We have discovered that tantalum nitride (TaN,)
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`better barrier layer for copper than tantalum (Ta). However,
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`copper deposited directly over TaN, does not exhibit a
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`sufficiently high degree of <111> crystal orientation to
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`provide the desired copper electromigration characteristics.
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`We have developed a barrier layer structure comprising a
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`layer of Ta overlying a layer of TaN,, which provides both a
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`barrier to the diffusion of a copper layer deposited thereover,
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`and enables the formation of a copper layer having a high
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`<111> crystallographic content, so that copper electromi-
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`gration resistance is increased.
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`The TaN,, layer, where x ranges from about 0.1 to about
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`1.5, is sufficiently amorphous to prevent the diffusion of
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`copper into underlyingsilicon orsilicon oxide surfaces. The
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`desired thickness for the TaN, layer is dependent on the
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`device structure. For a typical interconnect, the TaN,, layer
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`thickness ranges from about 50 A to about 1,000 A. For a
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`contact, the TaN,, layer, the thickness on the wall of a contact
`via ranges from“about 10 A to about 300 A, depending on
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`the feature size. The TaN,, layer is preferably deposited using
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`standard reactive ion sputtering techniques at a substrate
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`temperature ranging from about 20° C. to about 500° C.
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`However, ion deposition sputtering techniques may be used
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`to deposit this layer.
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`The Ta layer deposited over the TaN, layer has a desired
`thickness ranging from about 5 Ato about 500 A, wherein
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`the thickness is preferably greater than about 20 A, depend-
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`ing on the feature size. The Ta layer is preferably deposited
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`using standard ion sputtering techniques at a substrate
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`temperature ranging from about 20° C. to about 500° C.
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`However, ion deposition sputtering techniques may be used
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`to deposit this layer.
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`The copper layer is deposited at the thickness desired to
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`the needs of the device. The copper layer may be
`suit
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`deposited using any of the preferred techniques knownin the
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`art. Preferably, the entire copper layer or at least a “seed”
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`layer of copper is deposited using physical vapor deposition
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`techniques such as sputtering or evaporation, as opposed to
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`CVD. Since the crystal orientation of the copperis sensitive
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`to deposition temperature, it is important that the maximum
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`Page 5 of 9
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`Page 5 of 9
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`

`

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`US 6,887,353 B1
`
`
`5
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`layer structure enables the deposition of an overlying copper
`
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`layer having a high <111> crystallographic content, so that
`
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`electromigration resistance of the copper is increased.
`
`I. Definitions
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`As a preface to the detailed description, it should be noted
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`that, as used in this specification and the appended claims,
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`the singular forms “a”, “an”, and “the” include plural
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`referents, unless the context clearly dictates otherwise. Thus,
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`for example, the term “a semiconductor” includes a variety
`of different materials which are known to have the behav-
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`ioral characteristics of a semiconductor, reference to a
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`“plasma” includes a gas or gas reactants activated by an RF
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`glow discharge, reference to “the contact material”or“inter-
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`connect material” includes copper and copper alloys, and
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`other conductive materials which have a melting point
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`enabling them to be sputtered over the temperature range
`described herein.
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`Specific terminology of particular importance to the
`
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`
`
`
`
`description of the present invention is defined below.
`
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`The term “aspect ratio” refers to the ratio of the height
`
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`
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`dimension to the width dimension of particular openings
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`into which an electrical contact is to be placed. For example,
`
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`a via opening which typically extends in a tubular form
`
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`through multiple layers has a height and a diameter, and the
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`aspect ratio would be the height of the tubular divided by the
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`diameter. The aspect ratio of a trench would be the height of
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`the trench divided by the minimal travel width of the trench
`at its base.
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`The term “contact via” or “via” refers to an electrical
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`contact having an aspect ratio which is typically greater than
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`1:1. Acontact via most frequently extends through multiple
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`layers of material to connect one electrically conductive
`element with another.
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`The term “copper” includes alloys of copper of the kind
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`typically used in the semiconductor industry. The preferred
`
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`embodiments described herein were for a copper alloy
`
`
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`
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`comprising about 98% by weight copper.
`
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`The term “feature” refers to contacts, vias, trenches, and
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`other structures which make up the topography of the
`substrate surface.
`
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`The term “interconnect” generally refers to conductive
`
`
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`structures within a semiconductive device. For purposes of
`
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`this patent application, electrical contacts in the form of a
`
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`conductive lines in trenches, for example) is distinguished
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`The term “ion-deposition sputtered” and the term “reac-
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`tive ion metal plasma (IMP)” refer to sputter deposition
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`tering cathode and the substrate support electrode, whereby
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`10% or more of the sputtered emission is in the form of ions
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`The term “traditional sputtering” refers to a method of
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`forming a film layer on a substrate wherein a target is
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`sputtered and the material sputtered from the target passes
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`between the target and the substrate to form a film layer on
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`the substrate, and no meansis provided to ionize a substan-
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`tial portion of the target material sputtered from the target
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`before it reaches the substrate. One apparatus configured to
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`provide traditional sputtering is disclosed in U.S. Pat. No.
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`5,320,728, the disclosure of which is incorporated herein by
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`Page6 of 9
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`reference. In such a traditional sputtering configuration, the
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`percentage of target material which is ionized is less than
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`10%, more typically less than 1%, of that sputtered from the
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`The term “XRD”(X-ray Diffraction) refers to a technique
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`commonly used to measure crystalline orientation, wherein
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`radiation over particular wavelengths is passed through the
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`to be characterized, and the diffraction of the
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`radiation, caused by the material through whichit passes,is
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`measured. A map is created which showsthe diffraction
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`pattern,and the crystal orientation is calculated based on this
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`A “traditionally sputtered” tantalum nitride-comprising
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`film or layer is deposited on a substrate by contacting a
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`tantalum target with a plasmacreated from an inert gas such
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`as argon in combination with nitrogen gas. A portion of the
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`tantalum sputtered from the target reacts with nitrogen gas
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`which has been activated by the plasma to produce tantalum
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`nitride, and the gas phase mixture contacts the substrate to
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`form a layer on the substrate.
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`II. An Apparatus for Practicing the Invention
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`A process system in which the method of the present
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`invention maybecarried out is the Applied Materials, Inc.
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`(Santa Clara, Calif.) Endura® Integrated Processing System.
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`This process system is not specifically shown in the Figures.
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`However, the system is generally known in the semicon-
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`ductor processing industry and is shown and described in
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