U.S. Patent 7,421,032
`Petition for Inter Partes Review
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`DOCKET NO.: 1033300-00287
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`7,421,032
`PATENT:
`INVENTORS: HUI JIN, AAMOD KHANDEKAR, ROBERT J. MCELIECE
`FILED:
`OCTOBER 3, 2006
`ISSUED:
`SEPTEMBER 2, 2008
`TITLE:
`SERIAL CONCATENATION OF INTERLEAVED
`CONVOLUTIONAL CODES FORMING TURBO-LIKE
`CODES
`___________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`Apple Inc.
`Petitioner
`
`v.
`
`California Institute of Technology
`Patent Owner
`
`Case IPR2017-0701
`
`
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 7,421,032
`UNDER 35 U.S.C. § 312 AND 37 C.F.R. § 42.104
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`U.S. Patent 7,421,032
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`TABLE OF CONTENTS
`I.  Mandatory Notices ............................................................................................... 3 
`A.  Real Party-in-Interest .................................................................................... 3 
`B.  Related Matters ............................................................................................. 3 
`C.  Counsel .......................................................................................................... 4 
`D.  Service Information ....................................................................................... 4 
`II.  Certification of Grounds for Standing ................................................................. 4 
`III. Overview of Challenge and Relief Requested ..................................................... 4 
`A.  Prior Art Patents and Printed Publications .................................................... 4 
`B.  Relief Requested ........................................................................................... 6 
`IV. Overview of the Technology ................................................................................ 6 
`A.  Error-Correcting Codes in General ............................................................... 6 
`B.  Coding Rate ................................................................................................... 9 
`C.  Performance of Error-Correcting Codes ..................................................... 10 
`D.  LDPC Codes, Turbocodes, and Repeat-Accumulate Codes ....................... 10 
`E.  Mathematical Representations of Error-Correcting Codes ......................... 13 
`F. 
`Irregularity ................................................................................................... 17 
`V.  Overview of the ’032 Patent .............................................................................. 19 
`A.  Claims ......................................................................................................... 19 
`B.  Summary of the Specification ..................................................................... 20 
`C.  Level of Ordinary Skill in the Art ............................................................... 21 
`VI. Claim Construction ............................................................................................ 22 
`A.  Equation in “generating” step of claim 1 .................................................... 22 
`B.  “irregular” ................................................................................................... 23 
`VII.  Overview of primary prior art references ................................................... 24 
`A.  Ping.............................................................................................................. 24 
`B.  MacKay ....................................................................................................... 32 
`C.  Divsalar ....................................................................................................... 33 
`D.  Luby97 ........................................................................................................ 36 
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`E.  Pfister ......................................................... Error! Bookmark not defined. 
`VIII.  Grounds for Challenge ................................................................................ 37 
`A.  Ground 1: Claims 1-10 Are Obvious over Ping in View of MacKay,
`Divsalar, and Luby97 .................................................................................. 37 
`IX. Conclusion .......................................................................................................... 74 
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`I. MANDATORY NOTICES
`A. Real Party-in-Interest
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`Apple Inc. (“Apple” or “Petitioner”) and Broadcom Corp. are the real
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`parties-in-interest.
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`B. Related Matters
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`U.S. Pat. No. 7,421,032 (the “’032 patent,” Ex. 1101) is assigned to the
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`California Institute of Technology (“Caltech” or “Patent Owner.”) On May 26,
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`2016, Caltech sued Apple, Broadcom Corp., and Avago Technologies, Ltd. in the
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`U.S. District Court for the Central District of California, claiming that Apple
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`products compliant with the 802.11n and 802.11ac wireless communication
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`standards infringe the ’032 patent (and three others). On August 15, 2016, Caltech
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`amended its complaint to assert patent infringement against Cypress
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`Semiconductor Corp. See Amended Complaint, California Institute of Technology
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`v. Broadcom, Ltd. et al. (Case 2:16-cv-03714), Docket No. 36. The ’032 patent
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`was also asserted by Caltech against Hughes Communications Inc. in California
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`Institute of Technology v. Hughes Communs., Inc (Case 2:13-cv-07245), and its
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`claims were challenged in one petition for inter partes review, IPR2015-00060.
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`Patents in the priority chain of the ’032 patent were challenged in IPR2015-00068,
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`IPR 2015-00067, IPR2015-00059, IPR2015-00061, IPR-2015-00081, IPR2017-
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`00210, IPR2017-00211, IPR2017-00219, IPR2017-00297, and IPR2017-00423.
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`C. Counsel
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`Lead Counsel: Richard Goldenberg (Registration No. 38,895)
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`Backup Counsel: Brian M. Seeve (Registration No. 71,721)
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`D.
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`Service Information
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`Petitioner consents to electronic service.
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`E-mail: richard.goldenberg@wilmerhale.com
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`Post and Hand Delivery: WilmerHale, 60 State St., Boston MA 02109
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`Telephone: 617-526-6548
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`II. CERTIFICATION OF GROUNDS FOR STANDING
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`Petitioner certifies pursuant to Rule 42.104(a) that the patent for which
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`review is sought is available for inter partes review and that Petitioner is not
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`barred or estopped from requesting an inter partes review challenging the patent
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`claims on the grounds identified in this Petition.
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`III. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
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`Pursuant to Rules 42.22(a)(1) and 42.104(b)(1)-(2), Petitioner challenges
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`claims 1-10 of the ’032 Patent (“the challenged claims”) and requests that each
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`challenged claim be canceled.
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`A.
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`Prior Art Patents and Printed Publications
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`Petitioner relies upon the patents and printed publications listed in the Table
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`of Exhibits, including:
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`U.S. Patent 7,421,032
`Petition for Inter Partes Review
`1. L. Ping, W. K. Leung, N. Phamdo, “Low Density Parity Check Codes
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`with Semi-random Parity Check Matrix.” Electron. Letters, Vol. 35,
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`No. 1, pp. 38-39, published on January 7, 1999 (“Ping”; Ex. 1103.)
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`2. D. J. C. MacKay, S. T. Wilson, and M. C. Davey, “Comparison of
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`Constructions of Irregular Gallager Codes,” IEEE Trans. Commun.,
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`Vol. 47, No. 10, pp. 1449-54, published in Oct. 1999 (“MacKay”; Ex.
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`EX. 1102.)
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`3. D. Divsalar, H. Jin, and R. J. McEliece, “Coding Theorems for
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`‘Turbo-like’ Codes,” Proc. 36th Allerton Conf. on Comm., Control
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`and Computing, Monticello, Illinois, pp. 201-10, September 1998
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`(“Divsalar”; Ex. 1117.)
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`4. Luby, M. et al., “Practical Loss-Resilient Codes,” STOC ’97, pp. 150-
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`59, published in 1997 (“Luby97”; Ex. 1108.)
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`The ’032 patent is a continuation of U.S. Patent No. 7,116,710, which claims
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`priority to provisional applications filed on May 18, 2000 and August 18, 2000.
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`The Petitioner reserves the right to dispute that the challenged claims are entitled to
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`these priority dates. However, even if the challenged claims are entitled to the
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`earliest claimed priority date of May 18, 2000, the references relied upon in this
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`Petition qualify as prior art under 35 U.S.C. § 102.
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`U.S. Patent 7,421,032
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`B. Relief Requested
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`Petitioner requests that the Patent Trial and Appeal Board cancel the
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`challenged claims because they are unpatentable under 35 U.S.C. § 103 as set forth
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`in this Petition. This conclusion is further supported by the declaration of Professor
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`James Davis, Ph.D. (“Davis Declaration,” Ex. 1104), filed herewith.
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`IV. OVERVIEW OF THE TECHNOLOGY
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`The ’032 patent relates to channel coding and error-correcting codes. This
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`section introduces channel coding, error-correcting codes, and several
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`developments in the field relevant to the ’032 patent. (Ex. 1104, ¶21.)
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`A. Error-Correcting Codes in General
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`Digital electronics use bits to represent information. A bit is a binary unit of
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`information that is a 1 or 0. Any type of information can be represented digitally
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`with bits. (Ex. 1104, ¶22.)
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`When transmitting binary information over an analog communication
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`channel, the data bits representing the information to be communicated
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`(“information bits”) are converted into an analog signal. This process is called
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`modulation. The transmitted signal is received by a receiving device and converted
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`back into binary form through demodulation. (Ex. 1104, ¶23.)
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`Modulation, Transmission, and Demodulation
`Transmission over physical channels is rarely 100% reliable. The
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`
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`transmitted signal can be corrupted during transmission by “noise”. Noise can
`
`cause bits to “flip” during transmission, causing a bit transmitted as a 1 to be
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`demodulated as 0, and vice versa. (Ex. 1104, ¶24.)
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`Error-correcting codes were developed to mitigate transmission errors.
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`Using the information bits, an error-correcting code generates “parity bits” that
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`allow the receiver to verify that the information bits were transmitted correctly, and
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`to correct transmission errors. (Ex. 1104, ¶25.)
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`Bits are encoded by an encoder, which receives a sequence of information
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`bits as input, generates parity bits according to a particular encoding algorithm, and
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`outputs a sequence of encoded bits (or data elements) called a codeword. The
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`codeword produced by the encoder is then modulated and transmitted as an analog
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`signal. (Ex. 1104, ¶26.)
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`At the receiver, the signal is received and demodulated, and the codeword is
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`passed to the decoder, which uses a decoding algorithm to recover the original
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`information bits. (Ex. 1104, ¶27.)
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`Encoding and Decoding
`Error-correcting codes work by adding redundant information to the original
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`
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`message. Due to redundancy, the information represented by a given information
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`bit is spread across multiple bits of the codeword. Thus, if a codeword bit is flipped
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`during transmission, the original information bit can still be recovered from the
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`other codeword bits. (Ex. 1104, ¶28.)
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`As a simple example, consider an encoding scheme, called “repeat-three,”
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`that outputs three copies of each information bit. In this scheme, the information
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`bits “1 0 1” would be encoded as “111 000 111.” Upon receipt, the decoder
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`converts instances of “111” into “1” and instances of “000” into “0” to produce the
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`decoded bits “1 0 1,” which match the original information bits. (Ex. 1104, ¶29.)
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`Suppose a bit is flipped during transmission, changing “000” to “010.” The
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`decoder will be able to detect a transmission error, because “010” is not a valid
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`“repeat-three” codeword. Using a “majority vote” rule, the decoder can infer that
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`the original information bit was 0, correcting the transmission error. Thus, due to
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`the redundancy incorporated into the codeword, no information was lost. (Ex.
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`1104, ¶30.)
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`Error-correcting codes may be either systematic or non-systematic. (Ex.
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`1120, p. 12, “Also, a BCI can be systematic or non-systematic.”; pp. 12-13,
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`Figures 2.1 and 2.2 captions showing both systematic and non-systematic
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`encoders.) In a systematic code, parity bits and original information bits are
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`included in the codeword. (Ex. 1120, p. 14 “For example, a systematic encoder is
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`one for which the encoder input (the data) forms a substring of the output (the
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`codword).”; Ex. 1121, pp. 6, 229.) In a non-systematic code, the encoded data
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`includes only parity bits. (Id.) Systematic and non-systematic codes had been
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`known for decades before May 18, 2000, the claimed priority date of the ʼ032
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`patent. (Ex. 1104, ¶¶31-32.)
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`B. Coding Rate
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`Many error-correcting codes encode information bits in groups, or blocks of
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`fixed length n. An encoder receives a k-bit block of information bits as input, and
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`produces a corresponding n-bit codeword. The ratio k/n is called the rate of the
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`code. Because the codeword generally includes redundant information, n is
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`generally greater than k, and the rate k/n of an error-correcting code is generally
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`less than one. (Ex. 1104, ¶33.)
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`Performance of Error-Correcting Codes
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`C.
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`One metric used to assess the performance of an error-correcting code is its
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`bit-error rate (BER.) The BER is defined as the number of corrupted information
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`bits divided by the total information bits during a particular interval. For example,
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`if a decoder outputs one thousand bits and ten are corrupted (i.e., they differ from
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`the original information bits), then the BER of the code during that interval is (10
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`bit errors) / (1000 total bits) = 0.01 or 1%. (Ex. 1104, ¶¶34-35.)
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`D. LDPC Codes, Turbocodes, and Repeat-Accumulate Codes
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`In 1963, Robert Gallager described a set of error-correcting codes called
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`Low Density Parity Check (“LDPC”) codes. Gallager described how LDPC codes
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`provide one method of generating parity bits from information bits using a matrix
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`populated with mostly 0s and relatively few 1s, as explained below. (See Gallager,
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`R., Low-Density Parity-Check Codes, Monograph, M.I.T. Press, 1963; Ex. 1105.)
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`(Ex. 1104, ¶38.)
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`Gallager’s work was largely ignored over the following decades. (Ex. 1104,
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`¶39.)
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`In 1993, researchers discovered “turbocodes,” a class of error-correcting
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`codes capable of transmitting information at a rate close to the so-called “Shannon
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`Limit” – the maximum rate at which information can be transmitted over a
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`channel. As explained in the Davis Declaration, the main drawback of
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`convolutional codes is that they do not perform well over channels where errors are
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`clustered together. Turbocodes overcome this deficiency: using a turbocode, a
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`small number of errors will not result in loss of information unless the errors
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`happen to fall close together in both the original data stream and in the permuted
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`data stream, which is unlikely. (Ex. 1104, ¶¶40-41.)
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`In 1995, David J. C. MacKay rediscovered Gallager’s work from 1963
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`relating to low-density parity-check (LDPC) codes and demonstrated that they
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`have performance comparable to that of turbocodes. See MacKay, D. J. C, and
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`Neal, R. M. “Near Shannon Limit Performance of Low Density Parity Check
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`Codes,” Electronics Letters, vol. 32, pp. 1645-46, 1996 (Ex. 1116.) This
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`rediscovery was met with wide acclaim. Turbocodes and LDPC codes have some
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`common characteristics: both codes use permutations to spread out redundancy,
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`and both use iterative decoding algorithms. (Ex. 1104, ¶42.)
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`In 1995 and 1996, researchers began to explore “concatenated”
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`convolutional codes. See Benedetto, S. et al., Serial Concatenation of Block and
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`Convolutional Codes, 32.10 Electronics Letters 887-8, 1996 (Ex. 1107.) While
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`turbocodes use two convolutional coders connected in parallel, concatenated
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`convolutional codes use two convolutional coders connected in series: the
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`information bits are encoded by a first encoder, the output of the first encoder is
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`interleaved, and the interleaved sequence is encoded by a second encoder. In such
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`codes, the first and second encoders are often called the “outer coder” and the
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`“inner coder,” respectively. (Ex. 1104, ¶43.)
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`In 1998, researchers developed “repeat-accumulate,” or “RA codes,” by
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`simplifying the principles underlying turbocodes. (See Ex. 1117.) In RA codes,
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`information bits are first passed to a repeater that repeats (i.e., duplicates) them and
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`outputs a stream of repeated bits (the encoder described above in the “repeat three”
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`coding scheme is one example of a repeater). The repeated bits are then optionally
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`reordered by an interleaver and passed to an “accumulator” to form parity bits. (Ex.
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`1104, ¶44.)
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`In accumulation, each input bit is added to the previous input bits to produce
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`a sequence of running sums, each of which represents the sum of all input bits yet
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`received. More formally, if an accumulator receives a sequence of input bits i1, i2,
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`i3, … in, it will produce output bits o1, o2, o3, … on, such that:
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`The  symbol denotes modulo-2 addition.1 Accumulators can be implemented
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`simply, allowing accumulate codes to be encoded quickly and cheaply. (Ex. 1104,
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`¶45.)
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`E. Mathematical Representations of Error-Correcting Codes
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`1.
`Linear Transformations
`Coding theorists often think of error-correcting codes in linear-algebraic
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`terms. For instance, a k-bit block of information bits is a k-dimensional vector of
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`bits and an n-bit codeword is an n-dimensional vector of bits (a “k-dimensional
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`vector of bits” is a sequence of k bits). The encoding process, which converts
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`blocks of information bits into codewords, is a linear transformation that maps k-
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`dimensional bit vectors to n-dimensional bit vectors. This transformation is
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`represented by an n × k matrix G called a generator matrix. For a vector of
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`information bits u, the corresponding codeword x is given by:
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`1 Modulo-2 addition (also called “XOR”) is an addition operation that is performed
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`on bits, defined as follows: 11=0, 10=1, 01=1, and 00=0.
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`The n-dimensional vectors that can be written in the form Gu are valid codewords.
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`(Ex. 1104, ¶46.)
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`Most n-dimensional vectors are not valid codewords. It is this property that
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`allows a decoder to determine when there has been an error during transmission.
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`This determination is made using an (n - k) × n matrix H, called a parity check
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`matrix. Using a parity check matrix, a given vector x is a valid codeword if and
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`only if Hx = 0. As explained in the Davis Declaration, if the parity check shows
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`that Hx does not equal 0, then the decoder determines there has been a
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`transmission error (much like the “010” example in the “repeat three” code above).
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`Each of the n - k rows (i.e., “n” minus “k”) of the parity-check matrix H represents
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`an equation that a valid codeword must satisfy. For example, consider a codeword
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`x and a parity check matrix H given as follows (Ex. 1104, ¶¶47-48):
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`If x is a valid codeword, the product Hx must be equal to 0, so we have:
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`As this equation shows, the first row of H represents the constraint that x3+x4 = 0,
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`and the second row of H represents the constraint that x1+x2 = 0. If the vector x
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`satisfies both of these constraints, it is a valid codeword. These can be referred to
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`as “parity constraints.” In practice, parity-check matrices often have hundreds or
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`thousands of rows, each of which represents an equation of the form xa+xb+…+xz =
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`0. These equations are called parity-check equations. (Ex. 1104, ¶49.)
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`2.
`Repeating and Permuting as Examples of LDGM Codes
`As explained above, the encoding process can be represented using a
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`generator matrix. This is true of all linear codes, including the “repeat,”
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`“interleave,” and “accumulate” phases of the “repeat-accumulate” codes discussed
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`above. Specifically, the “repeat” and “interleave” phases can be represented using
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`generator matrices whose entries are mostly 0s, with a relatively low proportion of
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`1s. Such generator matrices are called “low-density generator matrices” (LDGMs).
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`The following is a generator matrix that repeats each information bit twice (Ex.
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`1104, ¶50):
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`Using this generator matrix, encoding a sequence of input bits “101010101”
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`would result in the encoded sequence “110011001100110011” (the number of
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`times each input bit is repeated is determined by the number of “1s” in the column
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`corresponding to that input bit). In the 18×9 matrix above, 11.1% of the entries are
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`1s, and the rest are 0s, making GREPEAT2 a low-density generator matrix (LDGM).
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`(Ex. 1104, ¶51.)
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`Permutation is another linear transform represented by a low-density
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`generator matrix. For example, the matrix below is a permutation matrix that will
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`output bits in a different order than the input bits (Ex. 1104, ¶52):
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`Permutation matrices, like GSHUFFLE above, have exactly one 1 per row and
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`one 1 per column. The order of the output bits is determined by the position of
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`each 1 within its row/column. The matrix above, for example, would transform
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`input bits i1, i2, i3, i4, i5, i6, i7, i8 into the output sequence i2, i1, i7, i5, i4, i8, i6, i3.
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`Permutation matrices are square, with dimensions n×n, because the input sequence
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`and the output sequence have the same length. With only one 1 per row/column of
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`permutation matrices, the density of 1s is 1/n (GSHUFFLE has a density of 1/8, or
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`12.5%). With linear codes, which often operate on blocks of more than a thousand
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`bits, a permutation matrix might comprise 0.1% 1s or fewer, and, as explained in
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`the Davis Declaration, are therefore very low-density generator matrices
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`(LDGMs). (Ex. 1104, ¶53.)
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`F.
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`Irregularity
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`Irregular LDPC codes were first introduced in a 1997 paper by Luby et al.
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`See Luby, M. et al., “Practical Loss-Resilient Codes,” STOC ’97, 1997 (Ex. 1108).
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`The paper showed that irregular codes perform better than regular codes on certain
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`types of noisy channels. (Ex. 1104, ¶57.)
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`In regular codes, each information bit contributes to the same number of
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`parity bits, while in irregular codes different information bits or groups of
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`information bits contribute to different numbers of parity bits.2 This is consistent
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`with the Board’s construction of “irregular” in prior proceedings. (See, e.g.,
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`IPR2015-00060, Paper 18, p. 12.) (Ex. 1104, ¶58.)
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`After Luby’s initial paper describing irregularity, the same team of
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`researchers published a second paper, expanding the theory of irregularity in error-
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`correcting codes. (See Luby, M. et al., “Analysis of Low Density Codes and
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`Improved Designs Using Irregular Graphs,” STOC ’98, pp. 249-59, published in
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`1998; Ex. 1109). At the time, both of these papers were widely read by coding
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`theorists, and motivated extensive research into irregularity. (Ex. 1104, ¶59.)
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`For example, the 1998 Luby paper was the first reference cited in a paper by
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`Frey and MacKay titled “Irregular Turbocodes,” presented at the 1999 Allerton
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`Conference on Communications, Control, and Computing. (See Ex. 1110.) The
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`second author, MacKay, was the same researcher who had rediscovered LDPC
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`2 An information bit contributes to a parity bit if the column in the generator matrix
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`corresponding to the information bit has a 1 in the row corresponding to the parity
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`bit.
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`codes in 1995. In “Irregular Turbocodes,” the authors applied the concept of
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`irregularity to turbo codes by explaining how to construct irregular turbo codes
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`where some information bits connect to more check nodes than others. The
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`experimental results presented in the paper demonstrated that these irregular
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`turbocodes perform better than regular turbocodes known in the art. (See Ex. 1110,
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`p. 7.) (Ex. 1104, ¶60.)
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`By May 18, 2000, the claimed priority date of the ’032 patent, it was
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`common knowledge that the performance of any type of error-correcting code
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`could be improved with irregularity. (Ex. 1104, ¶61.)
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`V. OVERVIEW OF THE ’032 PATENT
`A. Claims
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`The ’032 patent includes 23 claims, of which claims 1, 11, and 18 are
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`independent. Claims 1-10 are challenged in this Petition. (Ex. 1104, ¶92)
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`Independent claim 1 is directed to a method that comprises generating a
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`sequence of parity bits from a collection of message bits in accordance with
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`particular mathematical formulas, and making the parity bits available for
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`transmission. (Ex. 1101, 7:61-10:57.) (Ex. 1104, ¶93)
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`B.
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`Summary of the Specification
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`The specification of the ’032 patent is generally directed to irregular RA
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`codes (or “IRA” codes). Figure 2 of the specification, below, shows the structure
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`of an IRA encoder (Ex. 1104, ¶94):
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`Ex. 1101, Fig. 2
`Explaining this figure, the patent describes encoding data using an outer
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`
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`coder 202 connected to an inner coder 206 via an interleaver 204 (labeled “P”) (Ex.
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`1101, 2:35-42.) (Ex. 1104, ¶95.)
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`Outer coder 202 receives a block of information bits and duplicates each bit
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`a given number of times, producing a sequence of repeated bits at its output. (Ex.
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`1101, 2:52-60.) The outer coder repeats bits irregularly – i.e., it outputs more
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`duplicates of some information bits than others. (Id.) (Ex. 1104, ¶96.)
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`The repeated bits are passed to an interleaver 204, where they are scrambled.
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`(Ex. 1101, 3:24-28.) The scrambled bits are then passed to the inner coder 206,
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`where they are accumulated to form parity bits. (Id., 2:66-3:18.) According to the
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`specification (Ex. 1104, ¶97):
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`Ex. 1101 at 3:3-18
`The specification describes systematic and non-systematic codes. In a
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`
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`systematic code, the encoder outputs a copy of the information bits in addition to
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`the parity bits output by inner coder 206 (the systematic output is represented in
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`Fig. 2. as an arrow running toward the right along the top of the figure). In a non-
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`systematic code, the codeword output by the encoder is comprised of parity bits
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`only. (Ex. 1104, ¶98.)
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`C. Level of Ordinary Skill in the Art
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`A person of ordinary skill in the art is a person with a Ph.D. in mathematics,
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`electrical or computer engineering, or computer science with emphasis in signal
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`processing, communications, or coding, or a master’s degree in the above area with
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`at least three years of work experience in this field at the time of the alleged
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`invention. (Ex. 1104, ¶91.)
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`VI. CLAIM CONSTRUCTION
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`A claim in inter partes review is given the “broadest reasonable construction
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`in light of the specification.” 37 C.F.R. § 42.100(b). See Cuozzo Speed
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`Technologies, LLC v. Lee, No. 15446, 579 U.S. ____, slip. op. at 13 (U.S. Jun. 20,
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`2016). Any claim term which lacks a definition in the specification is also given a
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`broad interpretation. In re ICON Health & Fitness, Inc., 496 F.3d 1374, 1379 (Fed.
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`Cir. 2007).
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`Should the Patent Owner, seeking to avoid the prior art, contend that the
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`claims warrant a narrower construction, the appropriate course is for the Patent
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`Owner to seek to amend the claims to expressly correspond to its contentions in
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`this proceeding. See 77 Fed. Reg. 48764 (Aug. 14, 2012).
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`Consistent with this standard, this section proposes constructions of terms
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`and provides support for these proposed constructions. Terms not included in this
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`section have their broadest reasonable meaning in light of the specification as
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`commonly understood by those of ordinary skill.
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`A. Equation in “generating” step of claim 1
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`The “generating” step of ’032 patent claim 1 recites the following equation:
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`"(cid:1876)(cid:3037)(cid:3404)(cid:1876)(cid:3037)(cid:2879)(cid:2869)(cid:3397)(cid:3533)(cid:2021)(cid:4666)(cid:3037)(cid:2879)(cid:2869)(cid:4667)(cid:3028)(cid:2878)(cid:3036)
`(cid:3028)
`(cid:3036)(cid:2880)(cid:2869)
`“(cid:1876)(cid:3037)(cid:2879)(cid:2869)” is the value of a parity bit “j-1,” and
`(cid:3533)(cid:2021)(cid:4666)(cid:3037)(cid:2879)(cid:2869)(cid:4667)(cid:3028)(cid:2878)(cid:3036)
`(cid:3028)
`(cid:3036)(cid:2880)(cid:2869)
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`where
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`
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`is the value of a sum of “a” randomly chosen irregular repeats of the
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`message bits.”
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`(Ex. 1112) (Ex. 1104, ¶99).
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`In IPR2015-00060, the Board construed this equation as: “The parity bit xj is
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`the sum of (a) the parity bit xj-1 and (b) the sum of a number, ‘a’ of randomly
`
`chosen irregular repeats of the message bits,” with the clarification that “[a] parity
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`bit xj is determined by two components. The first component is the parity bit
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`previous to the parity bit being determined (parity bit xj-1). The second component
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`is the sum of ‘a’ (‘a’ is a number) message bits (information bits) that have been
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`randomly repeated.” The Board’s prior construction is the broadest reasonable
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`construction of this term. (IPR2015-00060, Paper 18, p. 11.) (Ex. 1104, ¶100.)
`
`B.
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`“irregular”
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`In IPR2015-00060, the Board stated that the term “‘irregular’ refers to the
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`notion that different message bits or groups of message bits contribute to different
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`numbers of parity bits.” (IPR2015-00060, Paper 18, p. 11.) Petitioner agrees with
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`the Board’s previous construction of this term. (Ex. 1104, ¶101.)
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`As explained above, in irregular codes, different information bits or groups
`
`of information bits contribute to different numbers of parity bits. (Ex. 1104, ¶102.)
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`VII. OVERVIEW OF PRIMARY PRIOR ART REFERENCES
`A.
`
`Ping
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`L. Ping, W. K. Leung, N. Phamdo, “Low Density Parity Check Codes with
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`Semi-random Parity Check Matrix,” Electron. Letters, Vol. 35, No. 1, pp. 38-39
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`(“Ping”, Ex. 1103) was published in January 1999, more than a year before the
`
`filing of the provisional application to which the ʼ032 patent claims priority. Ping
`
`is thus prior art to the ʼ032 patent under 35 U.S.C. § 102(a) and (b). Ping was not
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`considered by the Patent Office during prosecution of the ’032 patent. (Ex. 1104,
`
`¶62.)3
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`Ping discloses an LDPC code with two stages or coding blocks: an outer
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`LDGM coder followed by an inner coder that is an accumulator. In Ping’s outer
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`coder, a generator matrix is applied to a sequence of information bits to produce
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`sums of information bits. In Ping’s inner coder, parity bits are set equal to
`
`
`3 Ping was at issue in IPR2015-00060. Petitioner has addressed the issues
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`addressed by the Board in IPR2015-00060 regarding Ping.
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`accumulated sums of information bits. Ping thus teaches LDPC codes that are also
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`accumulate codes. (See Ex. 1103, p. 38.) (Ex. 1104, ¶63.)
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`Ping’s Equation (4) shows that Ping’s encoding process involves two
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`distinct types of encoding operations – i.e., a two-stage encoding method. This is a
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`logical division of the Ping encoding p