JEDEC
`STANDARD
`
`Double Data Rate (DDR) SDRAM
`Specification
`
`JESD79
`
`JUNE 2000
`
`JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1014, Cover
`
`

`

`NOTICE
`
`JEDEC standards and publications contain material that has been prepared, reviewed, and
`approved through the JEDEC Board of Directors level and subsequently reviewed and approved
`by the EIA General Counsel.
`
`JEDEC standards and publications are designed to serve the public interest through eliminating
`misunderstandings between manufacturers and purchasers, facilitating interchangeability and
`improvement of products, and assisting the purchaser in selecting and obtaining with minimum
`delay the proper product for use by those other than JEDEC members, whether the standard is to
`be used either domestically or internationally.
`
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`may involve patents or articles, materials, or processes. By such action JEDEC does not assume
`any liability to any patent owner, nor does it assume any obligation whatever to parties adopting
`the JEDEC standards or publications.
`
`The information included in JEDEC standards and publications represents a sound approach to
`product specification and application, principally from the solid state device manufacturer
`viewpoint. Within the JEDEC organization there are procedures whereby an JEDEC standard or
`publication may be further processed and ultimately become an ANSI/EIA standard.
`
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`
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`
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`Arlington, VA 22201-3834
`
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`
`Printed in the U.S.A.
`All rights reserved
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1014, Cover-2
`
`

`

`PLEASE!
`
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`THE
`LAW!
`
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`
`JEDEC Solid State Technology Association
`2500 Wilson Boulevard
`Arlington, Virginia 22201-3834
`or call (703) 907-7559
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1014, Cover-3
`
`

`

`JEDEC Standard No. 79
`
`Double Data Rate (DDR) SDRAM Specification
`
`(The material contained in this standard was formulated under the cognizance of the JC-42.3
`Subcommittee on RAM Memories and approved by the JEDEC Board of Directors. The text in
`this standard is from the following BoD Ballots: JCB-99-70, JCB-99-84, JCB-00-08, JCB-00-10
`JCB-00-11, JCB-00-12, JCB-00-13, and JCB-00-23.)
`
`1 Purpose
`
`To define the minimum set of requirements for JEDEC-compliant 64M x4/x8/x16 DDR
`SDRAMs. System designs based on the required aspects of this specification will be supported
`by all DDR SDRAM vendors providing JEDEC compliant devices.
`
`2 Scope
`
`This comprehensive standard defines all required aspects of 64M x4/x8/x16 DDR SDRAMs,
`including features, functionality, AC and DC parametrics, packages and pin assignments. This
`scope will subsequently be expanded to formally apply to x32 devices, and higher density
`devices as well.
`
`-i-
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1014, p. i
`
`

`

` JESD 79
`Page 1
`
`DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION
`16 M x4 (4 M x4 x4 banks), 8 M x8 (2 M x8 x4 banks), 4 M x16 (1 M x16 x4 banks)
`
` FEATURES
`• Double–data–rate architecture; two data transfers
`per clock cycle
`• Bidirectional, data strobe (DQS) is transmitted/re-
`ceived with data, to be used in capturing data at
`the receiver
`• DQS is edge–aligned with data for READs; cen-
`ter–aligned with data for WRITEs
`• Differential clock inputs (CK and CK)
`• DLL aligns DQ and DQS transitions with CK transi-
`tions
`• Commands entered on each positive CK edge;
`data and data mask referenced to both edges of
`DQS
`• Four internal banks for concurrent operation
`• Data mask (DM) for write data
`• Burst lengths: 2, 4, or 8
`• CAS Latency: 2 or 2.5
`• AUTO PRECHARGE option for each burst access
`• Auto Refresh and Self Refresh Modes
`• 15.6 (cid:1)s Maximum Average Periodic Refresh Inter-
`val
`• 2.5 V (SSTL_2 compatible) I/O
`• VDDQ = +2.5 V ±0.2 V
`• VDD = +3.3 V ±0.3 V or +2.5 V ±0.2 V
`GENERAL DESCRIPTION
`The 64 Mb DDR SDRAM is a high–speed CMOS, dy-
`namic
`random–access
`memory
`containing
`67,108,864 bits. It is internally configured as a quad–
`bank DRAM.
`The 64 Mb DDR SDRAM uses a double–data–rate
`architecture to achieve high–speed operation. The
`double data rate architecture is essentially a 2n pre-
`fetch architecture with an interface designed to trans-
`fer two data words per clock cycle at the I/O pins. A
`single read or write access for the 64 Mb DDR SDRAM
`effectively consists of a single 2n–bit wide, one clock
`cycle data transfer at the internal DRAM core and two
`corresponding n–bit wide, one–half–clock–cycle data
`transfers at the I/O pins.
`A bidirectional data strobe (DQS) is transmitted ex-
`ternally, along with data, for use in data capture at the
`receiver. DQS is a strobe transmitted by the DDR
`SDRAM during READs and by the memory controller
`during WRITEs. DQS is edge–aligned with data for
`READs and center–aligned with data for WRITEs.
`The 64 Mb DDR SDRAM operates from a differential
`clock (CK and CK; the crossing of CK going HIGH and
`
`CK going LOW will be referred to as the postive edge of
`CK). Commands (address and control signals) are reg-
`istered at every positive edge of CK. Input data is regis-
`tered on both edges of DQS, and output data is refer-
`enced to both edges of DQS, as well as to both edges
`of CK.
`Read and write accesses to the DDR SDRAM are
`burst oriented; accesses start at a selected location
`and continue for a programmed number of locations in
`a programmed sequence. Accesses begin with the
`registration of an ACTIVE command, which is then fol-
`lowed by a READ or WRITE command. The address
`bits registered coincident with the ACTIVE command
`are used to select the bank and row to be accessed.
`The address bits registered coincident with the READ
`or WRITE command are used to select the bank and
`the starting column location for the burst access.
`The DDR SDRAM provides for programmable read
`or write burst lengths of 2, 4 or 8 locations. An AUTO
`PRECHARGE function may be enabled to provide a
`self–timed row precharge that is initiated at the end of
`the burst access.
`As with standard SDRAMs, the pipelined, multibank
`architecture of DDR SDRAMs allows for concurrent
`operation, thereby providing high effective bandwidth
`by hiding row precharge and activation time.
`An auto refresh mode is provided, along with a pow-
`er–saving, power–down mode. All inputs are compat-
`ible with the JEDEC Standard for SSTL_2. All outputs
`are SSTL_2, Class II compatible.
`Initial devices will have a VDD supply of 3.3 V (nomi-
`nal). Eventually, all devices will migrate to a VDD sup-
`ply of 2.5 V (nominal). During this initial period of prod-
`uct availability, this split will be vendor and device
`specific.
`This data sheet includes all features and functional-
`ity required for JEDEC DDR devices; options not re-
`quired, but listed, are noted as such. Certain vendors
`may elect to offer a superset of this specification by of-
`fering improved timing and/or including optional fea-
`tures. Users benefit from knowing that any system de-
`sign based on
`the
`required aspects of
`this
`specification are supported by all DDR SDRAM ven-
`dors; conversely, users seeking to use any superset
`specifications bear the responsibility to verify support
`with individual vendors.
`Note: The functionality described in, and the tim-
`ing specifications included in this data sheet are
`for the DLL Enabled mode of operation.
`
` Note: This specification defines the minimum set of requirements for JEDEC 64 M x4/x8/x16 DDR
`SDRAMs. Vendors will provide individual data sheets in their specific format. Vendor data sheets should
`be consulted for optional features or superset specifications.
`
`Release 1
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1014, p. 1
`
`

`

`. . . . . . . . .
`Fig. 25, Write to Read–Min tDQSS, Interrupting
`37
`Fig. 26, Write to Read–Min tDQSS, Odd, Interrupting
`. . . . .
`38
`Fig. 27, Write to Read–Nominal tDQSS, Interrupting
`. . . . .
`39
`Fig. 28, Write to Precharge–Max tDQSS, Noninterrupting
`. .
`40
`Fig. 29, Write to Precharge–Min tDQSS, Noninterrupting
`. .
`41
`Fig. 30, Write to Precharge–Max tDQSS, Interrupting
`. . . . .
`42
`Fig. 31, Write to Precharge–Min tDQSS, Interrupting
`. . . . .
`43
`Fig. 32, Write to Precharge–Min tDQSS, Odd, Interrupting
`.
`44
`Fig. 33, Write to Precharge – Nominal tDQSS,Interrupting
`. .
`45
`Precharge
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`46
`Fig. 34, Precharge Command
`. . . . . . . . . . . . . . . . . . . . . . . . .
`46
`Fig. 35, Power–Down
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`47
`Truth Table 2 (CKE)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`48
`Truth Table 3 (Current State, Same Bank)
`. . . . . . . . . . . . . . . . .
`49
`Truth Table 4 (Current State, Different Bank)
`. . . . . . . . . . . . . . .
`51
`Simplified State Diagram
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`53
`Absolute Maximum Ratings
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`54
`Capacitance
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`54
`DC Electrical Characteristics and Operating Conditions
`. . . . . . . . . . .
`54
`Output V–I Characteristics
`. . . . . . . . . . . . . . . . . . . . . . . . . . .
`55 & 56
`AC Operating Conditions
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`57
`Idd Specifications and Conditions
`57
`. . . . . . . . . . . . . . . . . . . . . . . . . .
`AC Electrical Characteristics (Timing Table)
`58 & 59
`. . . . . . . . . . . . . . .
`Fig. 36, Test Reference Load
`. . . . . . . . . . . . . . . . . . . . . . . . . .
`60
`Timing Waveforms
`. . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 37, Data Input Timing
`Fig. 38, Data Output Timing
`. . . . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 39, Initialize and Mode Register Set
`. . . . . . . . . . . . . . . . . .
`Fig. 40, Power–Down Mode
`. . . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 41, Auto Refresh Mode
`. . . . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 42, Self Refresh Mode
`. . . . . . . . . . . . . . . . . . . . . . . . . . .
`Reads
`. . . . . . . . . . . . . .
`Fig. 43, Read – Without Auto Precharge
`Fig. 44, Read – With Auto Precharge
`. . . . . . . . . . . . . . . .
`Fig. 45, Bank Read Access
`. . . . . . . . . . . . . . . . . . . . . . .
`Writes
`. . . . . . . . . . . . . .
`Fig. 46, Write – Without Auto Precharge
`Fig. 47, Write – With Auto Precharge
`. . . . . . . . . . . . . . . .
`Fig. 48, Bank Write Accesses
`. . . . . . . . . . . . . . . . . . . . . .
`Fig. 49, Write – DM Operation
`. . . . . . . . . . . . . . . . . . . . .
`
`
`
`JESD 79
`Page 2
`
`CONTENTS
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Pin Assignment Diagram
`3
`Functional Block Diagram – 16 M x4
`. . . . . . . . . . . . . . . . . . . . . . . . .
`4
`Functional Block Diagram – 8 M x8
`. . . . . . . . . . . . . . . . . . . . . . . . . .
`5
`Functional Block Diagram – 4 M x16
`. . . . . . . . . . . . . . . . . . . . . . . . .
`6
`Pin Descriptions
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`7
`Functional Description
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`8
`Initialization
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`8
`Register Definition
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`8
`Mode Register
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`8
`Burst Length
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`8
`Fig. 1, Mode Register Definition
`. . . . . . . . . . . . . . . . .
`9
`Table 1, Burst Definition
`. . . . . . . . . . . . . . . . . . . . . . .
`9
`Burst Type
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`10
`Read Latency
`10
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Operating Mode
`10
`. . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Table 2, CAS Latency & Frequency
`10
`. . . . . . . . . . . . . .
`Fig. 2, Required CAS Latencies
`. . . . . . . . . . . . . . . . . .
`11
`Extended Mode Register
`. . . . . . . . . . . . . . . . . . . . . . . . .
`12
`DLL Enable/Disable
`12
`. . . . . . . . . . . . . . . . . . . . . . . . .
`Output Drive Strength
`12
`. . . . . . . . . . . . . . . . . . . . . . . .
`QFC\ Enable/Disable
`12
`. . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 3, Extended Mode Register Definition
`12
`. . . . . . . . .
`Ternibology Definitions
`DDR–200
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`DDR–266
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Commands
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Truth Table 1a (Commands)
`. . . . . . . . . . . . . . . . . . . . . . . . . .
`Truth Table 1b(DM Operation)
`. . . . . . . . . . . . . . . . . . . . . . . . .
`Deselect
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`No Operation (NOP)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Mode Register Set
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Active
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Read
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Write
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Precharge
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Auto Precharge
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Burst Terminate
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Auto Refresh
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Self Refresh
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Operation
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Bank/Row Activation
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 4, Activating a Specific Row
`. . . . . . . . . . . . . . . . . . . .
`Fig. 5, tRCD & tRRD Definition
`. . . . . . . . . . . . . . . . . . . . .
`Reads
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 6, Read Command
`. . . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 7, Read Burst
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 8, Consecutive Read Bursts
`. . . . . . . . . . . . . . . . . . .
`Fig. 9, Nonconsecutive Read Bursts
`. . . . . . . . . . . . . . . . .
`Fig. 10, Random Read Accesses
`. . . . . . . . . . . . . . . . . . .
`Fig. 11, Terminating a Read Burst
`. . . . . . . . . . . . . . . . . . .
`Fig. 12, Read to Write
`. . . . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 13, Read to Precharge
`. . . . . . . . . . . . . . . . . . . . . . .
`Writes
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 14, Write Command
`. . . . . . . . . . . . . . . . . . . . . . . . .
`Figs. 15 & 16, Write Burst
`. . . . . . . . . . . . . . . . . . . . . . . .
`Fig. 17, Write to Write–Max tDQSS
`. . . . . . . . . . . . . . . . . .
`Fig. 18, Write to Write–Min tDQSS
`. . . . . . . . . . . . . . . . . .
`Fig. 19a, Write to Write–Max tDQSS, Nonconsecutive
`. . . .
`Fig. 19b, Write to Write–Min tDQSS, Nonconsecutive
`. . . .
`Fig. 20, Random Writes–Max tDQSS
`. . . . . . . . . . . . . . . .
`Fig. 21, Random Writes–Min tDQSS
`. . . . . . . . . . . . . . . .
`Fig. 22, Write to Read–Max tDQSS, Noninterrupting
`. . . . .
`Fig. 23, Write to Read–Min tDQSS, Noninterrupting
`. . . . . .
`Fig. 24, Write to Read–Max tDQSS, Interrupting
`. . . . . . . .
`
`12
`12
`13
`13
`13
`14
`14
`14
`14
`14
`14
`14
`14
`14
`14
`15
`16
`16
`16
`16
`17
`17
`18
`19
`20
`21
`23
`24
`25
`26
`26
`27
`28
`29
`30
`31
`32
`33
`34
`35
`36
`
`61
`61
`62
`63
`64
`65
`
`66
`67
`68
`
`69
`70
`71
`72
`
`Release 1
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1014, p. 2
`
`

`

` JESD 79
`Page 3
`
`ADDRESS ASSIGNMENT TABLE
`
` DENSITY BANKS ROW ADDR. COL ADDR BANK ADDR
`64 Mb
`4
`A0(cid:1)A11
`A0(cid:1)A9
`BA0, BA1
`64 Mb
`4
`A0(cid:1)A11
`A0(cid:1)A8
`BA0, BA1
`64 Mb
`4
`A0(cid:1)A11
`A0(cid:1)A7
`BA0, BA1
`
`16M X 4
`8M X 8
`4M X 16
`
`4M X 16 DDR SDRAM
`8M X 8 DDR SDRAM
`
`16M X 4 DDR SDRAM
`
`66
`
`65
`
`64
`
`63
`
`62
`
`61
`
`60
`
`59
`
`58
`
`57
`
`56
`
`55
`
`54
`
`53
`
`VSS
`
`NC
`
`DQ7 DQ15
`
`VSSQ
`
`NC
`
`NC DQ14
`
`DQ3
`
`DQ6 DQ13
`
`VDDQ
`
`NC
`
`NC
`
`NC DQ12
`
`DQ5 DQ11
`
`VSSQ
`
`NC
`
`NC DQ10
`
`DQ2
`
`DQ4 DQ9
`
`VDDQ
`
`NC
`
`NC
`
`NC DQ8
`
`66 PIN
`TSOP2
`MS–024FC
`&
`LSOJ
`MO–199
`&
`MO–200
`
`1 2 3 4 5 6 7 8 9 1
`
`0
`
`11
`
`12
`
`13
`
`14
`
`VDD
`
`DQ0
`
`NC
`
`VDDQ
`
`DQ1
`
`NC
`
`NC
`
`DQ2
`
`DQ1
`
`DQ0
`
`VSSQ
`
`DQ3
`
`NC
`
`DQ4
`
`DQ2
`
`NC
`
`NC
`
`VDDQ
`
`DQ5
`
`NC
`
`NC
`
`DQ6
`
`DQ3
`
`DQ1
`
`DQ7
`
`NC
`
`VSSQ
`
`NC
`
`NC
`
`VDDQ
`
`UDQS
`
`UDM
`
`10.16 mm
`PIN PITCH
`0.65 mm
`
`TOP VIEW
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`27
`
`28
`
`29
`
`30
`
`31
`
`32
`
`33
`
`52
`
`51
`
`50
`
`49
`
`48
`
`47
`
`46
`
`45
`
`44
`
`43
`
`42
`
`41
`
`40
`
`39
`
`38
`
`37
`
`36
`
`35
`
`34
`
`VSSQ
`
`DQS
`
`NC
`
`VREF
`
`VSS
`
`DM
`
`CK
`
`CK
`
`CKE
`
`NC
`
`NC
`
`A11
`
`A9
`
`A8
`
`A7
`
`A6
`
`A5
`
`A4
`
`VSS
`
`NC
`
`NC
`
`VDD
`NU,
`QFC
`NC
`
`W
`
`CE
`
`SR
`
`E
`
`NC
`
`BA0
`
`BA1
`A10
`/AP
`A0
`
`A1
`
`A2
`
`A3
`
`VDD
`
`LDQS
`
`LDM
`
`64 M DDR SDRAM (X4, X8, & X16) IN TSOP2 & LSOJ
`
`Release 1
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1014, p. 3
`
`

`

`JESD 79
`Page 4
`
`FUNCTIONAL BLOCK DIAGRAM -- x4 CONFIGURATION
`
`QFC
`GENERATOR
`
`DRVR
`
`QFC
`(OPTIONAL)
`
`DQ0 --
`DQ3, DM
`
`DQS
`
`8
`
`READ
`LATCH
`
`4
`
`4
`
`CLK
`
`DATA
`
`DLL
`
`MUX
`
`COL0
`
`4
`
`DQS
`GENERATOR
`
`1
`
`INPUT
`REGISTERS
`
`DRVRS
`
`DQS
`
`RCVRS
`
`1
`
`4
`
`1 1
`
`4 4
`
`1 1
`
`4 4
`
`WRITE
`FIFO
`&
`DRIVERS
`
`MASK
`
`2
`
`8
`
`CK
`out
`
`CK
`in
`
`DATA
`
`8
`
`CK
`
`COL0
`
`1
`
`BANK3
`
`BANK2
`
`BANK1
`
`BANK0
`MEMORY
`ARRAY
`(4,096 x 512 x 8)
`
`SENSE AMPLIFIERS
`
`4096
`
`I/O GATING
`DM MASK LOGIC
`
`8
`
`512
`(x8)
`
`COLUMN
`DECODER
`
`CONTROL
`LOGIC
`
`DECODE
`COMMAND
`
`CKEn
`
`CK
`CK
`
`Sn
`
`WE
`
`CAS
`RAS
`
`MODE REGISTERS
`
`REFRESH
`COUNTER
`
`12
`
`12
`
`12
`
`ROW--
`ADDRESS
`MUX
`
`12
`
`BANK0
`ROW--
`ADDRESS
`LATCH
`&
`DECODER
`
`4096
`
`A0--A11,
`BA0, BA1
`
`14
`
`ADDRESS
`REGISTER
`
`2
`
`10
`
`2
`
`BANK
`CONTROL
`LOGIC
`
`COLUMN--
`ADDRESS
`COUNTER/
`LATCH
`
`9
`
`1
`
`COL0
`
`Note 1: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
`not represent an actual circuit implementation.
`
`Note 2: DM is a unidirectional signal (input only) but is internally loaded to match the load of the bidirectional DQ and
`DQS signals.
`
`Release 1
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1014, p. 4
`
`

`

`JESD 79
`Page 5
`
`FUNCTIONAL BLOCK DIAGRAM -- x8 CONFIGURATION
`
`QFC
`GENERATOR
`
`DRVR
`
`CLK
`
`QFC
`(OPTIONAL)
`
`DQ0 --
`DQ7, DM
`
`DQS
`
`16
`
`READ
`LATCH
`
`8
`
`8
`
`MUX
`
`COL0
`
`DATA
`
`DLL
`
`8
`
`DQS
`GENERATOR
`
`1
`
`INPUT
`REGISTERS
`
`DRVRS
`
`DQS
`
`RCVRS
`
`1
`
`8
`
`1 1
`
`8 8
`
`COL0
`
`1 1
`
`8 8
`
`16
`
`WRITE
`FIFO
`&
`DRIVERS
`
`MASK
`
`2
`
`16
`
`CK
`in
`
`DATA
`
`CK
`out
`
`CK
`
`1
`
`BANK3
`
`BANK2
`
`BANK1
`
`BANK0
`MEMORY
`ARRAY
`(4,096 x 256 x 16)
`
`SENSE AMPLIFIERS
`
`4096
`
`CONTROL
`LOGIC
`
`DECODE
`COMMAND
`
`CKEn
`
`CK
`CK
`
`Sn
`
`WE
`
`CAS
`RAS
`
`MODE REGISTERS
`
`REFRESH
`COUNTER
`
`12
`
`12
`
`12
`
`ROW--
`ADDRESS
`MUX
`
`12
`
`BANK0
`ROW--
`ADDRESS
`LATCH
`&
`DECODER
`
`4096
`
`A0--A11,
`BA0, BA1
`
`14
`
`ADDRESS
`REGISTER
`
`2
`
`9
`
`2
`
`BANK
`CONTROL
`LOGIC
`
`I/O GATING
`DM MASK LOGIC
`
`16
`
`256
`(x16)
`
`COLUMN
`DECODER
`
`COLUMN--
`ADDRESS
`COUNTER/
`LATCH
`
`8
`
`1
`
`COL0
`
`Note 1: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
`not represent an actual circuit implementation.
`
`Note 2: DM is a unidirectional signal (input only) but is internally loaded to match the load of the bidirectional DQ and
`DQS signals.
`
`Release 1
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1014, p. 5
`
`

`

`JESD 79
`Page 6
`
`FUNCTIONAL BLOCK DIAGRAM -- x16 CONFIGURATION
`
`BANK3
`
`BANK2
`
`BANK1
`
`BANK0
`MEMORY
`ARRAY
`(4,096 x 128 x 32)
`
`SENSE AMPLIFIERS
`
`4096
`
`32
`
`READ
`LATCH
`
`16
`
`16
`
`CONTROL
`LOGIC
`
`DECODE
`COMMAND
`
`CKEn
`
`CK
`CK
`
`Sn
`
`WE
`
`CAS
`RAS
`
`MODE REGISTERS
`
`REFRESH
`COUNTER
`
`12
`
`12
`
`12
`
`ROW--
`ADDRESS
`MUX
`
`12
`
`BANK0
`ROW--
`ADDRESS
`LATCH
`&
`DECODER
`
`4096
`
`RCVRS
`
`1
`
`16
`
`1 1
`
`16
`
`16
`
`1 1
`
`16
`
`16
`
`COL0
`
`32
`
`WRITE
`FIFO
`&
`DRIVERS
`
`MASK
`
`2
`
`32
`
`ck
`in
`
`DATA
`
`ck
`out
`
`CK
`
`2
`
`A0--A11,
`BA0, BA1
`
`14
`
`ADDRESS
`REGISTER
`
`2
`
`8
`
`2
`
`BANK
`CONTROL
`LOGIC
`
`I/O GATING
`DM MASK LOGIC
`
`32
`
`128
`(x32)
`
`COLUMN
`DECODER
`
`COLUMN--
`ADDRESS
`COUNTER/
`LATCH
`
`7
`
`1
`
`COL0
`
`QFC
`GENERATOR
`
`DRVR
`
`CLK
`
`MUX
`
`COL0
`
`DATA
`
`DLL
`
`16
`
`DQS
`GENERATOR
`
`1
`
`INPUT
`REGISTERS
`
`DRVRS
`
`DQS
`
`QFC
`(OPTIONAL)
`
`DQ0 --
`DQ15,
`LDM, UDM
`
`LDQS,
`UDQS
`
`Note 1: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
`not represent an actual circuit implementation.
`
`Note 2: LDM and UDM are unidirectional signals (input only) but are internally loaded to match the load of the bidirec--
`tional DQ and DQS signals.
`
`Release 1
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1014, p. 6
`
`

`

` JESD 79
`Page 7
`
` PIN DESCRIPTIONS
`
`TYPE
`Input
`
`Input
`
`Input
`
`Input
`
`Input
`
`Input
`
`Input
`
`DESCRIPTION
`Clock: CK and CK are differential clock inputs. All address and control input signals
`are sampled on the crossing of the positive edge of CK and negative edge of CK.
`Output (read) data is referenced to the crossings of CK and CK (both directions of
`crossing).
`Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock sig-
`nals, and device input buffers and output drivers. Taking CKE LOW provides PRE-
`CHARGE POWER–DOWN and SELF REFRESH operation (all banks idle), or AC-
`TIVE POWER–DOWN (row ACTIVE in any bank). CKE is synchronous for POW-
`ER–DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for
`SELF REFRESH exit, and for output disable. CKE must be maintained high
`throughout READ and WRITE accesses. Input buffers, excluding CK, CK and CKE
`are disabled during POWER–DOWN. Input buffers, excluding CKE are disabled
`during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
`level after Vdd is applied. The standard pinout includes one CKE pin. Optional pin-
`outs include CKE0 and CKE1 on different pins, to facilitate device stacking.
`Chip Select: All commands are masked when S is registered high. S provides for
`external bank selection on systems with multiple banks. S is considered part of the
`command code. The standard pinout includes one S pin. Optional pinouts include
`S0 and S1 on different pins, to facilitate device stacking.
`Command Inputs: RAS, CAS and WE (along with S) define the command being
`entered.
`Input Data Mask: DM is an input mask signal for write data. Input data is masked
`when DM is sampled HIGH along with that input data during a WRITE access. DM
`is sampled on both edges of DQS. Although DM pins are input only, the DM loading
`matches the DQ and DQS loading. For the x16, LDM corresponds to the data on
`DQ0–DQ7; UDM corresponds to the data on DQ8–DQ15.
`Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write
`or PRECHARGE command is being applied.–
`Address Inputs: Provide the row address for ACTIVE commands, and the column
`address and AUTO PRECHARGE bit for READ/WRITE commands, to select one
`location out of the memory array in the respective bank. A10 is sampled during a
`precharge command to determine whether the PRECHARGE applies to one bank
`(A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank
`is selected by BA0, BA1. The address inputs also provide the op–code during a
`MODE REGISTER SET command. BA0 and BA1 define which mode register is
`loaded during the MODE REGISTER SET command (MRS or EMRS).
`Input/Output: Data bus
`Data Strobe: Output with read data, input with write data. Edge–aligned with read
`data, centered in write data. Used to capture write data. For the x16, LDQS corre-
`sponds to the data on DQ0–DQ7; UDQS corresponds to the data on DQ8–DQ15.
`FET Control: Optional. Output during every Read and Write access. Can be used to
`control isolation switches on modules. Open drain output.
`No Connect: No internal electrical connection is present.
` —
`DQ Power Supply: +2.5 V ±0.2 V.
`Supply
`DQ Ground.
`Supply
`Power Supply: One of +3.3 V ±0.3 V or +2.5 V ±0.2 V (device specific).
`Supply
`Supply Ground.
`Input
`SSTL_2 reference voltage.
`
`I/O
`I/O
`
`Output
`
`SYMBOL
`CK, CK
`
`CKE(n)
`
`S(n)
`
`RAS, CAS,
`WE
`DM
`
`BA0, BA1
`
`A0–A11
`
`DQ
`DQS
`
`QFC
`
`NC
`VDDQ
`VSSQ
`VDD
`VSS
`VREF
`
`Release 1
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1014, p. 7
`
`

`

`JESD 79
`Page 8
`
` FUNCTIONAL DESCRIPTION
`The 64 Mb DDR SDRAM is a high–speed CMOS,
`dynamic
`random–access memory containing
`67,108,864 bits. The 64 Mb DDR SDRAM is inter-
`nally configured as a quad–bank DRAM.
`The 64 Mb DDR SDRAM uses a double–data–
`rate architecture to achieve high–speed operation.
`The double–data–rate architecture is essentially a
`2n prefetch architecture, with an interface designed
`to transfer two data words per clock cycle at the I/O
`pins. A single read or write access for the 64 Mb
`DDR SDRAM consists of a single 2n–bit wide, one
`clock cycle data transfer at the internal DRAM core
`and two corresponding n–bit wide, one–half clock
`cycle data transfers at the I/O pins.
`Read and write accesses to the DDR SDRAM are
`burst oriented; accesses start at a selected location
`and continue for a programmed number of locations
`in a programmed sequence. Accesses begin with
`the registration of an ACTIVE command, which is
`then followed by a READ or WRITE command. The
`address bits registered coincident with the ACTIVE
`command are used to select the bank and row to be
`accessed (BA0, BA1 select the bank; A0–A11 se-
`lect the row). The address bits registered coincident
`with the READ or WRITE command are used to se-
`lect the starting column location for the burst ac-
`cess.
`Prior to normal operation, the DDR SDRAM must
`be initialized. The following sections provide de-
`tailed information covering device initialization, reg-
`ister definition, command descriptions and device
`operation.
`INITIALIZATION
`DDR SDRAMs must be powered up and initialized
`in a predefined manner. Operational procedures
`other than those specified may result in undefined
`operation. Power must first be applied to VDD, then
`to VDDQ, and finally to VREF (and to the system
`VTT). VTT must be applied after VDDQ to avoid de-
`vice latch–up, which may cause permanent dam-
`age to the device. Vref can be applied any time after
`VDDQ, but is expected to be nominally coincident
`with Vtt. Except for CKE, inputs are not recognized
`as valid until after VREF is applied. CKE is an
`SSTL_2 input, but will detect an LVCMOS LOW lev-
`el after VDD is applied. Maintaining an LVCMOS
`LOW level on CKE during power–up is required to
`guarantee that the DQ and DQS outputs will be in
`the High–Z state, where they will remain until driven
`in normal operation (by a read access). After all
`power supply and reference voltages are stable,
`and the clock is stable, the DDR SDRAM requires a
`200 m s delay prior to applying an executable com-
`mand.
`
`Once the 200 m s delay has been satisfied, a DE-
`SELECT or NOP command should be applied, and
`CKE should be brought HIGH. Following the NOP
`command, a PRECHARGE ALL command should
`be applied. Next a MODE REGISTER SET com-
`mand should be issued for the Extended Mode Reg-
`ister, to enable the DLL, then a MODE REGISTER
`SET command should be issued for the Mode Reg-
`ister, to reset the DLL, and to program the operating
`parameters. 200 clock cycles are required between
`the DLL reset and any read command. A PRE-
`CHARGE ALL command should be applied, placing
`the device in the ”all banks idle” state.
`Once in the idle state, two AUTO refresh cycles
`must be performed. Additionally, a MODE REG-
`ISTER SET command for the Mode Register, with
`the reset DLL bit deactivated (i.e., to program oper-
`ating parameters without resetting the DLL) must
`be performed. Following these cycles, the DDR
`SDRAM is ready for normal operation.
`REGISTER DEFINITION
`MODE REGISTER
`The Mode Register is used to define the specific
`mode of operation of the DDR SDRAM. This defini-
`tion includes the selection of a burst length, a burst
`type, a CAS latency, and an operating mode, as
`shown in Figure 1. The Mode Register is pro-
`grammed via the MODE REGISTER SET com-
`mand (with BA0 = 0 and BA1 = 0) and will retain the
`stored information until it is programmed again or
`the device loses power (except for bit A8, which is
`self–clearing).
`Mode Register bits A0–A2 specify the burst
`length, A3 specifies the type of burst (sequential or
`interleaved), A4–A6 specify the CAS latency, and
`A7–A11 specify the operating mode.
`The Mode Register must be loaded when all
`banks are idle and no bursts are in progress, and the
`controller must wait the specified time before initiat-
`ing any subsequent operation. Violating either of
`these requirements will result in unspecified opera-
`tion.
`Burst Length
`Read and write accesses to the DDR SDRAM are
`burst oriented, with the burst length being program-
`mable, as shown in Figure 1. The burst length deter-
`mines the maximum number of column locations
`that can be accessed for a given READ or WRITE
`command. Burst lengths of 2, 4, or 8 locations are
`available for both the sequential and the interleaved
`burst types.
`Reserved states should not be used, as unknown
`operation or incompatibility with future versions
`may result.
`
`Release 1
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1014, p. 8
`
`

`

` JESD 79
`Page 9
`
` Table 1
`
`BURST DEFINITION
`
`When a READ or WRITE command is issued, a
`block of columns equal to the burst length is effec-
`tively selected. All accesses for that burst take
`place within this block, meaning that the burst will
`wrap within the block if a boundary is reached. The
`block is uniquely selected by A1–Ai when the burst
`length is set to two, by A2–Ai when the burst length
`is set to four and by A3–Ai when the burst length is
`set to eight (where Ai is the most significant column
`address bit for a given configuration). The remain-
`ing (least significant) address bit(s) is (are) used to
`select the starting location within the block. The pro-
`grammed burst length applies to both read and write
`bursts.
`
`BA1
`
`BA0
`
`A11
`
`A10
`
`A9
`
`A8
`
`A7 A6 A5 A4 A3
`
`A2 A1 A0
`
`Address Bus
`
`BurstBurst
`
`Length
`
`tartingStarting
`
`
`CoumnCoumn
` Adress:
`
`2
`
`4
`
`A0
`
`0
`
`1
`
`A0
`
`0
`
`1
`
` 0
`
`1
`
`A1
`
`0
`
`0
`
`1
`
`1
`
`A2 A1 A0
`
`
`
`esses ithin a Burstrder oOrder of Accesses Within a Burst
`
`
`
`
`
`Type = Sequential
`
`Type = Interleaved
`
`0–1
`
`1–0
`
`0–1–2–3
`
`1–2–3–0
`
`2–3–0–1
`
`3–0–1–2
`
`0–1
`
`1–0
`
`0–1–2–3
`
`1–0–3–2
`
`2–3–0–1
`
`3–2–1–0
`
`11
`
`13
`
`12
`
`0*
`
`0*
`
`9
`
`8
`
`10
`Operating Mode
`
`7
`
`65
`
`4
`
`3
`
`2
`
`1
`
`0
`
`Mode Register
`
`CAS Latency BT
`
`Burst Length
`
`0
`
`0
`
`0
`
`0
`
`0
`
`1
`
`1
`
`0
`
`1
`
`0
`
`1
`
`0–1–2–3–4–5–6–7
`
`0–1–2–3–4–5–6–7
`
`1–2–3–4–5–6–7–0
`
`1–0–3–2–5–4–7–6
`
`2–3–4–5–6–7–0–1
`
`2–3–0–1–6–7–4–5
`
`3–4–5–6–7–0–1–2
`
`3–2–1–0–7–6–5–4
`
`8
`
`0
`
`1
`
`1
`
`1
`
`1
`
`0
`
`0
`
`1
`
`1
`
`0
`
`1
`
`0
`
`1
`
`4–5–6–7–0–1–2–3
`
`4–5–6–7–0–1–2–3
`
`5–6–7–0–1–2–3–4
`
`5–4–7–6–1–0–3–2
`
`6–7–0–1–2–3–4–5
`
`6–7–4–5–2–3–0–1
`
`7–0–1–2–3–4–5–6
`
`7–6–5–4–3–2–1–0
`
`
`
`
`
`
`Note:
`
`1. For a burst length of two, A1–Ai selects the two–
`data–element block; A0 selects the first access
`within the block.
`2. For a burst length of four, A2–Ai selects the four–
`data–element block; A0–A1 selects the first ac-
`cess within the block.
`3. For a burst length of eight, A3–Ai selects the eight–
`data–element block; A0–A2 selects the first ac-
`cess within the block.
`4. Whenever a boundary of the block is reached with-
`in a given sequence above, the following access
`wraps within the block.
`
`Burst Length
`
`A2
`
`A1
`
`A0
`
`A3 = 0
`
`A3 = 1
`
`Reserved
`
`Reserved
`
`2 4 8
`
`2 4 8
`
`Reserved
`
`Reserved
`
`Reserved
`
`Reserved
`
`Reserved
`