(19) United States
`(2) Patent Application Publication (10) Pub. No.: US 2005/0249011 A1
`(43) Pub. Date:
`Nov. 10, 2005
`Maeda
`
`US 200502490.11A1
`
`(54) MEMORY CONTROL DEVICE HAVING
`LESS POWER CONSUMPTION FOR
`BACKUP
`
`(30)
`
`Foreign Application Priority Data
`
`Feb. 23, 2001 (JP)...................................... 2001-047504
`
`(75) Inventor: Tadaaki Maeda, Tokyo (JP)
`Correspondence Address:
`FITZPATRICK CELLA. HARPER & SCINTO
`30 ROCKEFELLER PLAZA
`NEW YORK, NY 10112 (US)
`(73) Assignee: Canon Kabushiki Kaisha, Tokyo (JP)
`
`(21) Appl. No.:
`
`11/179,539
`
`(22) Filed:
`
`Jul. 13, 2005
`
`Related U.S. Application Data
`(62) Division of application No. 10/078,396, filed on Feb.
`21, 2002.
`
`Publication Classification
`
`(51) Int. Cl." … G11C 7/00
`(52) U.S. Cl. … 365/.222
`(57)
`ABSTRACT
`When power stoppage of a main power supply is detected
`during a normal operation, a power controller switches a
`power supply for a DRAM from the main power supply to
`a battery power supply and makes an instruction signal for
`instruction a self-refresh mode to a memory controller
`active. In response to this, the memory controller changes a
`clock enable signal for the DRAM to a low level to establish
`the self-refresh mode of the DRAM, and, after, the self
`refresh mode of the DRAM is established, supplying of
`power to the memory controller is stopped. The clock enable
`signal for the DRAM is maintained to the low level by
`pull-down resistance even when the supplying of power to
`the memory controller is stopped from a condition that the
`signal is changed to the low level in the self-refresh mode,
`thereby maintaining the self-refresh mode of the DRAM.
`
`NORMAL
`POWER-UP
`
`— — — — —
`
`.
`;
`
`
`
`TO
`
`
`
`i.
`i
`
`t
`
`. .
`POWER...
`\;
`MEMORY
`CONTROLLER
`& SDRAM
`BACKUP Clk!
`Reset.L
`RamBackup :
`ClkE
`Cali
`RaS.L
`|
`|
`|
`cal
`Wel; ;
`;
`;
`;
`SeRe?ki i ;
`;
`; SelfRefesh Command
`POWER H
`(??leh)
`CONTROLLER
`
`i
`i
`
`i
`
`i
`i
`
`l
`w
`
`i
`
`t
`*
`
`---
`
`- %
`
`| DETECTION OF
`
`; POWERDOWN
`
`i
`l
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1013, p. 1
`
`

`

`Patent Application Publication Nov. 10, 2005 Sheet 1 of 6
`
`US 2005/0249011 A1
`
`FIG. 1
`
`14
`VCC } Vbat
`
`15
`VOC } Vbat
`
`MEMORY
`CONTROLLER
`
`RamBackUp
`Vbatt
`
`
`
`SelfReiOk
`
`
`
`
`
`
`
`13
`
`POWER
`CONTROLLER
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1013, p. 2
`
`

`

`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1013, p. 3
`
`

`

`Patent Application Publication Nov. 10, 2005 Sheet 3 of 6
`
`US 2005/0249011 A1
`
`POWER-UP
`Ti
`
`
`
`FIG. 2B
`T2
`
`T3
`
`; CANCEL QF.RESET.L
`;RamBackup "Low"
`
`FROM
`FIG. 2B
`
`CANCEL OF RESET.L
`|Rambackup "High"
`
`:
`
`H–––––––. We
`: SELF-REFRESH MODE:
`;
`:
`I
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1013, p. 4
`
`

`

`Patent Application Publication Nov. 10, 2005 Sheet 4 of 6
`
`US 2005/0249011 A1
`
`FIG. 3
`
`15
`Vcc ) Vbat
`
`
`
`MEMORY
`CONTROLLER
`
`RambackUp
`Vbatt
`
`
`
`POWER
`CONTROLLER
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1013, p. 5
`
`

`

`Patent Application Publication Nov. 10, 2005 Sheet 5 of 6
`
`US 2005/0249011 A1
`
`FIG. 4A | FIG. 4B
`
`§§up
`-
`Clk:-------------------------------------------------------
`Resell:-----------------------------4--------------4-----
`Rambackup -------------4-------------4---4------4---4-----
`ClkE ---4-----------------------------------------4-----
`Cal:---4----------4--------------4---4----------4-----
`Rasl;---4-------------------------4---4----------4-----
`Cas L ----------------------------------4------------------
`
`FIG. 4B
`
`POWER
`;
`;
`;
`;
`;
`;
`;
`;
`;
`;
`;
`;
`;
`;
`?º ?º-º-º-º-º-º-º-º-º-j-i
`MEMORY
`!--------------4--------------4----------4---4-----
`;
`;
`113 ºf T4
`115;
`;
`;
`BACKUP clº?u Fu Fu Fu Fu Fu Fu Fu Fu ||--|--|--|
`
`pal-Hº ; ;
`;.
`RamBackup
`;
`;
`; ? TT | ;
`:
`ClkE TV || :
`;
`;
`;
`*TTTTTHTTH fºr
`*L-Fi jºini
`Casli TTTTTLTT|| tº
`Wel?—H ------
`:
`;
`;
`;
`; Seli Reiesh Command ||
`| OFF
`POWER
`WCC ;
`;
`;
`;
`;
`;
`;
`(#. ). —————————h|--|--4----------|--
`compoutfiji–fºr-4---
`POWER (SDRAM) ci-Fi-Ft. I
`º & yº ––––
`#5W:##5%ion
`POWERDOWN
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1013, p. 6
`
`

`

`Patent Application Publication Nov. 10, 2005 Sheet 6 of 6
`
`US 2005/0249011 A1
`
`FIG. 4B
`
`POWER-UP
`T10
`
`-
`
`T11
`
`T12
`
`£ANCEL QF.RESET.L
`|Rambackup "Low"
`
`|
`
`CANCEL OF RESET.L
`|Rambackup "High"
`
`
`
`
`
`
`
`|
`
`|
`
`|
`
`|
`
`?s=FREFRESHWops
`
`|
`
`|
`
`|
`
`|
`
`|
`
`;
`
`|
`
`;
`
`;
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1013, p. 7
`
`

`

`US 2005/0249011 A1
`
`Nov. 10, 2005
`
`MEMORY CONTROL DEVICE HAVING LESS
`POWER CONSUMPTION FOR BACKUP
`
`BACKGROUND OF THE INVENTION
`[0001] 1. Field of the Invention
`[0002] The present invention relates to a memory control
`device having a memory controller for controlling an opera
`tion of DRAM such as a synchronous dynamic random
`access memory (SDRAM) and a power controller for con
`trolling a power supply for the memory.
`[0003] 2. Related Background Art
`[0004] In the past, regarding electronic circuits of a com
`puter, in a system in which an SDRAM must be battery
`backed up if supplying power from exterior is interrupted,
`for example, upon power stoppage, the following procedures
`have been adopted:
`[0005] (1) During the power stoppage, power is sup
`plied from a battery to a memory controller itself so
`as to continue to control an interface to the SDRAM
`to be backed up; or
`[0006] (2) If the supplying power to the memory
`controller itself is stopped, a control signal between
`the memory controller and the SDRAM is switched
`by a switch, and a controller other than the memory
`controller controls the SDRAM to be backed up.
`However, in the above conventional procedure (1),
`since the battery power is consumed by the memory
`controller itself, as well as the SDRAM to be backed
`up, there was a disadvantage that a back-up sustain
`ing time is short. Particularly, in a case where the
`memory controller is incorporated into a large scale
`application specific integrated circuit (ASIC), since
`the battery power is supplied to the entire ASIC, the
`back-up sustaining time is further shortened.
`[0007] On the other hand, in the conventional procedure
`(2), since the power to the memory controller is stopped,
`although the disadvantage encountered in the procedure (1)
`can be eliminated, since an additional circuit such as the
`switch must be provided between the memory controller and
`the SDRAM, delay in the control signal is caused, with the
`result that it is very hard to increase operating frequency of
`the SDRAM. Incidentally, of course, this problem is also
`encountered in a DRAM, as well as the SDRAM.
`
`SUMMARY OF THE INVENTION
`[0008] An object of the present invention is to provide a
`memory control device in which supplying of power to a
`memory controller is stopped upon battery back-up of a
`DRAM to reduce power consumption without providing an
`additional circuit such as a switch between the memory
`controller and the DRAM, thereby permitting operating
`frequency to be increased.
`[0009] According to one aspect, the present invention
`which achieves the above object relates to a memory control
`device comprising a memory controller for controlling an
`operation of a DRAM and for outputting a clock enable
`signal to the DRAM, a power controller for controlling
`supplying of power to the DRAM from a main power supply
`or a back-up battery power supply and for detecting power
`stoppage of the main power supply, and pull-down resis
`
`tance for pulling down the clock enable signal to a low level,
`and wherein, if the power controller detects the power
`stoppage of the main power supply during a normal opera
`tion, the power controller switches a power supply for the
`DRAM from the main power supply to the battery power
`supply and instructs a self-refresh mode to the memory
`controller, so that the memory controller changes the clock
`enable signal for the DRAM to the low level to establish the
`self-refresh mode of the DRAM, and, after the DRAM is set
`to the self-refresh mode, the supplying of power to the
`memory controller is stopped, and, even after the stoppage,
`the clock enable signal is maintained to the low level by the
`pull-down resistance, thereby maintaining the self-refresh
`mode.
`[0010] Other objects and advantages besides that dis
`cussed above shall be apparent to those skilled in the art
`from the description of a preferred embodiment of the
`invention which follows. In the description, reference is
`made to accompanying drawings, which form a part thereof,
`and which illustrate an example of the invention. Such
`example, however, is not exhaustive of the various embodi
`ments of the invention, and therefore reference is made to
`claims which follow the description for determining the
`scope of the invention.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`[0011] FIG. 1 is a block diagram showing a construction
`of a memory control device according to a first embodiment
`of the present invention;
`[0012] FIG. 2 is comprised of FIGS. 2A and 2B illus
`trating timing charts showing signals for explaining an
`operation of the first embodiment;
`[0013] FIG. 3 is a block diagram showing a construction
`of a memory control device according to a second embodi
`ment of the present invention; and
`[0014] FIG. 4 is comprised of FIGS. 4A and 4B illus
`trating timing charts showing signals for explaining an
`operation of the second embodiment.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`[0015] The present invention will now be fully explained
`in connection with preferred embodiments thereof with
`reference to the accompanying drawings.
`
`First Embodiment
`[0016] Now, a first embodiment of the present invention
`will be explained with reference to FIGS. 1, 2A and 2B.
`FIG. 1 shows a construction of a memory control device
`according to the first embodiment. The memory control
`device includes a memory controller 11 and a power con
`troller 13 for a DRAM 12.
`[0017] In FIG. 1, the memory controller 11 serves to
`control an operation of a memory (SDRAM 12). The
`SDRAM 12 is a memory to be controlled. The power
`controller 13 serves to monitor and control a main power
`supply Vcc for the memory controller 11 and a battery power
`supply Vbatt for the SDRAM 12. A switch 14 serves to
`switch a power supply to the memory controller 11 to either
`the main power supply Vcc or the battery power supply
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1013, p. 8
`
`

`

`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1013, p. 9
`
`

`

`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1013, p. 10
`
`

`

`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1013, p. 11
`
`