(12) United States Patent
`Klein
`
`111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US006721860B2
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6, 721,860 B2
`Apr. 13, 2004
`
`(54) METHOD FOR BUS CAPACITANCE
`REDUCTION
`
`(75)
`
`Inventor: Dean A. Klein, Eagle, ID (US)
`
`(73) Assignee: Micron Technology, Inc., Boise, ID
`(US)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 199 days.
`
`(21) Appl. No.: 09/782,476
`
`(22) Filed:
`
`Feb. 13,2001
`
`(65)
`
`Prior Publication Data
`
`US 2001/0008006 A1 Jul. 12, 2001
`
`Related U.S. Application Data
`
`( 63) Continuation of application No. 09/015,376, filed on Jan. 29,
`1998, now abandoned.
`Int. Cl? ................................................ G06F 12/00
`(51)
`(52) U.S. Cl. ............................... 711/154; 711!1; 711!5;
`711!105; 711!202; 365/63; 365/189.01;
`365/230.03
`(58) Field of Search .............................. 365/63, 189.01,
`365/230.03; 710/4; 711/1, 5, 105, 202,
`154
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5/1991 Akimoto et a!. .............. 365/63
`5,014,242 A
`5,046,050 A * 9/1991 Kertis ......................... 327/51
`5/1992 Sato eta!. ............. 365/230.09
`5,115,413 A
`9/1992 Spohrer ....................... 326/86
`5,148,047 A
`5,260,892 A
`11/1993 Testa ........................... 365/63
`5,319,595 A
`6/1994 Saruwatari ............. 365/189.01
`10/1994 Kikuda eta!. ......... 365/230.03
`5,357,478 A
`11/1995 Bechtolsheim et a!. ....... 365!52
`5,465,229 A
`3/1996 Hatta .................... 365/230.03
`5,499,215 A
`12/1996 Miyamoto et a!. .......... 365/203
`5,586,076 A
`3/1998 Sanaga eta!. ......... 365/230.06
`5,732,042 A
`9/1998 Connolly et a!. .............. 710/4
`5,802,395 A
`7/1999 Sato eta!. .................. 365/201
`5,930,187 A
`5,953,215 A
`9/1999 Karabatsos ................. 361!767
`11/1999 Ushida .......................... 714/6
`5,987,623 A
`6,002,632 A
`12/1999 Krueger ................. 365/230.03
`6,011,710 A * 1!2000 Wiggers ...................... 365/63
`
`* cited by examiner
`
`Primary Examiner-Than Nguyen
`(74) Attorney, Agent, or Firm---Knobbe, Martens, Olson &
`Bear, LLP
`
`(57)
`
`ABSTRACT
`
`Data bus capacitance is reduced by decoupling unaccessed
`memory circuits from a data bus during data transfers to or
`from other memory circuits.
`
`4,757,215 A
`
`7/1988 Seo ............................ 307/425
`
`14 Claims, 6 Drawing Sheets
`
`!CJ
`
`SWITCH
`OFF
`
`!f
`
`YES
`
`NO
`
`!2
`
`SWITCH
`ON
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1009, p. 1
`
`

`

`U.S. Patent
`
`Apr. 13, 2004
`
`Sheet 1 of 6
`
`US 6, 721,860 B2
`
`!0
`
`SWITCH
`OFF
`
`11
`
`YES
`
`NO
`
`!2
`
`SWITCH
`ON
`
`NO
`
`!8
`
`TE
`F/0, 2
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1009, p. 2
`
`

`

`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1009, p. 3
`
`

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`
`33
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1009, p. 4
`
`

`

`U.S. Patent
`
`Apr. 13, 2004
`
`Sheet 4 of 6
`
`US 6, 721,860 B2
`
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`54
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`DATA
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`FIG, 5
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1009, p. 5
`
`

`

`U.S. Patent
`
`Apr. 13, 2004
`
`Sheet 5 of 6
`
`US 6, 721,860 B2
`
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`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1009, p. 6
`
`

`

`U.S. Patent
`
`Apr. 13, 2004
`
`Sheet 6 of 6
`
`US 6, 721,860 B2
`
`96'
`
`MEMORY
`ARRAY
`
`102
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`88
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`FIG, 10
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1009, p. 7
`
`

`

`US 6,721,860 B2
`
`1
`METHOD FOR BUS CAPACITANCE
`REDUCTION
`
`2
`or more memory banks. The method may comprise the act
`of decoupling a selected one of the memory banks from the
`bus when no memory access to or from the selected memory
`bank is being performed.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`RELATED APPLICATIONS
`This application is a continuation and claims priority to 5
`and incorporates by reference, in its entirety, U.S. applica(cid:173)
`tion Ser. No. 09/015,376, titled "Method for Bus Capaci(cid:173)
`tance Reduction", filed Jan. 29, 1998, now abandoned. This
`application also relates to U.S. application Ser. No. 09/015,
`845, titled "High Speed Data Bus", filed Jan. 29, 1998.
`
`10
`
`BACKGROUND OF THE INVENTION
`
`FIG. 1 is a flow chart showing one mode of operation of
`a computing system which incorporates the invention.
`FIG. 2 is a schematic diagram of one embodiment of a
`switch which may be used in systems which incorporate the
`invention.
`FIG. 3 is a block diagram of a computing system incor(cid:173)
`porating an embodiment of the invention.
`FIG. 4 is a block diagram of a computing system incor(cid:173)
`porating another embodiment of the invention.
`FIG. 5 is a block diagram of one embodiment of a
`memory subsystem incorporating the present invention.
`FIG. 6 is a block diagram of another embodiment of a
`20 memory subsystem incorporating the present invention.
`FIG. 7 is an illustration of one embodiment of a memory
`cycle decoder for controlling a transfer gate.
`FIG. 8 is an illustration of another embodiment of a
`25 memory cycle decoder for controlling a transfer gate.
`FIG. 9 is an illustration of a third embodiment of a
`memory cycle decoder for controlling a transfer gate.
`FIG. 10 is a block diagram of one embodiment of a
`memory integrated circuit incorporating the present inven-
`30 tion.
`
`1. Field of the Invention
`The invention relates generally to the field of computing 15
`systems. More specifically, the invention relates to creating
`a high speed data bus between a processor circuit and a
`memory array.
`2. Description of the Related Art
`Computing and data processing systems typically include
`a microprocessor which processes data that it retrieves from
`a memory circuit. The results of the processing operation are
`in turn stored back in the memory circuit. The rate at which
`the microprocessor can perform accesses to the memory to
`retrieve operands and store results may therefore create a
`limitation on the speed at which the computing system can
`perform the tasks it has been programmed to perform.
`Several factors are significant in determining the speed at
`which memory accesses can be performed. There is, for
`example, an inherent delay between the presentation of row
`and column addresses to the memory circuit and the time at
`which the requested data appears at the output of the
`memory circuit. In many systems, this problem is reduced
`by the practice of using a small amount of fast access but
`expensive memory as a cache for frequently used data. Main
`data storage remains comprised of a large amount of slower,
`less expensive memory.
`Another source of delay is the speed at which signals
`representative of digital data can be placed on the data bus 40
`which couples the microprocessor to the memory circuit.
`The speed of this data transfer is affected by the parasitic
`capacitance between each bus line and ground or other low
`impedance signal. This is because the device which is
`transferring data by driving the lines of the bus high or low 45
`must charge or discharge this parasitic capacitance with each
`transition, and the time required to accomplish this increases
`with increasing parasitic capacitance.
`This affect has long been recognized and several different
`ways of addressing it have been developed. In U.S. Pat. No. 50
`5,148,047 to Spohrer, for example, a higher speed bus driver
`circuit is described which adds a minimal amount of stray
`capacitance to the bus line. In the specific case of a data bus
`between a microprocessor and memory, U.S. Pat. Nos.
`5,465,229 and 5,260,892 suggest careful routing of data bus 55
`traces to minimize bus line capacitance and loading.
`In each of these cases, however, the benefits are limited.
`Altering the driver circuit does not alter the inherent capaci(cid:173)
`tance of the bus lines themselves. Altering bus line routing,
`although helpful, still leaves bus lines with significant para- 60
`sitic capacitance. Furthermore, neither of these methods
`addresses the fact that the bus is loaded with the input
`capacitance of the memory circuits themselves.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`35
`
`Embodiments of the invention will now be described with
`reference to the accompanying Figures, wherein like numer(cid:173)
`als refer to like elements throughout.
`FIG. 1 is an illustration of one operational mode of a
`system made in accordance with the invention. In this
`system, one or more switches are associated with memory
`elements of a computing system. Selective operation of
`these switches reduces parasitic capacitance of a data bus,
`and thereby allows increases in the speed data transfer. Thus,
`operation of a system comprising one or more memory
`elements may begin at block 10, with a switch associated
`with a memory element initially in the off state. In this state,
`the memory element is decoupled from at least one of the
`buses connecting it to the system processor. As represented
`by block 11, the computing system monitors whether or not
`the memory element is being accessed by the host system.
`If not, the system loops back to block 10, and leaves the
`switch in the off state. If a memory element access is being
`made, the system moves instead to block 12, at which point
`the switch is placed in the on state, thereby connecting the
`memory element to the portion of the bus it was isolated
`from.
`As illustrated by block 13, once the switch is on, the
`system monitors whether or not the memory access has been
`completed. If not, the system continues to leave the switch
`in the on state. Once the memory access cycle has
`completed, the system loops back to block 10, and places the
`switch in the off state. Thus, the system decouples a memory
`element from a bus when no memory access to or from the
`selected memory element is being performed. It will be
`65 appreciated by those of skill in the art that the switch need
`not necessarily remain in the on state for the entire duration
`of any given memory access cycle. It will typically be
`
`SUMMARY OF THE INVENTION
`The invention includes a method of reducing the parasitic
`capacitance of a bus provided between a processor and one
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1009, p. 8
`
`

`

`US 6,721,860 B2
`
`3
`sufficient to open the switch only during a portion of the
`memory cycle corresponding to the time during which valid
`information should be present on the bus which is routed
`through the switch.
`When the memory element is provided on a segment of a
`data bus which may be decoupled from other data bus
`segments, this may have the beneficial aspect of reducing the
`parasitic capacitance of the remainder of the data bus
`because the particular bus segment and its associated
`memory element no longer load the remainder of the data
`bus. In common computer applications, the memory element
`may be a DRAM memory module. As there are often two,
`four or perhaps eight memory modules provided, the above
`described system may decouple all but one of these modules
`during any given memory access, thereby significantly lim(cid:173)
`iting the capacitive loading on the bus connecting a memory
`controller to a memory module being accessed.
`Referring now to FIG. 2, the configuration of one embodi(cid:173)
`ment of a bus switch is illustrated which may be used in a
`system implementing the mode of operation described above
`with reference to FIG. 1. In this embodiment, the bus switch
`14 comprises one or more n-channel MOSFET transistors
`with commonly connected gates 15. The switch of FIG. 2
`further includes an input portion 16 and an output portion
`17, comprising one or more contacts for connection to
`corresponding one or more lines of a bus 18. It can be
`appreciated, however, that which side of the switch is
`considered the "input" and which side is considered the
`"output" is arbitrary, as data transmission can occur in either
`direction when the switch is in the on state.
`In this switch embodiment, the source 19 of each tran(cid:173)
`sistor may be coupled to a corresponding bus line of one
`segment of the bus 18. The drain 27 of each transistor may
`be coupled to a corresponding bus line of another segment
`of the bus 18. The switch 14 therefore decouples or isolates
`the bus segments when the transistors comprising the switch
`are in the off state, and couples or connects the bus segments
`when the transistors comprising the switch are in the on
`state. The transistors are turned on by asserting the gates 15
`via an input "transfer enable" signal line labeled TE in FIG.
`2. Bus switch circuits such as that illustrated in FIG. 2 are
`known to those of skill in the art. Integrated circuit embodi(cid:173)
`ments of such switches are available from, for example,
`Quality Semiconductor of Santa Clara, Calif., identified as
`their part numbers QS3384 and QS32384.
`FIG. 3 illustrates one embodiment of a computing system
`incorporating the invention. As shown in this Figure, the
`system includes a host processor 20 which in one embodi(cid:173)
`ment of the invention comprises a microprocessor such as 50
`the X86 or Pentium(TM) families from Intel Corporation.
`Any digital data processing circuitry may, however, com(cid:173)
`prise the host processor 20 of FIG. 3, including digital signal
`processors, microcontrollers, multi-processor systems, etc.
`The host processor 20 may interface with a memory con- 55
`troller 22. The memory controller interface circuitry
`includes a data bus 24 for the transfer of digital data between
`the memory controller 22 and the host processor 20. Addi(cid:173)
`tional circuitry including control and address buses also
`connect between the host processor 20 and memory con- 60
`troller 22, but these are not illustrated in FIG. 3.
`The memory controller 22 connects to circuitry 26 for
`interfacing with one or more memory circuits 28, two of
`which are illustrated in FIG. 3. This interface circuitry 26
`also includes a data bus 30a-d for the transfer of data
`between the memory circuits 28 and the memory controller
`22. As illustrated in FIG. 3, the data bus between the
`
`4
`memory controller 22 and memory elements 28 may com(cid:173)
`prise several branches 30a, 30b, one for each of the separate
`memory elements 28. Each branch may include a switch
`32a, 32b that, as will be explained in detail below, may be
`5 used to selectively isolate portions or segments 30c, 30d of
`the data bus running from the memory controller to the
`memory circuitry 28. It can be appreciated that by turning
`the switches 32a and 32b on or off, one or the other memory
`circuit 28 may be removed from the data bus. For example,
`10 when the host processor requires data in the memory circuit
`28 connected to bus segment 30c, switch 32a may be
`switched on, while switch 32b may be switched off. Thus,
`the design of FIG. 3 may reduce the parasitic capacitance
`that the memory controller needs to charge and discharge
`15 during data transfers because a portion of the data bus and
`the stray capacitance of unaccessed memory circuits are
`removed.
`It will also be appreciated that although the host processor
`20, memory controller 22, bus switches 32a and 32b, and
`20 memory 28 are illustrated as separate circuit blocks, various
`combinations could be placed on a single integrated circuit
`(IC). In one embodiment applicable to current personal
`computer designs, the host processor and memory controller
`are secured to a motherboard as separate integrated circuits.
`25 The memory circuit may be a conventional dynamic random
`access memory (DRAM) integrated circuit (I C). The DRAM
`IC may be part of a memory module 34 which also incor(cid:173)
`porates a separate IC forming the bus switch. The memory
`module may be a standard SIMM or DIMM style as are well
`30 known in the art, wherein the DRAM and bus switch are
`soldered to a printed circuit board which also includes
`contacts for interfacing with a mating motherboard connec(cid:173)
`tor. In other embodiments, the switch is incorporated into the
`DRAM IC. In addition, the memory controller may be part
`35 of the host processor I C. It is also contemplated that all of
`the circuitry shown in FIG. 3 may be placed on a single IC,
`or may be provided in a multi-chip package. In another
`advantageous embodiment illustrated in FIG. 4, a host
`processor 21 interfaces with a memory controller 23 via a
`40 bus 25 in a manner analagous to that shown and described
`with reference to FIG. 3. Memory elements 29 are also
`provided in this system. In one common application, the host
`processor 21 and memory controller 23 are separate inte(cid:173)
`grated circuits mounted on a personal computer mother-
`45 board along with a plurality of conventional DIMM or
`SIMM style DRAM memory modules 35 with DRAM
`memory integrated circuits 29 mounted thereon. Also pro(cid:173)
`vided in the embodiment of FIG. 4 is a bus switch 27 which
`splits a single input data bus 31a from the memory controller
`into a plurality of output data buses 31c, 31d, 31e, 31fwhich
`are routed to the respective memory modules 35. It can thus
`be appreciated that in the FIG. 4 embodiment, the switch 27
`includes the interface circuitry 26 illustrated in FIG. 3. In the
`personal computer motherboard environment referred to
`above, the bus switch 27 may comprise another separate
`integrated circuit mounted to the motherboard. This inte-
`grated circuit may, for example, comprise a plurality of the
`switches illustrated in FIG. 2. In this embodiment, the input
`side 17 of each of the four would be commonly connected
`to the input data bus 31a, and the output sides 16 would each
`be separately routed to one of the output data buses 31c, 31d,
`31e, and 31f. Therefore, selectively asserting the corre(cid:173)
`sponding four TE signal inputs would selectively couple the
`input data bus 31a to one of the output buses 31c, 31d, 31e,
`65 or 31f
`As shown in FIG. 4, the memory controller 23 may
`include a control output 37 which controls the bus switch 27
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1009, p. 9
`
`

`

`10
`
`15
`
`20
`
`25
`
`US 6,721,860 B2
`
`5
`
`5
`so as to connect the input data bus 31a to one of the output
`buses 31c, 31d, 31e, and 31/ while the remaining three
`output buses remain disconnected from the input bus. It can
`be appreciated that during memory accesses, the memory
`controller 23 will therefore only need to drive one bus and
`memory module rather than all of them during each memory
`access as is the current state of the art.
`Because given computer systems may have different
`numbers of memory modules installed, it is convenient to
`design a memory controller which is easily configurable to
`handle alternative system memory sizes. In one
`embodiment, therefore, the control bus is two bits wide, and
`the memory controller is configurable to output an encoded
`four state output signal (i.e. 00, 01, 10, or 11) for selecting
`one of four banks, or a decoded two state signal (i.e. 01 or
`10) for selecting between two memory banks. In the first
`case, the switch 27 may include four switches and a demul(cid:173)
`tiplexer for selecting one of the TE signal inputs to assert
`based on the value of the received four state control signal.
`In the second case, the switch 27 may include only two
`switches, wherein the TE control inputs of the switch are
`driven directly with the respective lines of the two state
`output. The same core memory controller logic circuit can
`thus be configured for use in both large and small systems.
`Of course, it will be appreciated that the control output 37
`may comprise an encoded or decoded signal of more than
`two output lines. The number of control output signals
`required may be determined by the number of separate
`memory elements in a given computer system.
`It will also be appreciated that the switch and switch
`control circuitry of the present invention may be provided on
`a memory module itself, rather than on a motherboard. Thus,
`FIG. 5 illustrates one embodiment of a DRAM memory
`module 60 manufactured in accordance with the invention.
`The memory module 60 includes one or more memory
`elements 62, each of which may comprise a memory inte(cid:173)
`grated circuit, which is mounted on a printed circuit board
`(not illustrated). Also mounted on the printed circuit board
`is a set of transfer gates 64, which may be constructed as
`illustrated in FIG. 2. As in conventional in memory modules,
`the module 60 includes electrical contacts for connection to
`an address bus 66, control lines 68, and a data bus 70. The
`control signals 68 may include a row address strobe (RAS),
`column address strobe (CAS) and write enable (WE) famil(cid:173)
`iar to those in the art, for example.
`The data input electrical contacts of the memory module
`are connected by the data bus 70 to inputs on the transfer
`gates 64. Outputs of the transfer gates 64 are connected to
`the memory elements 62. As explained above with reference
`to FIGS. 1 and 2, the transfer gates are a type of bus switch
`in the data bus 70. The transfer gates 64 may remain closed
`when the memory module is not being accessed by the host
`processor, and may be opened when a memory access is
`being performed.
`Referring again to FIG. 5, a gate control signal 72 may
`also be routed to another electrical contact on the memory
`module 60 from logic circuitry which is external to the
`module 60. This gate control signal 72 may be asserted
`whenever data is to be written to or read from the module 60. 60
`In systems with several modules, a different gate control
`signal will be routed to each module to selectively open the
`appropriate transfer gate for memory accesses from the
`various memory modules of the system.
`FIG. 6 illustrates another embodiment of a memory
`module incorporating the invention. In analogy with the
`embodiment of FIG. 5, The memory module 76 of FIG. 6
`
`6
`also includes memory elements 62, a set of transfer gates 64,
`and electrical contacts to interface with an address bus 66,
`control lines 68, and a data bus 70. In the embodiment of
`FIG. 6, however, the gate control signal 72 is not routed
`from external logic circuitry to an additional electrical
`contact on the module. Instead, a state decoder 78 is pro(cid:173)
`vided on the module 76. The state decoder may comprise a
`programmable logic device, for example. As inp.uts, the st~te
`decoder 78 receives one or more of the control signals which
`are received from the host system. The state decoder 78 has
`the gate control signal 72 as an output. The state decoder 78
`decodes the signals on the control lines to determine whether
`or not a memory access to or from the module is being made,
`and asserts the gate control signal 72 to open the transfer
`gates 64 when a memory access is being made. This
`embodiment has the advantage that no unconventional sig(cid:173)
`nal line for gate control needs to be created and routed to the
`memory module. Thus, a memory module as shown in FIG.
`6 could be placed in existing, conventional memory appli(cid:173)
`cations such as personal computer applications without any
`modification of a DRAM to memory controller interface.
`Specific implementations of decoders for creating the
`necessary TE control signals are illustrated in FIGS. 7, 8,
`and 9. Referring now to FIG. 7, a state decoder 78 could
`comprise an inverter 80 which has as an input a chip select
`signal 82 which is asserted low. In this embodiment, the
`transfer gates 64 would be as shown in FIG. 2, and would be
`in the on state when the output of the inverter went high.
`This may be appropriate when applying the invention to
`30 synchronous-DRAM memory modules, where a chip select
`signal is commonly used.
`Referring now to FIG. 8, more complicated state decoders
`may be desireable where the chip select input to the module
`is always asserted, and therefore the other memory control
`35 signals must be used to determine the status of memory
`access. In this case, the state decoder 78 could comprise a
`state machine 84 made with a programmable gate array for
`example. The state machine 84 would have inputs compris(cid:173)
`ing RAS, CAS, and WE. As is known, there may be several
`40 of each of these signals, depending on the architecture of the
`memory module. The state machine 84 will determine the
`status of memory accesses, and appropriately assert the gate
`control signal 72 when data transfer is to occur.
`FIG. 9 illustrates another decoder embodiment which may
`45 advantageously be used when the decoder is part of a
`memory controller as illustrated in FIG. 4. In this case, the
`address to be accessed selected by the host processor will
`identify which memory module 35 is to be accessed. In this
`decoder embodiment, selected bits of the address to be
`50 accessed are sent on a bus 87 to a decode circuit 86. The
`decode circuit 86 then selectively asserts the appropriate TE
`signal in response to the address bits on output lines 72a,
`72b, 72c, and 72d. Although illustrated as four decoded
`outputs in FIG. 9, one of skill in the art will readily be able
`55 to decode the memory access addresses to produce the
`encoded two bit signal described above with regard to FIG.
`4, or to produce other configurations of encoded or decoded
`outputs depending the desired application and bus switch
`configuration.
`It may also be noted that bus switch and associated control
`circuitry may alternatively be incorporated into a memory
`integrated circuit. One embodiment of this is illustrated in
`FIG. 10. The memory integrated circuit 88 of FIG. 10
`includes input terminals for the address bus 66 and data bus
`65 70. Also, control lines 68 are connected to control logic
`circuitry 90 on the chip. As in conventional memory inte(cid:173)
`grated circuits, the row and column addresses are input to a
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1009, p. 10
`
`

`

`US 6,721,860 B2
`
`7
`row latch 92 and column latch 94 respectively. These
`addresses are presented to a memory array 96 via a row
`decoder 98 and a column decoder 100. Sense amplifiers and
`gating circuitry 102 route data into and out of the memory
`array. This data is routed through input and output buffers 5
`104 provided between the memory array 96, and the data bus
`terminals of the memory integrated circuit 88.
`In this embodiment of the invention, a transfer gate input
`is connected to the data bus contacts on the integrated circuit
`88, and a transfer gate output is connected to data buffer
`registers. The control logic 90 can be made to additionally
`include the state decoder circuitry 78 described above with
`reference to FIG. 6. Thus, the transfer gate 64 is off when no
`memory access is occurring, and is on when data is being
`transferred between the integrated circuit 88 and the host
`system.
`The invention may be embodied in other specific forms
`without departing from its spirit or essential characteristics.
`The described embodiment is to be considered in all respects
`only as illustrative an not restrictive and the scope of the 20
`invention is, therefore, indicated by the appended claims
`rather than by the foregoing descriptions. All charges which
`come within the meaning and range of equivalency of the
`claims are to be embraced within their scope.
`What is claimed is:
`1. A method of reducing the parasitic capacitance of a bus
`provided between a processor and one or more memory
`banks comprising:
`receiving a chip select signal targeted for at least one of 30
`the memory banks; and
`decoupling at least a selected one of said one or more
`memory banks from said bus when no memory access
`to or from said selected memory bank is being per(cid:173)
`formed by said processor, wherein decoupling com- 35
`prises decoupling a bus switch, and wherein the tar(cid:173)
`geted bank is selectively decoupled from the bus in
`response to a change in state in the chip select signal.
`2. The method of claim 1, wherein said act of decoupling
`said selected memory bank comprises opening a transfer 40
`gate in each line of said bus.
`3. The method of claim 1, wherein the switch is located
`within at least one of the memory banks.
`4. The method of claim 1, wherein the memory bank
`comprises synchronous DRAM.
`5. The method of claim 1, wherein the memory bank, a
`memory controller for the memory bank, and the bus switch
`reside within a single integrated circuit.
`
`25
`
`10
`
`8
`6. A method of data transfer across a bus comprising:
`receiving a chip select signal targeted for a memory
`circuit; and
`decoupling a bus switch, and wherein the memory circuit
`is selectively decoupled from the bus in response to a
`change in state in the chip select signal, thereby reduc(cid:173)
`ing the parasitic capacitance of said bus.
`7. The method of claim 6, wherein the switch is located
`within at least one of the memory circuits.
`8. The method of claim 6, wherein the memory circuit
`comprises synchronous DRAM.
`9. The method of claim 6, wherein the memory circuit, a
`memory controller for the memory circuit, and the bus
`15 switch reside within a single integrated circuit.
`10. A method of data transfer between a microprocessor
`and a plurality of memory banks, said microprocessor and
`said plurality of memory banks being coupled by a data bus,
`said method comprising the acts of:
`receiving a chip select signal targeted for at lease one of
`the memory banks;
`reducing the parasitic capacitance of said data bus by
`isolating at least a first segment of said bus which
`connects to a first one of said memory banks, wherein
`isolating comprises switching a bus switch and wherein
`the first segment of said bus is isolated from the rest of
`the bus in response to a change in state in the chip select
`signal; and
`transferring data to or from a second one of said memory
`banks.
`11. The method of claim 10, additionally comprising the
`acts of:
`reintegrating said first segment of said bus with the
`remainder of said bus;
`isolating a second segment of said bus which connects to
`said second one of said memory banks; and
`transferring data to or from said first one of said memory
`banks.
`12. The method of claim 10, wherein the switch is located
`within at least one of first and second memory banks.
`13. The method of claim 10, wherein the memory bank
`comprise synchronous DRAM.
`14. The method of claim 10, wherein the memory bank,
`45 a memory controller for the memory bank, and the bus
`switch reside within a single integrated circuit.
`
`* * * * *
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1009, p. 11
`
`