(19) United States
`(2) Patent Application Publication (10) Pub. No.: US 2007/0136523 A1
`(43) Pub. Date:
`Jun. 14, 2007
`Bonella et al.
`
`US 20070136523A1
`
`(54) ADVANCED DYNAMIC DISK MEMORY
`MODULE SPECIAL OPERATIONS
`
`(76)
`
`Inventors: Randy M. Bonella, Portland, OR (US);
`Chung W. Lam, Hillsborough, CA
`(US)
`Correspondence Address:
`RAYMOND J. WERNER
`2056 NW ALOCLEK DRIVE, SUITE 314
`HILLSBORO, OR 97.124 (US)
`
`(21)
`
`Appl. No.:
`
`11/635,926
`
`(22)
`
`Filed:
`
`Dec. 8, 2006
`
`Related U.S. Application Data
`
`(60)
`
`Provisional application No. 60/749,267, filed on Dec.
`8, 2005.
`
`
`
`CPU Cache
`L1
`L2
`L3
`
`Main Memory
`DRAM
`
`Publication Classification
`
`(51) Int. Cl.
`(2006.01)
`G06F H3/00
`(52) U.S. Cl. … 711/113
`
`(57)
`
`ABSTRACT
`
`A memory module including a volatile memory, a non
`volatile memory, and a controller that provides address, data,
`and control interfaces to the memories and to a host system,
`such as, for example, a personal computer, is operable to
`interact with the host system so as to provide one or more
`additional layers in the memory hierarchy of the host
`system. In one aspect of the present invention the controller
`operates the volatile memory of the memory module as a
`cache for the non-volatile memory of the memory module.
`In another aspect of the present invention data representing
`one or more software applications and/or one or more data
`sets are stored in the non-volatile memory of the memory
`module along with security information such that a host
`system may quickly launch applications from the memory
`module rather than from a slower hard disk drive.
`
`Highest Performance
`Lowest Capacity
`
`Hard Disk Drive
`
`FLASH
`Write Buffer
`
`Hard Drive Disk
`Media
`
`Lowest Performance
`Highest Capacity
`
`Memory Performance Hierarchy
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1005, p. 1
`
`

`

`Patent Application Publication Jun. 14, 2007 Sheet 1 of 9
`
`US 2007/0136523 A1
`
`MM Controller
`
`DRAM
`Controller
`
`
`
`To
`§
`§
`(l)
`a.
`×
`LL]
`
`FLASH
`Controller
`
`C H2
`
`Töäänäß.
`: Batey UPS ?
`
`l
`
`Voltage Regulator
`Controller
`
`:
`| | | | | |||—º
`|| Batey || :
`|VR2|-vODe
`|
`VR3
`|
`| TF
`i Optional:
`!
`—VDDf
`[. : CAP UPS
`!
`VRX | VDDdr
`[]
`!
`l
`||Capacitor|* :
`|
`|
`!----------- |
`
`– 4 || +
`
`|
`
`1.5V,33V.
`3.3Vaux
`FIG. 1 Memory Module Block Diagram
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1005, p. 2
`
`

`

`Patent Application Publication Jun. 14, 2007 Sheet 2 of 9
`
`US 2007/0136523 A1
`
`Con?i?)
`SMBUS :=º ºr ºl
`SVCI)
`
`d
`
`-
`
`(RCr?
`
`+3
`
`§
`fy ##cle 1.0 (+) c.
`9.
`Lil
`
`Config
`
`e
`
`-
`
`ine
`
`|ECC / EDC
`
`ADDR
`(CNTRI)
`
`CLK
`
`DRAM
`Interface
`
`DRAM
`Controller
`
`–
`
`Tº
`
`System
`Aux
`
`(TEEENTRT)
`
`-
`ine
`
`eRLDat
`
`
`
`FLASH ADDR
`
`USB DATA
`*:4–
`USB 2.0
`| Hº-
`°º vsº T.TX
`Carole ( - USBGNIFIL)
`XI
`Config
`Y??– A?bitration
`Manager and
`IG) Control H
`
`
`
`
`
`
`
`
`
`FIG. 2 Memory Module Controller Block Diagram
`
`ECC / EDC
`Engine
`-
`WR Lvl
`Engine
`
`{GL}
`CH1
`FLASH
`Controller
`(Twº-)
`CH2
`(CME)
`
`FLASH
`Interface
`
`VRC1
`
`VRC2
`
`VRC2
`
`Voltage
`Regulator
`Controller
`Interface
`
`
`
`Voltage
`
`Controller
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1005, p. 3
`
`

`

`Patent Application Publication Jun. 14, 2007 Sheet 3 of 9
`
`US 2007/0136523 A1
`
`--
`Highest Performance
`Lowest Capacity
`
`CPU Cache
`L1
`L2
`L3
`
`Main Memory
`DRAM
`
`(2)
`
`
`
`Hard Disk Drive
`
`FLASH
`Write Buffer
`Hard Drive Disk ||
`Media
`
`||
`
`Lowest Performance
`Highest Capacity
`
`FIG. 3 Memory Performance Hierarchy
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1005, p. 4
`
`

`

`Patent Application Publication Jun. 14, 2007 Sheet 4 of 9
`
`US 2007/0136523 A1
`
`System Boot
`Manager
`9
`
`Power State
`Transition from D 0
`
`Power State
`T ition from D 0
`ranSItion from
`
`D2
`Transition to
`D0
`
`Power State
`Transition from D 0
`
`
`
`D3
`Transition to
`DO
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Transition to
`DO
`
`2"+ Boot
`W/ADDMM
`Flag ok
`
`Power State
`Transition from D 0
`
`2"+ Boot
`W/ADDMM
`St
`wº Flag ok
`
`
`
`
`
`Load
`Boot
`Boot Image
`from
`HDD \to ADDMM
`
`
`
`
`
`
`
`
`
`SET
`ADDMM
`Boot Flag
`For OS
`
`FIG. 4 System Boot Manager Flow Chart
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1005, p. 5
`
`

`

`Patent Application Publication Jun. 14, 2007 Sheet 5 of 9
`
`US 2007/0136523 A1
`
`POWER STATES
`
`Soft Off
`
`Switch Event
`
`
`
`
`
`Wake Event
`
`Switch Events
`
`FIG. 5 Memory Module Power State Diagram
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1005, p. 6
`
`

`

`Patent Application Publication Jun. 14, 2007 Sheet 6 of 9
`
`US 2007/0136523 A1
`
`
`
`
`
`
`
`
`
`
`
`
`
`MRU
`Manager
`
`Close Program
`Request
`
`Program
`Request
`
`DRAM
`Launch
`
`FIG. 6 MRU Manager Flow Chart
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1005, p. 7
`
`

`

`Patent Application Publication Jun. 14, 2007 Sheet 7 of 9
`
`US 2007/0136523 A1
`
`
`
`
`
`
`
`Launch Acceleration
`Manager
`
`Access Request
`MRU Image
`In DRAM
`
`Access Request
`MRU Image
`In Flash
`
`Flagged for
`FLASH only
`
`
`
`Do Not Load
`to DRAM
`- Low Priority
`- DRAM Full
`
`
`
`
`
`Ok for MRU
`Move to DRAM
`
`FIG. 7 Launch Acceleration Manager Flow Chart
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1005, p. 8
`
`

`

`Patent Application Publication Jun. 14, 2007 Sheet 8 of 9
`
`US 2007/0136523 A1
`
`
`
`
`
`
`
`
`
`
`
`Launch ACCeleration
`User Override
`Manager
`
`1*ACCESS
`Or
`New Program
`
`
`
`User Set
`Function
`
`Override
`MRU Control
`Pre-Set MRU
`
`FIG. 8 Launch Acceleration User Override Flow Chart
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1005, p. 9
`
`

`

`Patent Application Publication Jun. 14, 2007 Sheet 9 of 9
`
`US 2007/0136523 A1
`
`High Speed
`Medium Density
`Volatile Storage
`
`Low
`Speed
`High
`gr
`Density
`Non
`Volatile
`Storage
`
`READ
`
`System
`Interface
`
`Memory
`rface
`Inte
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Controller
`
`
`
`
`
`FIG. 9 (Prior Art)
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1005, p. 10
`
`

`

`US 2007/0136523 A1
`
`Jun. 14, 2007
`
`ADVANCED DYNAMIC DISK MEMORY MODULE
`SPECIAL OPERATIONS
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`[0001] This non-provisional application claims the benefit
`of earlier filed provisional application No. 60/749,267,
`entitled “Advanced Dynamic Disk Memory Module”, filed
`08 Dec. 2005; the entirety of which is hereby incorporated
`by reference.
`
`FIELD OF THE INVENTION
`[0002] The present invention relates generally to a plug
`and-play end-user add-in memory module for computers and
`consumer electronic devices, and more particularly relates to
`methods and apparatus for automatically managing active
`data sets in the memory module without external commands
`other than data set markers and for actively managing
`memory module maintenance operations independent of
`system control and in such a manner as to limit conflicts with
`normal memory module operations.
`
`BACKGROUND
`[0003] Advances in semiconductor manufacturing tech
`nology and digital systems architecture have provided the
`basis for the design, manufacture, and large-scale distribu
`tion of a wide variety of sophisticated consumer electronic
`devices and products. Many of these electronic products
`provide at least one connection, or interface, for use with one
`or more removable memory storage units, also referred to as
`removable memory modules.
`[0004] Removable memory modules have been used with
`personal computers (PC) for many years. Such removable
`memory modules, or storage media, are used for many
`applications. Historically, the primary use of removable
`memory modules has been for general data storage. More
`recently the use of removable memory modules for enter
`tainment or consumer applications including but not limited
`to audio, video and still pictures has become common.
`Conventionally, the type of storage device, or memory, used
`in such memory modules has been FLASH memory or hard
`disk drive mechanical storage media.
`[0005] What is needed are methods and apparatus for
`providing portable data storage with performance charac
`teristics between those of main memory and FLASH or hard
`disk drives, and which can be easily added and removed
`from a host system, and which can further be used to restore
`an image to main memory without resorting to loading data
`from a slower hard disk drive.
`
`SUMMARY OF THE INVENTION
`[0006] Briefly, a memory module including a volatile
`memory, a non-volatile memory, and a controller that pro
`vides address, data, and control interfaces to the memories
`and to a host system, such as, for example, a personal
`computer, is operable to interact with the host system so as
`to provide one or more additional layers in the memory
`hierarchy of the host system.
`[0007] In one aspect of the present invention the controller
`operates the volatile memory of the memory as a cache for
`the non-volatile memory of the memory module.
`
`[0008] In another aspect of the present invention data
`representing one or more software applications and/or one or
`more data sets are stored in the non-volatile memory of the
`memory module along with security information such that a
`host system may quickly launch applications from the
`memory module rather than from a slower hard disk drive.
`[0009] In a further aspect of the present invention, since
`the memory module is in a different and independent path
`from that of the primary storage device, while the host
`system is booting from the memory module it can begin and
`service other requests from the primary storage device
`concurrently with the restore sequence.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`[0010] FIG. 1 is a high level system block diagram of an
`illustrative memory module in accordance with the present
`invention.
`[0011] FIG. 2 is a high level block diagram of an illustra
`tive memory module controller, in accordance with the
`present invention, showing major functional blocks thereof.
`[0012] FIG. 3 relates to a memory performance hierarchy
`and is a diagram illustrating a four-tier memory hierarchy of
`a personal computer system incorporating a memory module
`in accordance with the present invention.
`[0013] FIG. 4 relates to a system boot manager and is a
`state transition diagram illustrating, in a personal computer,
`transitions from various mechanical power states to the
`possible states when a memory module in accordance with
`the present invention is incorporated in the personal com
`puter system.
`[0014] FIG. 5 is a power state transition diagram showing
`the state transitions occurring in an illustrative memory
`module controller in accordance with the present invention.
`[0015] FIG. 6 is a state transition diagram of an illustrative
`Most Recently Used Information Manager suitable for use in
`a memory module controller in accordance with the present
`invention.
`[0016] FIG. 7 is a state transition diagram of an illustrative
`Launch Acceleration Manager suitable for use in a memory
`module controller in accordance with the present invention.
`[0017] FIG. 8 is a state transition diagram of an illustrative
`Launch Acceleration User Override Manager suitable for
`use in a memory module controller in accordance with the
`present invention.
`[0018] FIG. 9 is a system block diagram of a conventional
`memory subsystem of a computer system.
`
`DETAILED DESCRIPTION
`[0019] Generally, a memory module with performance
`characteristics between those of main memory and non
`volatile memory is provided on a separate path and allows,
`among other things, fast application launching, and concur
`rent servicing of multiple threads involving, for example,
`accessing the hard disk drive concurrently with application
`launching from the memory module. These and other func
`tions and features of the memory module of the present
`invention are described in greater detail below.
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1005, p. 11
`
`

`

`US 2007/0136523 A1
`
`Jun. 14, 2007
`
`[0020] Reference herein to “one embodiment”, “an
`embodiment”, or similar formulations, means that a particu
`lar feature, structure, operation, or characteristic described
`in connection with the embodiment, is included in at least
`one embodiment of the present invention. Thus, the appear
`ances of such phrases or formulations herein are not neces
`sarily all referring to the same embodiment. Furthermore,
`various particular features, structures, operations, or char
`acteristics may be combined in any suitable manner in one
`or more embodiments.
`Terminology
`[0021] The terms integrated circuit (IC), semiconductor
`device, monolithic device, microelectronic device, and chip
`are often used interchangeably in the field of electronics.
`The present invention is applicable to all the above as they
`are generally understood in the field.
`[0022] Memory modules in accordance with the present
`invention address the performance gap between main
`memory and mass storage (e.g., hard disk drives (HDD)).
`There is an ever growing performance gap between these
`two layers in the memory hierarchy.
`[0023] It is noted that in a typical, but not required,
`application, a memory module in accordance with the
`present invention is an end-user add-in device. The port
`ability aspect of such an embodiment is both a benefit and
`a problem. The benefits include, but are not limited to no
`added cost to the base system; flexible configurations to
`allow customization to specific needs; and independent
`system link such that it substantially reduces bus conflict
`when retrieving information in a highly threaded environ
`ment. Further benefits include, but are not limited to, a
`reduction of power, and an improved HDD reliability. The
`power savings and reliability are side benefits of being able
`to keep the HDD in the offstate for extended periods of time.
`As for the problems due to the portable nature of the
`memory module, data encryption and security are useful to
`prevent the theft of data and/or the use of data that may have
`been modified without authorization.
`[0024] Disclosed herein are several mechanisms to
`improve memory system performance while maintaining
`data integrity and security. As noted above, various embodi
`ments of the present invention may incorporate one or more
`of these mechanisms. Power State Aware (PSA) is a mecha
`nism where the memory module controller can act, to a
`predetermined extent, independently of the ACPI power
`state manager to reduce power consumption for the purpose
`of meeting desired performance or power criteria. Stored
`Image Integrity (SII) is a mechanism by which stored
`images are protected from modification and/or theft, includ
`ing loading valid data sets based, at least in part, on
`predetermined file criteria. System Boot Manager is a
`mechanism that directs the memory module controller to
`source application code and data from the memory module
`and from specific memory types and locations within the
`memory module. Most Recently Used (MRU) is a mecha
`nism where the most recently used data and applications are
`maintained in a highly ready state to ensure that the system,
`of which the inventive memory module form a part,
`responds as quickly as possible. User Selectable Application
`Acceleration is a mechanism in which a user selects which
`applications and data sets are to be managed and maintained
`in the memory module. Adaptive Learning Method is a
`
`mechanism in which the memory module adapts to user
`operations over a period of time in order to maintain a high
`state of readiness. Memory Maintenance Routines are the
`mechanisms by which the memory module is managed.
`Various embodiments of the present invention support one
`or more memory maintenance technologies. DRAM refresh,
`FLASH write wearing, emergency power loss, cache flush
`ing, and security management are examples of such memory
`maintenance technologies.
`[0025] To meet the growing need for performance
`improvements new memory module configurations are nec
`essary to meet that performance demand. These new
`memory modules will use a combination of storage types to
`gain dramatic improvements in operational performance and
`storage capacity. In order for the different storage media to
`operate together cleanly and to deliver the highest possible
`performance special embedded operational functions must
`be defined. These embedded functions will be required to
`operate independent of normal system operations and must
`be designed to limit interference during normal operation.
`[0026] With these various storage media types available to
`the system, predetermined data sets and applications can be
`associated with different types of storage media to extract
`the best desired system behavior. Various functions are
`described herein to improve system performance based on
`the particular abilities afforded by a hybrid memory con
`figuration of memory modules in accordance with the
`present invention.
`[0027] An illustrative memory module, in accordance with
`the present invention, uses a hybrid memory configuration
`wherein high speed volatile memory is used to improve
`memory module system performance and to manage tem
`porary storage operations; and nonvolatile high density
`slower memory is used to store system data that is to be
`maintained regardless of power state. It is noted that non
`volatile memories such as FLASH have write life limita
`tions, and embodiments of the present invention allow the
`volatile memory of the memory module to be used at times
`in place of writes to the non-volatile memory, thereby
`effectively increasing the write life of the non-volatile
`memory. A simplified block diagram is shown in FIG. 1. The
`various types of storage media require maintenance opera
`tions to ensure proper long term operability.
`[0028] Various embodiments of the present invention
`allow for the addition of system capabilities that have not
`previously been available in memory module technologies.
`In various embodiments, these capabilities operate substan
`tially free from external control.
`Memory Module
`[0029] Referring to FIG. 1, an illustrative memory module
`is shown which consists of five major functional blocks and
`two lesser functional blocks. The major blocks are: an
`Express Card Interface; a memory module controller; a
`DRAM memory; a FLASH memory; and a voltage regulator
`(and/or one or more power transistors). The lesser blocks
`illustrated in FIG. 1 are: optional Uninterruptible Power
`Supply (UPS) capacitors or battery (for emergency shut
`down operations); and various other electrical components
`such as decoupling capacitors, inductors, and so on, which
`are used for well-known miscellaneous functions in elec
`tronic products such as memory modules.
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1005, p. 12
`
`

`

`US 2007/0136523 A1
`
`Jun. 14, 2007
`
`[0030] The memory module controller may be imple
`mented as a single integrated circuit, or as a combination of
`two or more integrated circuits. The present invention is not
`limited to any particular partitioning, distribution, or group
`ing of functional blocks onto one or more integrated circuits.
`The Express Card Interface is considered the Host bus
`interface as defined by the ExpressCard 1.0 specification. All
`other elements of the interface, DRAM/FLASH types, can
`be customized for any supplier to any application or avail
`ability of parts. In alternative embodiments, other functional
`blocks can be added depending on applications or tasks that
`the memory module is intended to perform. The arrange
`ment illustrated in FIG. 1 includes an embedded, or inte
`grated, voltage regulator control block within the memory
`module controller. In some embodiments, the power elec
`tronics may also be integrated within the memory module
`controller. As noted above, the present invention is not
`limited to any particular partitioning, distribution, or group
`ing, of circuits or functional blocks.
`[0031] The lesser blocks, mentioned above, make up the
`discrete components that are typically used for power decou
`pling, voltage regulator (VR) filtering, and fail safe DRAM
`data retention/emergency flushing, which various embodi
`ments perform if power is lost prior to mirroring the DRAM
`data to a nonvolatile location.
`[0032] In the illustrative embodiment of FIG. 1, all
`devices, with the exception of the memory module control
`ler, are off-the-shelf components that are commercially
`available. It will be appreciated that the present invention is
`not limited to the use of any particular off-the-shelf com
`mercially available components, and it will be further appre
`ciated that the illustrated devices may be custom designed,
`and/or integrated in any suitable manner.
`[0033] The battery UPS and CAPUPS are optional design
`features for the memory module controller. As part of the
`general architecture support for emergency power down
`conditions, backup power needs to be provided as an option.
`In some embodiments of the present invention, if power
`were lost and contents in the DRAM have not been saved in
`a non-volatile location then the intent would be to maintain
`a power reserve large enough to write the volatile data to a
`non-volatile location on the memory module. Such a non
`volatile location on the memory module is typically imple
`mented with FLASH memory, however the present inven
`tion is not limited to any particular non-volatile memory
`technology.
`Memory Controller
`[0034] Referring to FIG. 2, an illustrative Memory Mod
`ule Controller is shown that has six major blocks which
`interface to the external world. The ExpressCard Interface or
`Host includes a PCIe Controller; a USB Controller; and an
`SMBUS Controller. A DRAM Memory Controller; a
`FLASH Memory Controller; and a Voltage Regulator Con
`troller make up the customizable back end of the illustrative
`memory module controller.
`[0035] The PCIe (Host) interface in the illustrative
`embodiment of FIG. 2 conforms to the ExpressCard release
`1.0 specification. In that specification, compatibility to the
`PCI Express 1.0a release and the USB 2.0 specification is
`called for. It is noted that it is not necessary for the memory
`module controller to have both interfaces. Supporting only
`one of the interfaces is sufficient to meet the ExpressCard
`release 1.0 specification.
`
`[0036] The DRAM interface in the illustrative embodi
`ment of FIG. 2 conforms to the IEEE DDR2 DRAM
`specification. It will be appreciated that the IEEE DDR2
`DRAM specification can be replaced with a specification
`produced by a DRAM supplier, and that the circuitry of the
`DRAM controller can be modified so that the memory
`module controller is operable in accordance with the alter
`native DRAM specification.
`[0037] The FLASH interface in the illustrative embodi
`ment of FIG. 2 conforms to the IEEE NAND Flash Speci
`fication. It will be appreciated that the IEEE NAND Flash
`specification can be replaced with a specification produced
`by a FLASH supplier, and that the circuitry of the FLASH
`controller can be modified so that the memory module
`controller is operable in accordance with the alternative
`FLASH specification.
`[0038] It is noted that the SMBUS controller must con
`form to the SMBUS 2.0 specification per the ExpressCard
`release 1.0 specification.
`[0039] For reduced cost and simplicity of design, a Volt
`age Regulator controller is included in the illustrative
`memory module controller shown in FIG. 2. This is not a
`requirement of the ExpressCard release 1.0 specification. In
`some embodiments of the present invention, the integrated
`VR controller can be disabled, and an external VR can be
`incorporated into a memory module.
`[0040] Still referring to FIG. 2, there are several internal
`blocks that define the functionality of the memory module
`controller. These basic core functions and resources are
`supported to maximize the system performance based on the
`memory module resources that are available. These internal
`blocks include a Data, Address and command router; a
`Router Arbitration and control module; a Security manager;
`a CPRM manager and encryption engine; an AES manager
`and encryption engine (one per Data Storage path); an
`ECC/EDC Engine (one per Data storage path); a Write
`Leveling engine for the FLASH controller; and a sensor
`circuit operable to produce at least one signal that is repre
`sentative of a voltage variable performance parameter of a
`memory module controller integrated circuit.
`[0041] Still referring to FIG. 2, the router is a functional
`block that acts as the bus traffic control center. Data, Address
`and Command paths from the PCIe bus and the USB 2.0 bus
`destinations are controlled by the router. Two of the func
`tions supported by the router are: 1) DRAM as RD/WR
`Cache to the FLASH memory; and 2) operation of the
`DRAM fully independent from FLASH, with the FLASH
`maintenance functions built into the hardware of the
`memory module controller. The FLASH maintenance func
`tions are built into the controller and do not require system
`or user intervention.
`[0042] In various embodiments of the present invention,
`both router functions mentioned above are included since it
`may not be known if the operating system can easily or
`successfully delineate the difference between the two types
`of memory. If the DRAM is treated as a cache to the FLASH,
`then traditional cache management functionality is required.
`In some embodiments, software drivers are used to take
`advantage of the memory module with fully independent
`DRAM and FLASH operations. This effectively is having
`the memory module behave as though two more layers of
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1005, p. 13
`
`

`

`US 2007/0136523 A1
`
`Jun. 14, 2007
`
`memory hierarchy are disposed in the system between main
`memory and the HDD as shown in FIG. 3.
`[0043] The Router block of the illustrative embodiment
`shown in FIG. 2 is made up of path multiplexers for Address,
`Command and Data. Address and Command paths are
`unidirectional from the host to the memory, whereas the data
`path is bi-directional, i.e., having both a path from the host
`to the memory and a path from memory back to the host. The
`term bi-directional as used here indicates that signals travel
`in two directions, rather than the more limiting sense of
`using a single wire to transfer information in both directions.
`The bidirectional nature of the Data path can be managed as
`a read path and a write path independent of each other. Such
`an independent arrangement allows for increased perfor
`mance and flexibility.
`[0044] The Router block functionality may be imple
`mented by either a fixed hardwired state machine controller
`configurable via the config registers of the memory module
`controller; or by a microcontroller where the code to be
`executed by the microcontroller is stored in the FLASH
`memory of the memory module. This microcontroller imple
`mentation provides more flexibility for the operation of the
`module. It is noted that typical microcontroller architectures
`introduce the overhead of initial power-on latency and the
`possibility of slightly reduced performance.
`[0045] The memory module controller in accordance with
`the present invention is “Power State Aware”. By having
`independent knowledge, separate from the ACPI control, of
`the power state and by having access to a user configuration
`of the power management window, the memory controller
`can use this information to improve performance under
`certain conditions and significantly reduce power consump
`tion under other power managed conditions. The memory
`module controller follows the ACPI specification plus
`enhancements that are user configured and/or system con
`figured.
`[0046] In the D0 (On) and D1 (Standby) states there can
`be several power levels that can be configured depending on
`the importance of performance and/or battery life.
`
`TABLE 1
`
`Partial List of ACPI Power States
`
`ACPI
`Power Power
`State
`Source
`
`Power
`Level
`(0–5). Memory Module operational Condition
`
`DO
`
`DO
`
`DO
`
`D1
`
`D1
`D1
`
`Line/
`Battery
`Battery
`
`Battery
`
`Line/
`Battery
`Battery
`Battery
`
`5
`
`No operational restrictions, full power
`
`4
`
`PCle/DRAM performance reduction, no
`FLASH restrictions
`PCle/DRAM DRAM wr buffer only, FLASH
`restrictions
`2 DRAM in standby, FLASH idle
`
`3
`
`1 DRAM in standby, FLASH standby
`O DRAM off, FLASH standby
`
`[0047] Power Level 5 level allows for full function, full
`performance operation. There are no preset restrictions
`placed on the DRAM, the FLASH, or any of the Express
`Card interfaces. The only restriction is what is gated by the
`thermal limit, or the power-in available limits for the
`ExpressCard devices as defined earlier, and there is no
`compromise on those limits.
`
`[0048] Power Level 4 reduces power by limiting the
`DRAM performance and the PCIe transaction performance.
`This operating state is supported for battery operated
`devices. It is not required for battery mode operation and is
`considered user configurable.
`[0049] Reduction of power in the DRAM can be accom
`plished in one of two ways: 1) reduce the maximum allowed
`number of read or write sequences in a given time period to
`the DRAM, essentially throttle the DRAM operation or
`reduce the frequency in which the DRAM is operating. A
`simple throttling algorithm can be used to restrict the
`number of cycles to the DRAM in any given time period.
`This reduces power and, in general, produces no noticeable
`decrease in system performance. The power saved by this
`type of throttling is good but not optimal.
`[0050] An improved power saving option is to slow the
`operating frequency of the device down and restrict the
`number of requests being serviced by the ExpressCard
`interface. By doing this a significant savings in power can be
`achieved. Voltage can be reduced to the DRAM, frequency
`is reduced to the DRAM, and the number of cycle requests
`to the DRAM are reduced making the device function in a
`very lower power state while maintaining a reasonable
`system performance level. Power is calculated as the fol
`lowing: Power-Leakage+CV*f, so the ability to reduce
`voltage and frequency can result in major power savings.
`Some embodiments of the present invention include inte
`grated voltage regulation circuitry for the memory module
`we have the capability of controlling this element on the
`module.
`[0051] Power Level 3 provides a significant reduction in
`power, however performance of the memory module is
`reduced. In this power state the DRAM is used only as a
`write buffer to the FLASH memory. In this way, power
`consumed by the DRAM is reduced and power consumed by
`the interface is reduced as a consequence of the reduced
`number of access requests being processed. The DRAM is in
`an IDLE or STANDBY state most of the time and is only
`active when write traffic needs to be processed. This is
`substantially different than the operational states defined in
`Power Level 4 which allows both read and write traffic to be
`processed by the DRAM. As in the Power Level 4 Details,
`due to the lower operational state of the DRAM, voltage to
`the DRAM can be reduced as well as the frequency of
`operation by the DRAM thus saving additional power by the
`module.
`[0052] Power Level 2 state is a standby state where low
`startup latency is wanted but without traffic being processed
`by the module. In this mode the DRAM is in a low power
`standby state and the FLASH is idle. Start-up latency by the
`DRAM is restricted by how deep a standby state is managed
`to the DRAM, clocks on or off frequency of the clock and
`the voltage that is supplied to the DRAM. FLASH memory
`in IDLE allows for normal access to that memory without
`any latency hits.
`[0053] In Power Level 1 there may be very little difference
`in the power consumed as compared to Power Level 2 since
`the amount of power consumed by the FLASH device in idle
`mode vs. standby mode is minor. An option to save power
`in this mode is to keep the DRAM in a low power standby
`state and to turn the power off to the FLASH device. Again
`the overall power savings may be small compared to Power
`Level 2.
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK