Petition for Inter Partes Review of U.S. Patent No. 8,301,833
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`Paper No. 1
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`SK HYNIX INC., SK HYNIX AMERICA INC., and SK HYNIX MEMORY
`SOLUTIONS INC.,
`Petitioners,
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`v.
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`NETLIST, INC.
`Patent Owner
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`Patent No. 8,301,833
`Issued: October 30, 2012
`Filed: September 29, 2008
`Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott Milton, Jayesh Bhakta
`Title: Non-Volatile Memory Module
`____________________
`Inter Partes Review No. IPR2017-00649
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`
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 8,301,833
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.1-.80 & 42.100-.123
`________________________
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`Petition for Inter Partes Review of U.S. Patent No. 8,301,833
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`I.
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`TABLE OF CONTENTS
`COMPLIANCE WITH REQUIREMENTS FOR A PETITION
`
`FOR INTER PARTES REVIEW ................................................................. 1
`A.
`Certification the 833 Patent May Be Contested by Petitioners ............. 1
`B.
`Fee for Inter Partes Review (§ 42.15(a)) ............................................... 1
`C. Mandatory Notices (37 CFR § 42.8(b)) ................................................ 1
`D.
`Proof of Service (§§ 42.6(e) and 42.105(a)) ......................................... 2
`II.
`IDENTIFICATION OF CLAIMS BEING CHALLENGED .................... 2
`III. RELEVANT INFORMATION CONCERNING THE
`CONTESTED PATENT ............................................................................... 4
`A.
`Effective Filing Date of the 833 Patent ................................................. 4
`B.
`Person of Ordinary Skill in the Art ....................................................... 4
`C.
`The 833 Patent ....................................................................................... 5
`1. Technical Overview ........................................................................ 5
`2. Relevant Prosecution History .......................................................... 6
`D.
`Construction of Terms Used in the Claims ........................................... 8
`1. “Operable at a … Clock Frequency” .............................................. 8
`IV. OVERVIEW OF THE PRINCIPAL PRIOR ART .................................... 8
`A. U.S. Patent Application Publication No. 2007/0136523 to
`Bonella (Ex. 1005) ................................................................................ 8
`1. Overview of Bonella ....................................................................... 9
`2. DRAM Write Buffer ..................................................................... 11
`3. Configurable Power Consumption ................................................ 12
`B.
`U.S. Patent No. 6,026,465 to Mills (Ex. 1007) ................................... 13
`C.
`Ashmore (Ex. 1008) ............................................................................ 14
`PRECISE REASONS FOR RELIEF REQUESTED ............................... 14
`A.
`Claims 1-30 Are Obvious Over Bonella and Mills ............................. 14
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`U.S. Patent Application Publication No. 2006/0212651 to
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`V.
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`Petition for Inter Partes Review of U.S. Patent No. 8,301,833
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`Claims 7 and 23 Are Obvious Over Bonella, Mills, with or
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`Claims 8-10 and 24-26 Are Obvious Over Bonella, Mills, with
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`B.
`C.
`D.
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`
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`1. Claims 1 and 15 Are Unpatentable ............................................... 14
`2. Claims 2 and 18 Are Unpatentable ............................................... 31
`3. Claims 3 and 19 Are Unpatentable ............................................... 32
`4. Claims 4 and 20 Are Unpatentable ............................................... 33
`5. Claims 5 and 21 Are Unpatentable ............................................... 34
`6. Claims 6 and 22 Are Unpatentable ............................................... 34
`7. Claims 7 and 23 Are Unpatentable ............................................... 37
`8. Claims 8 and 24 Are Unpatentable ............................................... 39
`9. Claims 9 and 25 Are Unpatentable ............................................... 41
`10. Claims 10 and 26 Are Unpatentable ............................................. 41
`11. Claims 11 and 27 Are Unpatentable ............................................. 42
`12. Claims 12 and 28 Are Unpatentable ............................................. 42
`13. Claims 13 and 29 Are Unpatentable ............................................. 43
`14. Claims 14 and 30 Are Unpatentable ............................................. 45
`15. Claim 16 Is Unpatentable .............................................................. 46
`16. Claim 17 Is Unpatentable .............................................................. 47
`Claims 1-30 Are Obvious Over Bonella, Mills, and Ashmore ........... 48
`without Ashmore, and Larson ............................................................. 50
`or without Ashmore, and Windows 2000 ........................................... 53
`1. Claims 8 and 24 Are Unpatentable ............................................... 53
`2. Claims 9 and 25 Are Unpatentable ............................................... 55
`3. Claims 10 and 26 Are Unpatentable ............................................. 55
`E.
`Ashmore, and Klein ............................................................................. 56
`F.
`Ashmore, and Maeda ........................................................................... 58
`VI. CONCLUSION ............................................................................................ 59
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`Claim 16 Is Obvious Over Bonella, Mills, with or without
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`Claim 17 Is Obvious Over Bonella, Mills, with or without
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`Petition for Inter Partes Review of U.S. Patent No. 8,301,833
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`Attachment A. Proof of Service of the Petition
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`Attachment B. List of Evidence and Exhibits Relied Upon in Petition
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`Petition for Inter Partes Review of U.S. Patent No. 8,301,833
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`I.
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`COMPLIANCE WITH REQUIREMENTS FOR A PETITION
`FOR INTER PARTES REVIEW
`A. Certification the 833 Patent May Be Contested by
`Petitioners
`Petitioners certify they are not barred or estopped from requesting inter
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`partes review of U.S. Patent No. 8,301,833 (“the 833 Patent”) (Ex. 1001). No
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`Petitioner, nor any party in privity with a Petitioner, has filed a civil action
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`challenging the validity of any claim of the 833 Patent. The 833 Patent has not
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`been the subject of a prior inter partes review by any Petitioner or a privy of a
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`Petitioner.
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`Petitioners also certify this petition for inter partes review is filed within one
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`year of the date of service of a complaint alleging infringement of a patent – no
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`complaint alleging infringement of the 833 Patent has been served on any
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`Petitioner. Petitioners therefore certify this patent is available for inter partes
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`review.
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`B.
`Fee for Inter Partes Review (§ 42.15(a))
`The Director is authorized to charge the fee specified by 37 CFR § 42.15(a)
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`to Deposit Account No. 50-1597.
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`C. Mandatory Notices (37 CFR § 42.8(b))
`The real parties of interest of this petition are the Petitioners: SK hynix Inc.,
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`SK hynix America Inc. and SK hynix memory solutions Inc.
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`Petition for Inter Partes Review of U.S. Patent No. 8,301,833
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`The 833 Patent is involved in the following legal proceedings: Netlist, Inc. v.
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`SMART Modular Technologies, Inc., Case No. 8-13-cv-00996 (C.D. Cal.); Smart
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`Modular Technologies, Inc. v. Netlist, Inc., Case No. 4-13-cv-03916 (N.D. Cal.);
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`Diablo Technologies, Inc. v. Netlist, Inc., Case No. 4-13-cv-03901 (N.D. Cal.);
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`Netlist, Inc. v. Smart Modular Technologies, Inc., 4-13-cv-05889 (N.D. Cal.);
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`SanDisk Corp. v. Netlist, Inc., IPR2014-00994 (institution denied); and SMART
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`Modular Technologies Inc. v. Netlist, Inc., IPR2014-01370 (institution denied).
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`Lead Counsel is Joseph A. Micallef (Reg. No. 39,772), Sidley-SKH-
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`IPR@sidley.com, (202) 736-8492. Backup Lead Counsel is Samuel A. Dillon
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`(Reg. No. 65,197), Sidley-SKH-IPR@sidley.com, (202) 736-8298.
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`Service on Petitioner may be made by e-mail (Sidley-SKH-
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`IPR@sidley.com), mail, or hand delivery to: Sidley Austin LLP, 1501 K Street,
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`N.W., Washington, D.C. 20005. The fax number for lead and backup counsel is
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`(202) 736-8711.
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`D.
`Proof of Service (§§ 42.6(e) and 42.105(a))
`Proof of service of this petition is provided in Attachment A.
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`II.
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`IDENTIFICATION OF CLAIMS BEING CHALLENGED
`Petitioners propose several grounds for trial as set forth below, none of
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`which is redundant. Each ground is based primarily on U.S. Patent Application
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`Publication No. 2007/0136523 to Bonella (“Bonella”) (Ex. 1005). However,
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`Petition for Inter Partes Review of U.S. Patent No. 8,301,833
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`Petitioners also address several arguments that Patent Owner may raise in response
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`by proposing grounds that more closely satisfy the claim limitations to which such
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`arguments would be directed. Such additional grounds are not redundant because
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`they are “rational, narrowly targeted, and not burdensome.” IPR2015-01912, Paper
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`10 at 17-18. Petitioners therefore respectfully request that trial be instituted on all
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`grounds and arguments advanced herein. Specifically, this Petition seeks a finding
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`that claims 1-30 of the ‘833 Patent are unpatentable as follows:
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`(i) Claims 1-30 are obvious under 35 U.S.C. § 103 over Bonella (Ex.
`1005) in view of Mills (Ex. 1007);
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`(ii) Claims 1-30 are obvious under § 103 over Bonella in view of Mills
`and Ashmore (Ex. 1008);
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`(iii) Claims 7 and 23 are obvious under § 103 over Bonella, Mills, with or
`without Ashmore, and in further view of Larson (Ex. 1019);
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`(iv) Claims 8-10 and 24-26 are obvious under § 103 over Bonella, Mills,
`with or without Ashmore, and in further view of Windows 2000 (Ex.
`1021);
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`(v) Claim 16 is obvious under § 103 over Bonella, Mills, with or without
`Ashmore, and in further view of Klein (Ex. 1009); and
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`(vi) Claim 17 is obvious under § 103 over Bonella, Mills, with or without
`Ashmore, and in further view of U.S. Patent App. Pub. No.
`2005/0249011A1 to Maeda (Ex. 1013).
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`Petition for Inter Partes Review of U.S. Patent No. 8,301,833
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`Petitioner’s proposed claim constructions, the evidence relied upon, and the
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`precise reasons why the claims are unpatentable are provided in §§ III-V, below.
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`The evidence relied upon in this petition is listed in Attachment B.
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`III. RELEVANT INFORMATION CONCERNING THE
`CONTESTED PATENT
`A. Effective Filing Date of the 833 Patent
`The 833 Patent resulted from U.S. Patent Application Serial No. 12/240,916,
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`filed September 29, 2008, Ex. 1001, Face, which ultimately claims priority to U.S.
`
`Provisional Application No. 60/941,586, filed on June 1, 2007. Because the prior
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`art relied upon in this petition was either filed or published well before the June 1,
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`2007 date, for the purposes of the analysis here Petitioners will assume a June 1,
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`2007 effective date.
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`B.
`Person of Ordinary Skill in the Art
`A person of ordinary skill in the art in the field of the 833 Patent in the 2007
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`time frame would have been someone with a Bachelor’s degree in materials
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`science, electrical engineering, computer engineering, computer science, or in a
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`related field and at least one year of experience with the design or development of
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`semiconductor non-volatile memory circuitry or systems. Decl. of Ron Maltiel
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`(Ex. 1003), ¶¶48-49.
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`Petition for Inter Partes Review of U.S. Patent No. 8,301,833
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`C. The 833 Patent
`1.
`Technical Overview
`The 833 Patent discloses a memory system which can communicate with a
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`host system such as a disk controller of a computer system. Ex. 1001, Abstract.
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`The memory system can include volatile and non-volatile memory and a controller
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`configured to back up the volatile memory using the non-volatile memory in the
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`even of a trigger condition. Id. In order to power the system in the event of a
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`power failure or reduction, the memory system can include a secondary power
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`source such as a capacitor bank. Id. Figure 1 shows an example memory system:
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`
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`Ex. 1001, Fig. 1, 3:16-17; Ex. 1003, ¶50.
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`The volatile memory system can be operated at a reduced frequency during
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`backup and/or restore operations to improve the efficiency of the system and save
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`power. Ex. 1001, 4:41-44. Figure 9 depicts an example method of operating a
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`volatile memory subsystem at a reduced rate in a back-up mode:
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`
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`Ex. 1001, Fig. 9, 3:45-48; see id., 17:39-18:13; Ex. 1003, ¶51.
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`2.
`Relevant Prosecution History
`The application underlying the 833 Patent was filed on September 29, 2008.
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`The claims were initially rejected as obvious in view of the Li and Oshikiri
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`references. Ex. 1002, 166-172. Patent Owner responded by arguing that the art
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`merely showed “different processing speeds,” not “different memory subsystem
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`Petition for Inter Partes Review of U.S. Patent No. 8,301,833
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`operation frequenc[ies].” Id., 134-149. The Examiner again rejected the claims as
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`obvious, explaining that the claims were “not directed to the operating speed of a
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`memory, but instead … to the operating speed of a memory subsystem.” Ex. 1002,
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`123. Patent Owner submitted claim amendments that specified a “first clock
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`frequency,” a “second clock frequency,” and a “third clock frequency.” Ex. 1002,
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`107-117; Ex. 1003, ¶¶52-56.
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`The claims were again rejected as obvious, this time over the Li and Cope
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`references. Ex. 1002, 59-73. The Examiner also rejected what are now claims 2
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`and 18 as indefinite because they recited “approximately equal” clock frequencies.
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`Id. Patent Owner responded by amending the claims to replace the word
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`“approximately” with “substantially,” stating that “in practice there will always be
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`a difference” between clock frequencies. Id. Patent Owner also argued that Cope
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`“cannot be used to describe two modes of operation, where a DRAM in a first
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`mode operates at a first clock frequency and in a second mode operates at another
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`frequency.” Id., 71. The Examiner subsequently withdrew the rejections and the
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`833 Patent issued on October 10, 2012. Id., 1; Ex. 1003, ¶¶57-58.
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`Two previous petitions for inter partes review were filed against the 833
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`Patent. In IPR2014-00994, filed by SanDisk Corporation, the Board construed the
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`term “clock frequency” and ultimately denied review of claims 1-30, Paper 8, and
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`later denied SanDisk’s request for rehearing, Paper 10. In IPR2014-01370, filed
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`Petition for Inter Partes Review of U.S. Patent No. 8,301,833
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`by SMART Modular Technologies Inc., the Board determined that no claim terms
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`required explicit construction and denied review of claims 1-30. Paper 13.
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`D. Construction of Terms Used in the Claims
`In this proceeding, claims must be given their broadest reasonable
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`construction in light of the specification. 37 CFR § 42.100(b). If Patent Owner
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`contends terms in the claims should be read to have a special meaning, those
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`contentions should be disregarded unless Patent Owner also amends the claims
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`compliant with 35 U.S.C. § 112 to make them expressly correspond to those
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`contentions. See 77 Fed. Reg. 48764 at II.B.6 (Aug. 14, 2012); cf. In re Youman,
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`679 F.3d 1335, 1343 (Fed. Cir. 2012).
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`1.
`“Operable at a … Clock Frequency”
`The Board has previously interpreted the term “clock frequency” to require
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`“identification of a clock running at a particular frequency.” IPR2014-00994,
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`Paper 8 at 6. This interpretation is consistent with the 833 Patent’s specification.
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`See, e.g., Ex. 1001, 17:25-38; Ex. 1003, ¶63. Petitioners have applied this
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`interpretation below.
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`IV. OVERVIEW OF THE PRINCIPAL PRIOR ART
`A. U.S. Patent Application Publication No. 2007/0136523 to
`Bonella (Ex. 1005)
`Bonella was filed on December 8, 2006, and claimed priority to a
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`provisional application (11/635,926) (Ex. 1006) filed on December 8, 2005.
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`Petition for Inter Partes Review of U.S. Patent No. 8,301,833
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`Bonella is thus prior art under 35 U.S.C. § 102(e) (pre-AIA). Bonella expressly
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`incorporates its provisional application by reference. Ex. 1005, ¶1; Ex. 1003,
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`¶¶64-65.
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`1. Overview of Bonella
`Bonella is directed to a plug-and-play end-user add-in memory module for
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`computers and consumer electronic devices. Ex. 1005, ¶2. Bonella discloses a
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`memory module including a volatile memory, a non-volatile memory, and a
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`controller that provides address, data, and control interfaces to the memories and to
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`a host system, such as, for example, a personal computer, and provides one or
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`more additional layers in the memory hierarchy of the host system. Ex. 1005, ¶6.
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`Bonella teaches that this hybrid memory module fills the performance gap between
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`main memory and a hard disk drive, and “can improve HDD reliability by keeping
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`the HDD turned off for significant amounts of time, which also can reduce overall
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`power consumption on laptops.” Id., ¶65; Ex. 1003, ¶66.
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`Figure 1 is a high level system block diagram of an illustrative memory
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`module in accordance with the present invention:
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`
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`Figure 1 shows the illustrative memory module with “five major functional
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`blocks and two lesser functional blocks.” Ex. 1005, ¶29. “The major blocks are:
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`an Express Card Interface; a memory module controller; a DRAM memory; a
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`FLASH memory; and a voltage regulator (and/or one or more power transistors).”
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`Id. “The lesser blocks illustrated in FIG. 1 are: optional Uninterruptible Power
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`Supply (UPS) capacitors or battery (for emergency shut-down operations); and
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`various other electrical components such as decoupling capacitors, inductors, and
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`so on, which are used for well-known miscellaneous functions in electronic
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`products such as memory modules.” Id.; Ex. 1003, ¶¶67-68. Bonella discloses
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`that the memory module implements the DDR2 DRAM Specification and the
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`NAND Flash Specification, but can be modified to implement different interfaces
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`and conform with alternative specifications. Ex. 1005, ¶¶36-37; Ex. 1003, ¶69.
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`Bonella teaches that using a combination of storage types can “gain dramatic
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`improvements in operational performance and storage capacity,” but that doing so
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`requires “special embedded operational functions” in order to allow the memory
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`module to operate independently so as to limit interference with normal system
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`operation. Ex. 1005, ¶25. These functions include Flash write leveling, DRAM
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`write buffer flushing to Flash, Flash flushing to HDD, device failure management,
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`a power loss algorithm, security management, etc. Id., ¶¶92-108; Ex. 1003, ¶70.
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`2.
`DRAM Write Buffer
`Bonella teaches that its hybrid memory includes a DRAM write buffer
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`“which allows the HDD to be shut off for extended periods of time. This does two
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`things: 1) lowers power consumption; and 2) reduces HDD failures.” Ex. 1005,
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`¶99. By maintaining “[a] certain amount of DRAM” for “write buffering and data
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`read buffering,” Bonella’s system can “maintain a very high level of system
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`performance for” data accesses “that are traditionally targeted for the hard disk
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`drive.” Id., ¶80. Bonella teaches that write buffering allows for the HDD to be
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`shut off, meaning that write data is initially stored only to the DRAM and is later
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`copied to the HDD. Id., ¶99. One of ordinary skill in the art would be readily
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`familiar with the concept of write buffering or write caching. Ex. 1003, ¶¶71-72;
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`see, e.g., Microsoft Computer Dictionary (5th Ed.) (2002) (Ex. 1020), 76
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`(describing a “buffer”), 575 (defining an analogous “write-behind cache”).
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`Bonella also teaches that the DRAM write buffer is occasionally backed up
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`to the internal Flash memory so as to ensure data integrity in case of a power loss.
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`Ex. 1005, ¶96. This write buffer flushing can be triggered by a power loss event,
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`which then causes Bonella’s “Power loss algorithm” to be executed:
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`When the memory module controller detects a power loss
`event, the data that is flagged as critical is flushed to the FLASH, a
`flag is set and the memory module then shuts down. At new power on
`the normal power on sequence is followed and data restored to the
`DRAM.
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`Id., ¶101. During the execution of the power loss algorithm, Bonella’s memory
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`relies on backup power such as, for example, Uninterruptible Power Supply (UPS)
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`capacitors. Id., ¶29. The memory maintains a sufficiently large power reserve so
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`as to write the data to Flash memory. Id., ¶33; Ex. 1003, ¶¶73-75.
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`3.
`Configurable Power Consumption
`Bonella also teaches that the hybrid memory module includes “Power State
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`Aware” functionality that allows the module to significantly reduce power
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`consumption when required. Ex. 1005, ¶45. For example, Bonella teaches a
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`“Power Level 5” state that allows for full function, full performance operation. Id.,
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`¶47. Bonella also teaches a “Power Level 4” state that reduces the power
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`consumption of the memory module by limiting the DRAM performance. Id., ¶48.
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`Bonella explains that one way to reduce the power consumption of the memory
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`module is to slow or reduce the operating frequency of the DRAM. Id., ¶¶49-50;
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`Ex. 1003, ¶¶76-79. Bonella teaches that reducing the DRAM frequency in this
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`way can result in “major power savings.” Ex. 1005, ¶50.
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`B. U.S. Patent No. 6,026,465 to Mills (Ex. 1007)
`Mills was issued on February 15, 2000, and is therefore prior art under 35
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`U.S.C. § 102(b) (pre-AIA). Mills describes several interfaces for a Flash memory
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`device, one of which is a synchronous flash interface: “FIG. 6 illustrates a block
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`diagram of a synchronous flash interface (SFI) flash memory integrated circuit 600
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`that incorporates a complete synchronous flash interface in a single flash memory
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`chip.” Ex. 1007, 16:60-63. The synchronous flash interface includes a clock input
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`such that all the external operations of the device are synchronized to the rising
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`edge of the clock. Id., 17:10-25.
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`Mills teaches that this synchronous operation is used for both read
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`operations and write operations: “When SFI is enabled, interlace control 670 and
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`[bank] select logic 674 operate to interlace read (and write) operations between
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`flash bank A 610 and a flash bank B 620 ….” Id., 17:33-39. Because “the device
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`is interleaved internally,” it “creates an average access time for sequential read
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`Petition for Inter Partes Review of U.S. Patent No. 8,301,833
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`accesses that is significantly less than the access time of an asynchronous flash
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`device.” Id., 17:1-9; Ex. 1003, ¶¶81-82.
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`C. U.S. Patent Application Publication No. 2006/0212651 to
`Ashmore (Ex. 1008)
`Ashmore was filed on December 22, 2005, and is therefore prior art under
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`35 U.S.C. § 102(e) (pre-AIA). Ashmore “provides a method for reducing battery
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`power consumption during a main power loss to reduce the likelihood of loss of
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`user write-cached data in a write-caching mass storage controller.” Ex. 1008, ¶9.
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`Ashmore’s specific technique is explained as follows:
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`In response to a loss of main power, the controller only
`provides battery power to the critical memory banks, but not to the
`non-critical memory banks, in order to reduce the amount of battery
`power consumed during the main power outage, thereby extending the
`time the critical memory banks can store the critical data to reduce the
`likelihood of user data loss.
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`Id., ¶7; Ex. 1003, ¶84.
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`V.
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`PRECISE REASONS FOR RELIEF REQUESTED
`A. Claims 1-30 Are Obvious Over Bonella and Mills
`1.
`Claims 1 and 15 Are Unpatentable
`a)
`Preambles
`The preamble of claim 1 recites a “method for controlling a memory system
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`operatively coupled to a host system, the memory system including a volatile
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`memory subsystem and a non-volatile memory subsystem.” The preamble of claim
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`15 recites a “memory system operatively coupled to a host system.”
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`Bonella is directed to “a memory module including a volatile memory, a
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`non-volatile memory, and a controller that provides address, data, and control
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`interfaces to the memories and to a host system, such as, for example, a personal
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`computer, is operable to interact with the host system so as to provide one or more
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`additional layers in the memory hierarchy of the host system.” Ex. 1005, ¶6
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`(emphasis added); see also id., Fig. 1, ¶10. Bonella thus discloses a “memory
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`system” (e.g., memory module, Fig. 1) “operatively coupled to” (e.g., via an
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`ExpressCard Interface) “a host system” (e.g., host system). Id., Fig. 1, ¶6. The
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`memory system also includes a “volatile memory subsystem” (e.g., DRAM) and a
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`“non-volatile memory subsystem” (e.g., Flash). Id.; Ex. 1003, ¶¶86-88. Therefore,
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`Bonella discloses the preambles of claims 1 and 15 to the extent they are limiting.
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`Operating a “Volatile Memory Subsystem” at a
`b)
`“First Clock Frequency”
`Claim 1 recites “operating the volatile memory subsystem at a first clock
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`frequency when the memory system is in a first mode of operation in which data is
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`communicated between the volatile memory subsystem and the host system.”
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`Claim 15 recites “a volatile memory subsystem operable at a first clock frequency
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`when the memory system is in a first mode of operation in which data is
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`communicated between the volatile memory subsystem and the host system.”
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`Bonella discloses a “volatile memory subsystem” in the form of a DRAM
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`and its associated controller. Ex. 1005, Fig. 1. Bonella also discloses “operating
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`the volatile memory subsystem at a first clock frequency.” For example, in the top
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`right corner of Figure 2 Bonella shows a “CLK” signal being provided to the
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`DRAM Interface by the DRAM Controller:
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`
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`Id., Fig. 2; Ex. 1003, ¶91. One of ordinary skill in the art would understand that
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`Bonella’s DRAM is operating at the particular frequency of the clock signal
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`(“CLK”). Ex. 1003, ¶92; Ex. 1005, ¶52 (“frequency of the clock”). Indeed,
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`Bonella’s provisional application, which is incorporated by reference, explains that
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`“[a]ll address and control input signals are sampled on the crossing of the positive
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`edge of CK and negative edge of CK#” and “[d]ata is referenced to all CK and
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`CK# crossings.” Ex. 1006, 22.
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`This operation is further confirmed by the usual operation of DDR2 DRAM,
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`Ex. 1003, ¶93, which Bonella explains can be used with his system. Ex. 1005, ¶36.
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`According to the DDR2 specification at the time of Bonella’s priority date, a
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`conforming DDR2 DRAM device receives two input clock signals, CK and CK(cid:3364)(cid:3364)(cid:3364)(cid:3364),
`positive edge of CK and negative edge of CK(cid:3364)(cid:3364)(cid:3364)(cid:3364).” DDR2 SDRAM Specification,
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`and “[a]ll address and control input signals are sampled on the crossing of the
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`JESD79-2B (Jan. 2005) (Ex. 1010), 6, 29. A skilled artisan would understand
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`Bonella’s DRAM “CK” signal to be a clock signal operating at a particular
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`frequency. Ex. 1003, ¶93.
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`Bonella also discloses that the “volatile memory subsystem [is] operable at a
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`first clock frequency when the memory system is in a first mode of operation.”
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`Bonella’s memory module has multiple power states, including Power Level 5
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`which “allows for full function, full performance operation” with “no preset
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`restrictions placed on the DRAM.” Ex. 1005, ¶47. This is contrasted with certain
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`power saving options Bonella contemplates such as “slow[ing] the operating
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`frequency of the device down” such that the clock “frequency is reduced to the
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`DRAM ….” Id., ¶50. The default operating frequency of Bonella’s DRAM clock
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`is therefore a “first clock frequency” and is used during the conventional full-
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`power operation of the system, which a skilled artisan would understand included
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`where “data is communicated between the volatile memory subsystem and the host
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`system” during a read from and write to the DRAM write buffer. E.g., Id.,
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`Abstract, ¶6, 8-9; Ex. 1003, ¶98.
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`Bonella also discloses a specific example in the first mode in which “data is
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`communicated between the volatile memory subsystem and the host system.” For
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`example, Bonella’s system includes several uses for the memory module, one of
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`which is as a write buffer: “[a] certain amount of DRAM is required to be kept
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`available for write buffering and data read buffering … this is done to maintain a
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`very high level of system performance for the program(s) that are executing from
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`memory module that are traditionally targeted for the hard disk drive.” Ex. 1005,
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`¶80. Bonella also explains that this “allow[s] the volatile memory of the memory
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`module to be used at times in place of writes to the non-volatile memory, thereby
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`effectively increasing the write life of the non-volatile memory.” Id., ¶27 This
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`means that the DRAM receives write data from the host system (“data is
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`communicated between the volatile memory subsystem and the host system”). See
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`id.; Ex. 1003, ¶94; see also id., ¶¶95-97. Bonella therefore discloses these claim
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`elements.
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`To the extent one might argue that the Board’s interpretation of “clock
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`frequency” requires a particular numeric value (i.e., as in number of cycles per
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`second), it would have been obvious to operate Bonella’s DRAM at frequencies
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`from 67-400MHz because Bonella teaches that his DRAM interface can
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`correspond to the “DDR2 DRAM specification” or to any other DRAM
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`specification. Ex. 1005, ¶36. It was known that DDR DRAM could be operated at
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`frequencies as low as 67MHz (DDR SDRAM Specification, JESD79 (Jun. 2000)
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`(Ex. 1014), 58; Ex. 1003, ¶99) while DDR2 DRAM could be operated at
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`frequencies as high as 400MHz (Ex. 1010, 69; Ex. 1003, ¶99).
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`It would have been obvious to use one of the known DDR or DDR2 DRAM
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`modules in Bonella’s system, and to subsequently clock the module at standards-
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`specified rates. Ex. 1003, ¶100. To do so would have been merely the use of a
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`known structure (a standard DRAM module and clock frequency) for its known
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`use (operation as a DRAM module) to achieve a predictable result (operating a
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`DRAM module at a standard clock frequency in Bonella’s system). Id. Moreover,
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`a skilled artisan would have been motivated to operate such memory at the
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`standard-specified frequencies in order to ensure proper operation of the memory.
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`Id., ¶100-101. Therefore, operating Bonella’s volatile memory “at a first clock
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`frequency,” even under this narrow interpretation, would have been obvious.
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`Operating a “Non-Volatile Memory Subsystem” at
`c)
`a “Second Clock Frequency”
`Claim 1 recites “operating the non-volatile memory subsystem at a second
`
`clock frequency when the memory system is in a second mode of operation in
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`which data is communicated between the volatile memory subsystem and the non-
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`volatile memory subsystem.” Claim 15 recites “a non-volatile memory subsystem
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`operable at a second clock frequency when the memory system is in a second mode
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`of operation in which data is communicated between the volatile memory
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`subsystem and the non-volatile memory subsystem.”
`
`Bonella discloses a “non-volatile memory subsystem” in the form of Flash
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`memory and its associated controller. Ex. 1005, Fig 1. As explained with respect
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`to the claimed “first mode,” see Ex. 1003, ¶¶94-97, Bonella discloses utilizing
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`DRAM as a write buffer and periodically flushing the write data to the Flash
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`memory. Ex. 1005, ¶96. During a power loss event, however, the memory module
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`controller flushes critical data to the FLASH: “When the memory module
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`controller detects a power loss event, the data that is flagged as critical is flushed to
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`the FLASH ….” Id., ¶101; Ex. 1003, ¶103.
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`The operation of Bonella’s syste