_
`_
`_
`A Flash memory employs uniform-size blocks in array
`planes and has separate read and Write paths connected to the
`US 2003/0035322 A1 Feb- 20, 2003
`(51) Int. c1.7 ....................... .. G11C 16/04; G11C 16/06; “W Planes: The readPa“? can read from one may Plane
`611C 8/00
`While the Write path writes in another array plane and one or
`_
`_
`more blocks are being erased. The uniform block siZe
`(52) US‘ (13533323360 permits a symmetric layout and provides maximum ?ex
`(58) F M f S
`’
`'
`’ 365/185 '11 ’ 230 02
`ibility in storage of data, code, and parameters. The uniform
`block siZe also alloWs spare blocks in the array planes to
`365/23001, 230.03, 185.09, 49, 230.08
`replace of any defective blocks. Aredundancy system for the
`Flash memory uses a CAM and a RAM for address com
`References Cited
`parison and substitution to replace addresses corresponding
`to defective memory elements. To reduce access delays, part
`of the input address such as the roW address goes directly to
`decoders, While another part of the input address Such as the
`block address goes to the CAM array.
`
`1e
`
`0 earc ..................... ..
`
`.
`
`,
`
`.
`
`,
`
`(56)
`
`U_S_ PATENT DOCUMENTS
`
`5,758,056 A * 5/1998 Barr ......................... .. 714/710
`6’O88’264 A
`7/2000 Hfizen et a1‘
`6,233,181 B1 * 5/2001 Hidaka ..................... .. 365/200
`6,260,103 B1 * 7/2001 Alexis et a1. ............. .. 711/103
`6,426,893 B1 * 7/2002 Conley et a1. ....... .. 365/185.11
`
`(12> Ulllted States Patent
`Wong
`
`(16) Patent N6.=
`(45) Date of Patent:
`
`US 6,614,685 B2
`Sep. 2, 2003
`
`US006614685B2
`
`(54) FLASH MEMORY ARRAY PARTITIONING
`
`OTHER PUBLICATIONS
`
`ARCHITECTURES
`
`(75) Inventor: Sau Ching Wong, Hillsborough, CA
`(US)
`
`(73) Assignee: Multi Level Memory Technology, San
`Jose, CA (US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`_
`(21) Appl' NO" 09/927’693
`(22) Filed:
`Aug. 9, 2001
`
`_
`
`_
`
`_
`
`Intel, “Preliminary Datasheet for 1.8 Volt Intel® Wireless
`Flash 336K100’ (W18)? Order N0~ 290701—002 (Jan- 2001)
`pp- 1— -
`Pathak, B. et al., 2001 IEEE International Solid—State Cir
`cuits Conference, Session 2, Non—vo1ati1e Memories, “A
`1.8V 64Mb 100MHz Flexible Read While Write Flash
`Memory” (Feb. 5, 2001).
`
`* Cited by eXaIIliIler
`
`Primary Examiner—Vu A. Le
`Assistant Examiner—Jung H. Hur
`(74) Attorney, Agent, or Firm—David T. Millers
`(57)
`ABSTRACT
`
`(65)
`
`Prior Publication Data
`
`8 Claims, 7 Drawing Sheets
`
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`ARRAY PLANE 210
`
`12
`
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`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1025, p. 1
`
`

`
`U.S.
`Patent
`
`Sep. 2, 2003
`
`Sheet 1 0f 7
`
`US 6,614,685 B2
`
`110-13
`
`L____X_Mgri__:ml
`:
`:Meg::bit Array Plane
`( 8 32KW Blocks )
`
`4HMeg bit Array Plane
`( 8 32KW Blocks )
`
`X Decoders
`
`4; :Meg?bit Array Plane
`( 8 32KW Blocks)
`
`
`
`4‘Meg' bit Array Plane (8 32KW Blocks)
`
`----- -
`
`-
`
`X Decoders
`
`4: zMeg?bit Array Plane
`(8 32KW Blocks)
`
`4 Meg bit Array Plane
`(8 32KW Blocks)
`
`|
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`X Decoders
`X Decoders
`
`:
`
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`
`|
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`( 8 32KW Blocks )
`
`X Decoders
`X Decoders
`4 Meg bit Arrtay Plane
`(7 ‘32KW Blocks + 4KW)
`
`110-0
`
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`
`:
`
`4HMeg?bit Array Plane
`(8 32KW Blocks)
`
`4'Meg- bit Array Plane
`(8 32KW Blocks)
`
`X
`
`Decoders
`Decoders
`4::Meg5bit Array Plane
`(8 32KW Blocks)
`
`4 Meg bit Array Plane
`( 8 32KW Blocks )
`
`Decoders
`X
`Decoders
`X
`Meg bit ArrayaPlanie
`( 8 32KW Blocks )
`
`4 Meg bit Array Plane
`(8 32KW Blocks)
`
`X Decoders
`X Decoders
`4 Megabit Array Plane
`
`'
`
`(8 32KW Blocks)
`
`Periphery
`Circuits
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`
`f
`
`100
`
`Fig. 1
`(Prior Art)
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1025, p. 2
`
`

`
`U.S. Patent
`
`Sep. 2, 2003
`
`Sheet 2 of 7
`
`US 6,614,685 B2
`
`X Decoders
`4 Meg bit Array Plane
`' ~ ' ( 64 4KW Blocks) " '
`
`I
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`
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`\
`
`4 Meg bit Array Plane
`(64 4KWBlocks)
`
`X Decoders
`X Decoders
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`4 Meg bit Array Plane
`(64 4KWBlocks)
`
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`(64 4KWBlocks)
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`(64 4KWBlocks)
`
`4 Meg bit Array Plane
`(64 4KWB1ocks)
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`X Decoders
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`
`X Decoders
`X Decoders
`
`210-3
`
`4 Meg bit Array Plane
`(64 4KWB1ocks)
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`4 Meg bit Array Plane
`2104
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`r _ _ — — - _ _ — — _ _ _ _ — _ _ — - — _ _ — _ — ‘I
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`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1025, p. 3
`
`

`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1025, p. 4
`
`

`
`U.S. Patent
`
`Sep. 2, 2003
`
`Sheet 4 0f 7
`
`US 6,614,685 B2
`
`_________________________________________________ __,
`
`FFLASH MEMORY 5w
`
`IEEAéIT MEMORY-ARRAY- ________ _ '
`
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`
`h___——_____-—_—_____-.-___-_______—_____—__-___—______
`
`_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __l
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`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1025, p. 5
`
`

`
`U.S. Patent
`
`Sep. 2, 2003
`
`Sheet 5 0f 7
`
`US 6,614,685 B2
`
`WL'L
`
`ROW DECODERS m
`_i_ _1_
`
`O O O
`
`_J_
`
`FIG. 5
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1025, p. 6
`
`

`
`U.S. Patent
`
`Sep. 2, 2003
`
`Sheet 6 6f 7
`
`US 6,614,685 B2
`
`COLUMN DECODERS AND DRIVERS
`E
`
`AWLAWLQWL AWL
`
`6 2 6% 366F166 6 AWLAWLW gm;
`Fig
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`
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`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1025, p. 7
`
`

`
`U.S. Patent
`
`Sep. 2, 2003
`
`Sheet 7 0f 7
`
`US 6,614,685 B2
`
`
`
`wwmmonz >>Om
`
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`
`S R E W R D & S R E D O C E D N M U L O C
`
`READ CIRCUITS
`
`PROGRAM & VERIFY
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1025, p. 8
`
`

`
`US 6,614,685 B2
`
`1
`FLASH MEMORY ARRAY PARTITIONING
`ARCHITECTURES
`
`BACKGROUND
`
`2
`of the other ?fteen array planes 110. In memory 100, the
`selected Word and bit lines in the array plane selected for the
`Write or erase operation are biased at the program or erase
`voltages; While the selected Word and bit lines in the array
`plane selected for the read operation are biased at read
`voltages.
`The erase, Write, and read status of each array plane 110
`is stored in an on-chip state-machine (not shoWn), and the
`user changes the erase, Write, and read status of an array
`plane 110 by issuing commands to Flash memory 100.
`Memory 100 generally alloWs reading in one array plane
`While Writing or erasing in another array plane. Table 1
`shoWs some of the possible parallel operation scenarios for
`memory 100.
`
`TABLE 1
`
`First operation in
`
`Allowed Parallel Operation in Another Array Plane
`
`one array plane:
`
`Read
`
`Program
`
`Erase
`
`Idle
`Read
`Program
`Erase
`
`X
`
`X
`X
`
`X
`X
`
`X
`X
`
`10
`
`15
`
`Data storage as memories generally have uniform and
`small block siZes and often provide additional memory
`space for error correction codes (ECCs). For example, a
`NAND-type Flash memory typically provides 512 bytes of
`ECC memory (not useable for data) in every containing 16K
`bytes of data storage. These memories often have minimum
`pin counts With either serial or multiplexed interfaces and
`are often used in small Flash memory cards for portable
`applications. For long-term reliability, such memories typi
`cally provide real-time sector-mapping features similar to
`those found in Hard Disk Drives (HDDs). For example,
`NAND-type Flash memories, used in Smart Media Cards,
`specify that a small number of blocks may be invalid, due to
`one or more defective bits. The system design must be able
`to mask out the invalid blocks via address mapping. Such
`memories are sometimes called Mostly Good Memories
`(MGM) and typically guarantee a minimum of about 98%
`good bits.
`Compact Flash (CF) and Multi Media Cards (MMCs)
`typically use NOR-type Flash memories that provide fea
`tures to improve the endurance. For example, the memory
`may have an intelligent erase algorithm With veri?cation to
`avoid over-stressing the oxide and improve program/erase
`(P/E) cycle endurance. Sector “tagging” (or sector hot
`counts) in such memories keep track of P/E cycling history
`so that the erase voltage can be set for each sector
`individually, according to the sector’s P/E cycling history. In
`additional, such Flash memories generally provide real-time
`replacement of a sector after the sector has reached a pre-set
`lifetime maximum number of P/E cycles.
`Flash memories for combined parameter, code, and data
`storage typically have asymmetric block siZes that are
`optimiZed to store different types of information. In general,
`these memories lack extra memory space for ECC and
`real-time sector-mapping capabilities but do provide parallel
`operations (POs) such as read-While-Write (RWW) or read
`While-erase (RWE), Which alloW a processor or another
`external device to Write to or erase one part of the memory
`chip While reading from another part of the same memory
`chip. This capability increases system performance, and
`reduces overall system cost by eliminating additional
`memory chips such as system SRAM for program updates or
`EEPROM to store system parameters.
`A 2001 ISSCC paper 2.3 titled “1.8V 64 Mbit 100 MHZ
`Flexible Read While Write Flash Memory” (ISSCC Article),
`Which is incorporated by reference in its entirety, describes
`a Flash memory device With ?exible RWW capabilities
`based on a “Multiple Partition” architecture, Which alloWs
`parallel operations for code and data. Intel’s 1.8V Wireless
`Flash Memory Datasheet (28F640W18), Which is also incor
`porated by reference in its entirety, further describes the
`memory described in the ISSCC Article.
`FIG. 1 illustrates the layout of a 64-megabit device 100
`shoWn in a die micrograph in the ISSCC paper. Memory
`device 100 has sixteen array planes 110-0 to 110-15, generi
`cally referred to as array planes 110. Each array plane 110
`has the same storage capacity and speci?cally contains four
`megabits of storage. With the hardWare partitioning of
`memory 100 into array planes 110, the user of memory 100
`can initiate a Write or erase operation in any one of the
`sixteen array planes 110 While simultaneously reading in any
`
`25
`
`35
`
`45
`
`55
`
`65
`
`Memory 100 permits allocation of array planes 110 for
`speci?c purposes. An example allocation of the memory
`space uses four array planes 110 for an operating system (or
`Real Time OS), tWo array planes 110 for a boot sector, and
`the remaining ten array planes 110 for ?le management.
`With this allocation and the RWW capability, a CPU can
`simultaneously read code of the Real Time OS While Writing
`or erasing data in the ?le management sections. The RWW
`architecture, in Which a user can seamlessly access data
`across various array plane or partition boundaries, increases
`the overall system performance.
`As shoWn in FIG. 1, one of array plane 110-0 is adapted
`for parameter storage, While ?fteen array planes 110-1 to
`110-15 are intended for main storage. More speci?cally,
`each of the 4-megabit array planes 110-1 to 110-15 contains
`eight 32-KWord “main” blocks, While the 4-megabit param
`eter array plane 100-0 contains eight 4-kWord “parameters”
`blocks and seven 32-KWord main blocks. Each 32-KWord or
`4-KWord block is independently erasable as a block.
`The bulk of the storage capacity of memory 100 is in the
`main blocks and can store code or data. The parameter
`blocks in array plane 110-0 are smaller for more ef?cient
`storage of parameters because parameters generally come in
`smaller units and are more frequently updated. For example,
`in a MP3 player, data representing music comes in relatively
`large units that are ef?ciently stored in the main blocks, and
`control parameters such as directory information requires
`less storage but is more frequently changed. More conven
`tional system using a data storage Flash memory Would
`normally store parameters in a separate EEPROM to
`improve storage efficiency and alloW access to parameters
`While accessing data. HoWever, softWare techniques alloW
`Flash memory 100 to emulate the Word-reWrite functionality
`of EEPROMs. As a result, the asymmetrically blocked
`architecture enables code, parameters, and data integration
`Within a single memory device.
`Flash memories With similar parallel operation capabili
`ties and asymmetric block architectures are described in the
`datasheet for the Simultaneous Operation Flash Memory
`(Am29DL323C) available from Advanced Micro Devices,
`Inc. and the datasheet for the Concurrent Flash
`(AT49BV1604 & AT49BV1614) available from Atmel, Inc.
`These datasheets are hereby incorporated by reference in
`their entirety.
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1025, p. 9
`
`

`
`US 6,614,685 B2
`
`3
`The 32 Meg bit device of AMD is divided into tWo banks,
`With bank 1 containing 8 megabits and bank 2 containing 24
`Meg bits. Bank 1 is further segmented into ?fteen 32-KWord
`blocks and eight 4-KWord blocks, While bank 2 is segmented
`into forty-eight 32-K Word blocks. In actual application, the
`user can structure bank 1 to store data and boot code, and
`bank 2 to store control code. The command sequence that
`tells bank 1 to program or erase data blocks resides as
`executable codes in bank 2. While bank 1 is being pro
`grammed or erased, the system can continue to execute code
`from bank 2 to manage other system operations. Depending
`on system implementation, the CPU can also execute code
`from bank 1, and program or erase any of the blocks in Bank
`2.
`A 16-megabit memory device from Atmel, Inc. has a bank
`containing 12 megabits and a bank containing 4 megabits
`and alloWs a read operation in one bank While the other bank
`performs a Write operation. Furthermore, the device has 40
`blocks including thirty 32-KWord main blocks, eight
`4-KWord parameter blocks, and tWo 16-KWord boot blocks.
`One of the disadvantages of asymmetric block architec
`tures is the inability to layout the arrays With symmetry and
`balance. For example, the 64-megabit memory of FIG. 1 has
`a layout in Which array plane 110-0, Which contains the
`parameter blocks, requires more integrated circuit area than
`do each of array planes 110-1 to 110-15. The parameter
`blocks contain less storage (i.e., feWer memory cells) than
`the main blocks do, and the parameter blocks require pro
`portionally more overhead because of the need for a block
`select transistor per block. Block select transistors connect
`the local bit lines (Within a block) to the global bit lines
`(across all blocks in the same array plane). For stacked-gate
`NOR Flash With negative-gate-channel-erase, additional
`overhead associated With the independent P-Well inside a
`separate Deep N-Well, is required for each block. Since the
`Width of array planes 110-1 to 110-8 on the left side of
`memory 100 is less than the required Width of array plane
`110-0, part of array plane 110-0 is on the right side of
`memory 100 With array planes 110-9 to 110-15. Peripheral
`circuitry 120 is around the blocks of array plane 110-0 that
`are on the right side of memory 100. Additionally, Flash
`memory 100 has nine array planes 110-0 to 110-8 on the left
`side and only seven array planes 110-9 to 110-15 on the right
`side.
`Memories With asymmetric block architectures and array
`layouts such as illustrated in FIG. 1 have signi?cant draW
`backs. In particular, since block siZes are non-uniform and
`hardWired, these memories cannot provide complete ?ex
`ibility in array partitioning. Only speci?c array planes are
`adapted for storage of parameter data. Therefore, these
`memories are unable to support all applications optimally
`and ef?ciently. For example, if an application’s boot infor
`mation occupies 16-K Words (or four 4-KWord parameter
`blocks), memory 100 Will have four 4-KWord parameter
`blocks and seven 32-KWord main blocks remaining in
`parameter array plane 110-0. Then, if this particular appli
`cation requires a total of tWelve individual 4-KWord blocks
`to store parameters (that need frequent updates), the appli
`cation must use up all of the remaining 11 blocks in
`parameter partition 110-0, and one of the eight main blocks
`in one of the ?fteen array planes 110-1 to 110-15. The
`remaining seven main blocks in the array plane containing
`one block of parameters cannot be effectively used to store
`data because parallel operations cannot simultaneously
`access parameters and data from the same array plane.
`Accordingly, the memory space in the seven main blocks of
`the array plane containing one block of parameters becomes
`(effectively) unusable.
`
`15
`
`25
`
`35
`
`45
`
`55
`
`65
`
`4
`A memory With an asymmetric block architecture also
`requires more time to develop. In particular, an asymmetric
`block architecture Would require additional time, manpoWer,
`and efforts to layout, simulate, and verify, and requires more
`effort and time to characteriZe and test the devices during
`prototyping and mass production
`Asymmetric array layout is also undesirable because an
`asymmetric layout generally uses integrated circuit area
`inef?ciently, Which results in a larger die siZe and greater
`manufacturing costs. The asymmetric layout of FIG. 1, for
`example, requires longer global lines running vertically
`betWeen the left and right portions of array plane 110-0 and
`requires additional column related circuitry such as sense
`ampli?ers, column decoders, and column pass devices, roW
`decoders, and drivers. The longer global I/O lines affect die
`siZe and performance.
`Asymmetric layouts also suffer from: non-uniform poWer
`and signal bussing, Which Will cause memory cells to exhibit
`different characteristics and performance across the array,
`e.g., the parameter blocks on the right may be more or less
`subject to noise from the periphery circuits.
`In addition to problems With asymmetric layout, variation
`in the siZes of blocks has disadvantages. In particular,
`differences in memory cell characteristics or performance
`can arise from the differences in the siZes of p-Wells. Having
`different block siZes that use a negative gate erase process
`generally cause p-Well siZes to vary since the p-Well siZes are
`proportional to the block siZes. The substrate resistance can
`vary With the siZe of the p-Wells and cause differences in the
`characteristics of memory cells in different blocks.
`Redundancy implementation in an asymmetric block
`architecture is also more complex. In conventional Flash
`memory redundancy and repair schemes, a defective
`memory element (either a Word line or a bit line) is identi?ed
`during testing, disabled, and replaced by a spare memory
`element. As a result, Whenever an incoming address matches
`the defective memory element’s address, a redundancy
`circuit causes selection of the spare memory element instead
`of the defective memory element. Providing both Word
`line-based and bit line-based redundancy provides the small
`granularity for defect replacement, but the circuit implemen
`tation can be very complex (requiring substantial complica
`tion of the decoders), requires substantial layout overhead,
`and adversely affects speed because of additional circuitry
`required in the decoders. Partition-Level redundancy repre
`sents the largest granularity, and is not practical to imple
`ment. Block-Level redundancy offers a compromise
`betWeen partition-level redundancy and bit line or Word line
`level redundancy, but block-level redundancy is not practi
`cal for a memory having asymmetric block siZes.
`
`SUMMARY
`
`In accordance With an aspect of the invention, a Flash
`memory has all blocks siZed for storage of frequently
`changed parameters but uses the blocks for storing
`parameters, codes, and main data. There are no physical
`distinctions betWeen main and parameter blocks. With all
`blocks being interchangeable and having a small siZe, the
`memory provides greater ?exibility allocation of blocks for
`storage of data, code, or parameters.
`Flash memories in accordance With the invention do not
`require asymmetric layouts and therefore avoid the disad
`vantages associated With asymmetric Flash memory layouts.
`In particular, array uniformity alloWs both right and left side
`arrays to have the same height (e.g., the same number of
`array planes per side, instead of more array planes on one
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1025, p. 10
`
`

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`US 6,614,685 B2
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`5
`side and a small array located among periphery circuits on
`the other side.) The layout or ?oor plan of the memories
`handles poWer, address, and signal buses more efficiently to
`reduce integrated circuit area required for these features. The
`layout symmetry can also provide better matching of cell
`performance across the memory array (e.g., better and more
`uniform bit line loading, noise effects, and erase character
`istics for all memory cells in all array planes.)
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 shoWs the layout of a knoWn Flash memory
`containing parameter blocks and main blocks that differ in
`storage capacity.
`FIG. 2 shoWs the layout of a Flash memory having array
`planes With uniform block siZe and providing parallel opera
`tions for access of data, code, or parameters in accordance
`With an embodiment of the invention.
`FIG. 3 shoWs separate read and Write paths for array
`planes of the Flash memory of FIG. 2.
`FIGS. 4A and 4B illustrate alternative implementations of
`redundancy systems for in Flash memories With uniform
`block siZe in accordance With an embodiment of the inven
`tion.
`FIG. 5 shoWs a redundancy system using a CAM and
`RAM for comparison and replacement of logical addresses
`With physical addresses.
`FIG. 6 shoWs an embodiment of a CAM for use in the
`redundancy system of FIG. 5.
`FIG. 7 shoWs an array plane including share block for a
`redundancy system in accordance With an embodiment of
`the invention.
`Use of the same reference symbols in different ?gures
`indicates similar or identical items.
`
`DETAILED DESCRIPTION
`
`In accordance With an aspect of the invention, a Flash
`memory for storing data, code, and parameters has a parti
`tion that de?nes array planes With blocks of uniform siZe.
`The memory supports parallel operations such as read
`While-Write (RWW) and read-While-erase (RWE) in any tWo
`array planes so that code or parameters required for access
`ing data can be read from one array plane While completing
`an access of other data from another array plane. The
`uniform block siZe is adapted for the information type (e.g.,
`parameters) needing the smallest blocks, Which provides
`maximum ?exibility by alloWing use of each array plane for
`any type of data. The uniform block siZe also facilitates use
`of an efficient block redundancy repair scheme in a Flash
`memory implementing parallel operations.
`FIG. 2 illustrates a Flash memory 200 With array planes
`210 that have uniform block siZe and implement parallel
`access of data, code, and/or parameters. In an exemplary
`embodiment, Flash memory 200 has a 64 Mbits of acces
`sible information storage that is partitioned into sixteen
`4-Mbit array planes 210-0 to 210-15, Which are generically
`referred to herein as array planes 210. Each array plane 210
`includes memory cells that are organiZed into blocks 212
`that permit block erase operations. In accordance With an
`aspect of the invention, all blocks in memory 200 have the
`same siZe (e.g., the same number of memory cells), and in
`the exemplary embodiment of the invention, each array
`plane 210 includes sixty-four 4-kWord blocks 212 of
`memory cells.
`Each memory cell in Flash memory 200 can be a con
`ventional Flash memory cell such as a stacked-gate transis
`
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`tor that is erased by FN tunneling, programmed by channel
`hot electron injection, and read by sensing bit line currents
`through the memory cell When the control gate (or Word
`line) associated With the memory cell is bias at a read
`voltage. In another embodiment, each memory cell in Flash
`memory 200 can be a stacked-gate transistor that is pro
`grammed and erased by FN tunneling. In either case, each
`memory cell in Flash memory 200 can be a binary memory
`cell, a multi-bit-per-cell digital Flash memory cell, or an
`analog Flash memory cell.
`Associated With each array plane 210 is X decode cir
`cuitry 220 that selects and biases a Word line in the array
`plane 210 for a read or Write operation. Y decode circuitry
`240 selects and biases global bit lines of array planes 210.
`In particular, for a read/Write operation, Y decode circuitry
`240 connect sense ampli?ers/data latches 250 to selected
`global bit lines. Block select circuitry (not shoWn) selects
`among blocks 212 in a selected array plane 210 and connects
`the global bit lines in the selected array plane to local bit
`lines in the selected block 212.
`For parallel operations, memory 200 includes an internal
`Write path and an internal read path. FIG. 3 illustrates a Write
`data path 310 and a read data path 320 connected to array
`planes 210. The separate Write and read data paths 310 and
`320 alloW any one of array planes 210 to receive data via
`path 310 for a Write operation While another array plane 210
`outputs data via path 320 for a read-While-Write operation.
`Generally, data input and output signals on paths 210 and
`220 With proper input and output buffering, share the same
`external data pads (not shoWn). I/O and control circuits (not
`shoWn) for memory 200 can control the timing of output
`data signals on the data pads to avoid bus contention With
`input data signals and can assert a busy signal to prevent an
`external system from driving data pads While memory 200
`is outputting data.
`Memory 200 also includes a Write address bus 312 that
`connects Write address latches 314 to array planes 210 and
`a read address bus 322 that connects read address latches
`324 to array planes 210. When the external system initiates
`a Write operation, Write latches 314 latch a Write address
`from the external system and subsequently hold the Write
`address until memory 200 is ready to receive another Write
`address, (e.g., until the Write operation is complete).
`Similarly, read address latches 324 latch a read address from
`the external system and subsequently hold the read address
`until memory 200 is ready to receive another read address,
`(e.g., until the read operation is complete).
`Each array plane 210 contains address selection circuitry
`including a partition control circuit 320 and multiplexer 325.
`Partition control circuit 320 determines Whether the array
`plane Will perform a read, a Write, an erase, or no operation
`(e.g., idle or standby). If the array plane is selected for a read
`or Write operation, partition control 320 causes multiplexer
`325 to select either the latched read or Write address,
`depending on Whether the operation is a read or a Write.
`In array plane 210, decode circuitry including Y decode
`circuitry 240, X decode circuitry 220, and block decode
`circuitry 360 receive the address signal from multiplexer
`335. Y decode circuitry 240 selects global bit lines 340
`corresponding to a column address portion of the Write
`signal. The number of selected global bit lines depends on
`number of bits simultaneously accessed in an array plane
`210. FIG. 3 illustrates accessing a single bit at a time. Global
`bit lines 340 extend to all of the blocks 212 Within the array
`plane 210, and block decode circuitry 360 connects global
`bit lines 360 to local bit lines 345 in the block 212 corre
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1025, p. 11
`
`

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`US 6,614,685 B2
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`10
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`15
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`sponding to the address signals. X decode circuitry 220 for
`the selected block 212 selects a Word line 346 connected to
`a memory cell selected for the Write or read operation.
`For a Write operation, data latches 252 latch input data
`from data pads (not shoWn) and provide the latched data
`signal via Write path 310 to every array plane 210. Write
`address latches 314 latch the Write address from address
`pads and provide the Write address to every array plane 210
`via Write address bus 312. In the array plane 210 containing
`one or more memory cell being programmed, the partition
`control circuit 330 selects the Write address for use in the
`array plane. Partition control circuit 330 also connects data
`latches 252 to Y decode circuitry 240 so that the selected
`global and local bit lines are biased to the appropriate level
`for the data bits being stored in selected memory cells.
`For a conventional programming operation using channel
`hot electron injection, X decode circuitry 220 biases the
`selected Word line of the selected memory cell to a pro
`gramming voltage Vpp (typically about 8 to 12 volts). Y
`decode circuitry 240 biases the selected global bit lines to a
`programming voltage Vcp (typically about 4 to 6 volts), and
`the source line of the selected block is grounded. Application
`of the programming voltages during a series of cycles or
`intervals raises the threshold voltage of the memory cells
`selected for programming, and sense ampli?ers 350 can
`verify Whether the threshold voltages of the selected
`memory cell has reached a target level of a programmed
`memory cell. Once the target threshold voltage is reached,
`further programming is stopped.
`For a read operation, read address latches 324 latch the
`read address from the address pads and provide the read
`address to every array plane 210 via read address bus 322.
`In an array plane 210 containing a selected memory cell
`being read, partition control circuit 330 selects the read
`35
`address for use and connects a read sense ampli?er 355 to Y
`decode circuitry 240. For a binary operation, X decode
`circuitry 220 biases the selected Word line 346 at a voltage
`Vr betWeen a high threshold voltage corresponding to a
`programmed memory cell and a loW threshold voltage
`corresponding to an erased memory cell. Sense ampli?ers
`355 generate a data output signal according to Whether sense
`ampli?ers 355 sense currents (or measure the amount of
`current for multi-bit-per-cell or analog storage) through the
`selected memory cells.
`An erase operation can generally be conducted in any of
`the array planes that are not performing a Write operation or
`a read operation. In particular, an erase operation in an array
`plane can use read sense ampli?ers 355 in the array plane for
`verify operations that determine Whether memory cells have
`reach the target threshold voltage of the erase operation, and
`the erase operation therefore does not require use of the
`Write or read data paths 310 or 320 (or to the Write or read
`addresses). According to an aspect of the present invention,
`Flash memory 200 can perform an erase operation during a
`RWW