(19) United States
`(2) Patent Application Publication (10) Pub. No.: US 2007/0070669 A1
`(43) Pub. Date:
`Mar. 29, 2007
`Tsern
`
`US 20070070669A1
`
`(54)
`
`(75)
`
`(73)
`(21)
`(22)
`
`MEMORY MODULE INCLUDING A
`PLURALITY OF INTEGRATED CIRCUIT
`MEMORY DEVICES AND A PLURALITY OF
`BUFFER DEVICES IN A MATRIX
`TOPOLOGY
`
`Inventor: Ely Tsern, Los Altos, CA (US)
`Correspondence Address:
`DENIRO/RAMBUS
`575 MARKET STREET
`SUITE 2500
`SAN FRANCISCO, CA 94105 (US)
`Assignee: Rambus Inc.
`Appl. No.:
`11/236,401
`
`Filed:
`
`Sep. 26, 2005
`
`Publication Classification
`
`(51)
`
`Int. Cl.
`GIFC 5/02
`
`(2006.01)
`
`
`
`Signal
`Path
`(Controll
`Address)
`103
`
`(52) U.S. Cl. … 365/51
`
`(57)
`
`ABSTRACT
`
`A memory module includes a plurality of signal paths that
`provide data to a memory module connector interface from
`a plurality of respective integrated circuit buffer devices that
`access data from an associated plurality of integrated circuit
`memory devices. The memory module forms a plurality of
`“data slices” or a plurality of portions of the memory module
`data bus that is coupled to the respective integrated circuit
`buffer devices. Each integrated circuit buffer device is also
`coupled to a bus that provides control information that
`specifies an access to at least one integrated circuit memory
`devices. According to an embodiment, a SPD device stores
`information regarding configuration information of the
`memory module. In embodiments, at least one integrated
`circuit buffer devices access information stored in the SPD
`device. In a package embodiment, a package houses an
`integrated circuit buffer die and a plurality of integrated
`circuit memory dies.
`
`Memory
`Module
`
`data slice a
`Memory
`Devices \,. -------------/
`
`data slice b
`
`data slice c
`
`data slice d
`
`Buffer
`100a
`
`Signal
`Path (Data)
`1.20a
`
`Path (Data)
`120 b
`
`Signal
`Path (Data)
`120C:
`
`Signal
`Path (Data)
`120d
`
`Signal
`Path
`(Controll
`Address/
`Clock)
`121
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 1
`
`

`
`Patent Application Publication Mar. 29, 2007 Sheet 1 of 18
`
`US 2007/0070669 A1
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`
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`| -61-I
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`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 2
`
`

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`Patent Application Publication Mar. 29, 2007 Sheet 2 of 18
`
`US 2007/0070669 A1
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`- - - - - - - - - - - - - - - - - - - - -* * *
`
`
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 3
`
`

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`Patent Application Publication Mar. 29, 2007 Sheet 3 of 18
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`US 2007/0070669 A1
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`
`
`k - - - - - - - - - - - - - - - - - - - -
`
`?z?
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 4
`
`

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`Patent Application Publication Mar. 29, 2007 Sheet 4 of 18
`
`US 2007/0070669 A1
`
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`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 5
`
`

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`Patent Application Publication Mar. 29, 2007 Sheet 5 of 18
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`US 2007/0070669 A1
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`
`
`G -61-I
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`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 6
`
`

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`Patent Application Publication Mar. 29, 2007 Sheet 6 of 18
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`
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`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 7
`
`

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`Patent Application Publication Mar. 29, 2007 Sheet 7 of 18
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`-- — — — — — — - — — - — - — - — - — - ~- — -4
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`
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`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 8
`
`

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`Patent Application Publication Mar. 29, 2007 Sheet 8 of 18
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`
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 9
`
`

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`Patent Application Publication Mar. 29, 2007 Sheet 9 of 18
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`US 2007/0070669 A1
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`
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`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 10
`
`

`
`Patent Application Publication Mar. 29, 2007 Sheet 10 of 18
`
`US 2007/0070669 A1
`
`Device 1000
`
`-
`Rº: |
`?&
`3.33.3%
`s
`
`3.
`
`Signal path
`1006
`(Data)
`
`_2^
`Signal path
`1005
`(Control?
`Address/Clock)
`
`
`
`/
`Signal path
`1004
`Vº
`Signal path
`1.20a
`(Data)
`
`
`
`V2
`
``s
`
`Signal path
`121
`(Control/Address/Clock)
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 11
`
`

`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 12
`
`

`
`Patent Application Publication Mar. 29, 2007 Sheet 12 of 18
`
`US 2007/0070669 A1
`
`
`
`00Z), 30?A?CI
`
`
`
`
`
`
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 13
`
`

`
`Patent Application Publication Mar. 29, 2007 Sheet 13 of 18
`
`US 2007/0070669 A1
`
`e00),
`
`
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 14
`
`

`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 15
`
`

`
`Patent Application Publication Mar. 29, 2007 Sheet 15 of 18
`
`US 2007/0070669 A1
`
`
`
`
`
`
`
`
`
`
`
`36exioedaqq Kuouuaw
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 16
`
`

`
`Patent Application Publication Mar. 29, 2007 Sheet 16 of 18
`
`US 2007/0070669 A1
`
`eInpou
`
`?uoueu0,26
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`voll
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 17
`
`

`
`Patent Application Publication Mar. 29, 2007 Sheet 17 of 18
`
`US 2007/0070669 A1
`
`
`
`Buffer Device
`100a
`
`Configuration
`Register
`Set 1881
`
`Clock
`Circuit
`1870
`
`Redundancy
`And
`Repair
`Circuit
`1883
`
`Computation
`Circuit 1865
`
`Data Cache and
`Tags Circuit
`1860
`
`SPD
`Logic and
`interface
`
`Interface
`
`Request and
`Address logic
`Circuit
`1840
`
`iqnal
`*.
`1005
`(Control
`Address
`
`Interface
`1820 b
`
`Configurable Serialization/Deserialization
`Circuit 1891
`
`Buffer
`Interface
`1103a
`
`Repeater
`Circuit
`1899
`B ypass
`Circuit
`1898
`
`Signal Path 121
`(ControllAddress/Clock)
`Fig. 18
`
`Signal Path 120a
`(Data)
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 18
`
`

`
`Patent Application Publication Mar. 29, 2007 Sheet 18 of 18
`
`US 2007/0070669 A1
`
`Signal
`Signal
`Path
`Path
`1950a ! 1951a
`(Data
`Address
`
`
`
`Signal
`Path
`
`Signal
`Path
`y
`
`Signal
`Path
`1951 b
`(Address
`
`Signal
`Path
`1950b
`(Data
`
`Memory
`Device
`1900
`2^
`
`Demux and
`Row Packet
`Decoder 1910
`
`Control
`Registers
`1911
`
`Clock
`Circuit
`1912
`
`Demux and
`Column Packet
`Decoder 1913.
`
`Column and
`Mask
`IDecoder 1915
`
`Memory Core 1900b
`Memory Interface 1900a
`
`Fig. 19
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 19
`
`

`
`US 2007/0070669 A1
`
`Mar. 29, 2007
`
`MEMORY MODULE INCLUDING A PLURALITY
`OF INTEGRATED CIRCUIT MEMORY DEVICES
`AND A PLURALITY OF BUFFER DEVICES IN A
`MATRIX TOPOLOGY
`
`FIELD OF THE INVENTION
`[0001] The present invention generally relates to inte
`grated circuit devices, high speed signaling of such devices,
`memory devices, and memory systems.
`
`BACKGROUND
`[0002] Some contemporary trends predict that processors,
`such as general purpose microprocessors and graphics pro
`cessors, will continue to increase system memory and data
`bandwidth requirements. Using parallelism in applications
`such as multi-core processor architectures and multiple
`graphics pipelines, processors should be able to drive
`increases in system bandwidths at rates some predict will be
`doubled every three years for the next ten years. There are
`several major trends in dynamic random access memory
`(“DRAM”) that may make it prohibitively costly and chal
`lenging to keep up with increasing data bandwidth and
`system memory requirements. For example, transistor speed
`relative to feature size improvements in a given DRAM
`technology node, and the rising costs of capital investment
`required to move DRAM technology to greater memory
`densities for a given DRAM die adversely affect the rate at
`which DRAM technology can keep pace with the increasing
`data bandwidth and system capacity requirements.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`[0003] Embodiments are illustrated by way of example,
`and not by way of limitation, in the figures of the accom
`panying drawings and in which like reference numerals refer
`to similar elements and in which:
`[0004] FIG. 1 illustrates a memory module topology
`including a plurality of integrated circuit memory devices
`and a plurality of integrated circuit buffer devices;
`[0005] FIG. 2 illustrates a memory module topology hav
`ing a split multi-drop control/address bus;
`[0006] FIG. 3 illustrates a memory module topology hav
`ing a single multi-drop control/address bus;
`[0007] FIG. 4 illustrates a memory module topology that
`provides data between each integrated circuit buffer device
`and a memory module connector interface;
`[0008] FIG. 5 illustrates a memory module topology
`including a plurality of integrated circuit memory devices
`and a plurality of integrated circuit buffer devices with an
`integrated circuit buffer device for control and address
`information;
`[0009] FIG. 6 illustrates termination of a control/address
`signal path in a memory module topology of FIG. 5;
`[0010] FIG. 7 illustrates termination of data signal paths in
`a memory module topology of FIG. 5;
`[0011] FIG. 8 illustrates termination of a split control/
`address signal path in a memory module topology of FIG. 5;
`[0012] FIG. 9A illustrates a top view of a memory module
`topology including a plurality of integrated circuit memory
`devices and a plurality of integrated circuit buffer devices;
`
`[0013] FIG.9B illustrates a side view of a memory module
`topology including a plurality of integrated circuit memory
`devices and a plurality of integrated circuit buffer devices;
`[0014] FIG. 9C illustrates a bottom view of a memory
`module topology including a plurality of integrated circuit
`memory devices and a plurality of integrated circuit buffer
`devices;
`[0015] FIG. 10 is a block diagram illustrating a topology
`of a device having a plurality of integrated circuit memory
`dies and an integrated circuit buffer die;
`[0016] FIG. 11 illustrates a multi-chip package (“MCP”)
`device having a plurality of integrated circuit memory dies
`and an integrated circuit buffer die;
`[0017] FIG. 12 illustrates a packaged device having a
`plurality of integrated circuit memory dies and another
`packaged device having a buffer die; both packages are
`stacked and housed together in a single package-on-package
`(“POP”) device;
`[0018] FIG. 13 illustrates a device having a plurality of
`integrated circuit memory devices and a buffer device that
`are disposed on a flexible tape;
`[0019] FIG. 14 illustrates a device having a plurality of
`integrated circuit memory dies and a buffer die that are
`disposed side-by-side and housed in a package;
`[0020] FIG. 15 illustrates a device having a plurality of
`integrated circuit memory dies and a buffer die that are
`housed in separate packages and integrated together into a
`larger POP device;
`[0021] FIG. 16 illustrates a memory module topology
`including a serial presence detect device (“SPD”);
`[0022] FIG. 17 illustrates a memory module topology with
`each data slice having an SPD;
`[0023] FIG. 18 is a block diagram of an integrated circuit
`buffer die;
`[0024] FIG. 19 is a block diagram of a memory device.
`
`DETAILED DESCRIPTION
`[0025] According to embodiments, a memory module
`includes a plurality of signal paths that provide data to a
`memory module connector from a plurality of respective
`integrated circuit buffer devices (or dies) that access the data
`from an associated plurality of integrated circuit memory
`devices (or dies). In a specific embodiment, each integrated
`circuit buffer device is also coupled to a bussed signal path
`that provides control and/or address information that speci
`fies an access to at least one integrated circuit memory
`device associated with the respective integrated circuit
`buffer device.
`[0026] According to embodiments, a memory module
`connector includes a control/address interface portion and a
`data interface portion. A control/address bus couples a
`plurality of integrated circuit buffer devices to the control/
`address interface portion. A plurality of data signal paths
`couple the plurality of respective integrated circuit buffer
`devices to the data interface portion. Each integrated circuit
`buffer device includes 1) an interface to couple to at least
`one integrated circuit memory device, 2) an interface to
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 20
`
`

`
`US 2007/0070669 A1
`
`Mar. 29, 2007
`
`couple to the control/address bus and 3) an interface to
`couple to a data signal path in the plurality of data signal
`paths.
`[0027] According to embodiments, a memory module may
`include a non-volatile memory location, for example using
`an electrically erasable programmable read only memory
`(“EEPROM") (also known as a Serial Presence Detect
`(“SPD”) device), to store information regarding parameters
`and configuration of the memory module. In embodiments,
`at least one integrated circuit buffer device accesses infor
`mation stored in the SPD device.
`[0028] In a package embodiment, a package houses an
`integrated circuit buffer die and the plurality of integrated
`circuit memory dies. In the package, a plurality of signal
`paths transfer data (read and/or write data) between the
`integrated circuit buffer die and the plurality of integrated
`circuit memory dies. The integrated circuit buffer die pro
`vides control signals from an interface of the package to the
`plurality of integrated circuit memory dies. Data stored in
`memory arrays of the plurality of integrated circuit memory
`dies is provided to a signal path disposed on the memory
`module via the integrated circuit buffer die in response to the
`control signals. In an embodiment, the package may be a
`multichip package (“MCP”). In an embodiment, the plural
`ity of integrated circuit memory dies may be housed in
`common or separate packages. In an embodiment described
`below, the memory module may include a series of inte
`grated circuit dies (i.e., memory die and buffer die) stacked
`on top of one another and coupled via a signal path.
`[0029] As described herein, an integrated circuit buffer
`device is also referred to as a buffer or buffer device.
`Likewise, an integrated circuit memory device is also
`referred to as a memory device.
`[0030] In an embodiment, an integrated circuit memory
`device is distinguished from a memory die in that a memory
`die is a monolithic integrated circuit formed from semicon
`ductor materials for storing and/or retrieving data or other
`memory functions, whereas an integrated circuit memory
`device is a memory die having at least some form of
`packaging or interface that allows the memory die to be
`accessed.
`[0031] Likewise in an embodiment, an integrated circuit
`buffer device is distinguished from a buffer die in that a
`buffer die is a monolithic integrated circuit formed from
`semiconductor materials and performs at least one or more
`buffer functions described herein, whereas an integrated
`circuit buffer device is a buffer die having at least some form
`of packaging or interface that allows communication with
`the buffer die.
`[0032] In the embodiments described in more detail
`below, FIGS. 1-8 illustrate control/address and data signal
`path topologies including a plurality of integrated circuit
`memory devices (or dies) and a plurality of integrated circuit
`buffer devices (or dies) situated on a memory module. FIGS.
`10, 18, and 19 also illustrate signal path topologies including
`integrated circuit memory devices (or dies) and integrated
`circuit buffer devices (or dies) situated on a memory module
`as well as the operation of an integrated circuit buffer device
`(or die) and memory device (or die) in embodiments among
`other things.
`[0033] FIG. 1 illustrates a memory module topology
`including a plurality of integrated circuit memory devices
`
`and a plurality of associated integrated circuit buffer devices.
`In an embodiment, a memory module 100 includes a plu
`rality of buffer devices 100a-d coupled to a common
`address/control signal path 121. Each buffer device of the
`plurality of buffer devices 100a-d provides access to a
`plurality of respective integrated circuit memory devices
`101a-d via signal paths 102a-d and 103. In an embodiment,
`respective data slices a-d are formed by one of buffers
`100a-d and sets of memory devices 101a-d. Buffer devices
`100a-d are coupled to signal paths 1.20a-d, respectively, that
`transfer data (read and write data) between the buffer devices
`100a-d and a memory module connector interface. In an
`embodiment, mask information is transferred to buffer
`devices 100a-d from a memory module connector interface
`using signal paths 120a-d, respectively.
`[0034] In an embodiment, a data slice is a portion of the
`memory module data signal path (or bus) that is coupled to
`the respective integrated circuit buffer device. The data slice
`may include the full data path or portions of data paths to and
`from a single memory device disposed on the memory
`module.
`[0035] Integrated circuit memory devices may be consid
`ered as a common class of integrated circuit devices that
`have a plurality of storage cells, collectively referred to as a
`memory array. A memory device stores data (which may be
`retrieved) associated with a particular address provided, for
`example, as part of a write or read command. Examples of
`types of memory devices include dynamic random access
`memory (“DRAM”), including single and double data rate
`synchronous DRAM, static random access memory
`(“SRAM”), and flash memory. A memory device typically
`includes request or command decode and array access logic
`that, among other functions, decodes request and address
`information, and controls memory transfers between a
`memory array and signal path. A memory device may
`include a transmitter circuit to output data for example,
`synchronously with respect to rising and falling edges of a
`clock signal, (e.g., in a double data rate type of memory
`device). Similarly, the memory device may include a
`receiver circuit to receive data, for example, synchronously
`with respect to rising and falling edges of a clock signal or
`outputs data with a temporal relationship to a clock signal in
`an embodiment. A receiver circuit also may be included to
`receive control information synchronously with respect to
`rising and falling edges of a clock signal. In an embodiment,
`strobe signals may accompany the data propagating to or
`from a memory device and that data may be captured by a
`device (e.g., memory device or buffer, or controller) using
`the strobe signal.
`[0036] In an embodiment, an integrated circuit buffer
`device is an integrated circuit that acts as an interface
`between a memory module connector interface and at least
`one integrated circuit memory device. In embodiments, the
`buffer device may store and/or route data, control informa
`tion, address information and/or a clock signal to at least one
`integrated circuit memory device that may be housed in a
`common or separate package. In an embodiment, the buffer
`isolates, routes and/or translates data, control information
`and a clock signal, singly or in combination, between a
`plurality of memory devices and a memory module connec
`tor interface. An embodiment of a memory module connec
`tor interface is described below and shown in FIGS. 9A-C.
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 21
`
`

`
`US 2007/0070669 A1
`
`Mar. 29, 2007
`
`[0037] At least one signal path 121, as shown in FIG. 1,
`disposed on memory module 100, transfers control and/or
`address (control/address) information between at least one
`of the buffer devices 100a-d and a memory module connec
`tor interface in various embodiments. In an embodiment,
`signal path 121 is a multi-drop bus. As illustrated in FIGS.
`2-8 and described below, alternate topologies for transfer
`ring control/address information, data and clock signals
`between one or more buffer devices 100a-d and a memory
`module connector interface may be used in alternate
`embodiments. For example, a split multi-drop control/ad
`dress bus, segmented multi-drop control/address bus, and
`point-to-point and/or daisy chain topologies for a data bus
`may be employed.
`[0038] In an embodiment, clock signals and/or clock
`information may be transferred on at least one signal line in
`signal path 121. These clock signal(s) provide one or more
`clock signals having a known frequency and/or phase. In an
`embodiment, a clock signal is synchronized with or travels
`along side the control/address information. In an embodi
`ment, an edge of the clock signal has a temporal relationship
`with an edge of a control/address signal representing the
`control/address information. In an embodiment, a clock
`signal is generated by a clock source, master device (e.g.,
`controller device) and/or buffer device.
`[0039] In an embodiment, a clock signal and/or clock
`information may be transferred on at least one signal line in
`respective signal paths 120a-d. Buffer devices 100a-d may
`receive and/or transmit a clock signal with data on signal
`paths 120a-b. In an embodiment, write data is provided to
`buffer devices 100a-d on signal paths 1.20a-d and a clock
`signal is provided on signal path 120a-d along side write
`data. In an embodiment, a clock signal (such as a clock-to
`master (“CTM’”)) is provided from buffer devices 100a-d on
`signal path 120a-d along side read data on signal paths
`120a-d. In an embodiment, a clock signal is synchronized
`with or travels along side the write and/or read data. An edge
`of the clock signal has a temporal relationship or is aligned
`with an edge of a data signal representing write and/or read
`data. Clock information can be embedded in data, eliminat
`ing the use of separate clock signals along with the data
`signals.
`[0040] In an embodiment, a read, write and/or bidirec
`tional strobe signal may be transferred on at least one signal
`line in respective signal paths 1.20a-d. Buffer devices 100a-d
`may receive and/or transmit a strobe signal with data on
`signal paths 120a-b. In an embodiment, write data is pro
`vided to buffer devices 100a-d on signal paths 120a-d and a
`strobe signal is provided on signal path 120a-d along side
`write data. In an embodiment, a strobe signal is provided
`from buffer devices 100a-d on signal path 120a-d along side
`read data on signal paths 120a-d. In an embodiment, a strobe
`signal is synchronized with or travels along side the write
`and/or read data. An edge of the strobe signal has a temporal
`relationship or is aligned with an edge of a data signal
`representing write and/or read data.
`[0041] In an embodiment, addresses (for example, row
`and/or column addresses) for accessing particular memory
`locations in a particular integrated circuit memory device
`and/or commands are provided on signal path 121 from a
`memory module connector interface. In an embodiment, a
`command relates to a memory operation of a particular
`
`integrated circuit memory device. For example, a command
`may include a write command to store write data at a
`particular memory location in a particular integrated circuit
`memory device and/or a read command for retrieving read
`data stored at a particular memory location from a particular
`integrated circuit memory device. Also, multiple memory
`devices in different data slices can be accessed simulta
`neously. In embodiments, a command may include row
`commands, column commands such as read or write, mask
`information, precharge and/or sense command. In an
`embodiment, control information is transferred on signal
`path 121 over a common set of lines in the form of a time
`multiplexed packet where particular fields in the packet are
`used for including command operation codes and/or
`addresses. Likewise, packets of read data may be transferred
`from integrated circuit memory devices via buffers 100a-d
`on respective signal paths 120a-d to memory module con
`nector interface. In an embodiment, a packet represents one
`or more signals asserted at particular bit windows (or a time
`interval) for asserting a signal on particular signal lines.
`[0042] In embodiments, memory module 100 communi
`cates (via a memory module connector interface) with a
`master device (e.g., a processor or controller).
`[0043] FIG. 2 illustrates an embodiment of a memory
`module topology having a split multi-drop control/address/
`clock bus. In particular, memory module 200 includes a split
`multi-drop control/address bus 221 coupled to buffers
`100a-d and a memory module connector interface. With
`reference to FIG. 2, a first portion of bus 221 is terminated
`by termination 230 and a second portion of bus 221 is
`terminated by termination 231. In an embodiment, the
`impedance of termination 230 matches the impedance of the
`first portion of bus 221 (Z0) coupled to buffers 100c-d and
`the impedance of termination 231 matches the impedance of
`the second portion of bus 221 (Z1) coupled to buffers
`100a-b. In an embodiment, impedance Z0 equals impedance
`Z1. In embodiments, terminations 230 and 231, singly or in
`combination, are disposed on memory module 100, buffer
`devices 100a and 100d or packages used to house buffer
`devices 100a and 100d.
`[0044] FIG. 3 illustrates a memory module topology hav
`ing a single multi-drop control/address/clock bus terminated
`by termination 330. In an embodiment, the impedance of
`termination 330 matches the impedance of signal path 121
`(or control/address/clock bus). In embodiments, termination
`330, singly or in combination, is disposed on memory
`module 300 or on buffer device 100d.
`[0045] FIG. 4 illustrates a memory module topology that
`provides data between each integrated circuit buffer device
`and a memory module connector interface. In an embodi
`ment, each signal path 120a-d is terminated by an associated
`termination 420a-d, respectively. In an embodiment, termi
`nations 420a-d have respective impedances that match the
`impedance Z0 of each of the signal paths 1.20a-d. In embodi
`ments, terminations 420a-d, singly or in combination, are
`disposed on memory module 400, each of buffer devices
`100a-d or packages used to house buffer devices 100a-d.
`[0046] Referring to FIG. 1, a control/address signal rate
`ratio of signal path 121 to signal path 103 may be 2:1 (or
`other multiples such as 4:1, 8:1, etc.) so that a memory
`module connector interface is able to operate as fast as
`specified while memory devices 101a-d may operate at half
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1016, p. 22
`
`

`
`US 2007/0070669 A1
`
`Mar. 29, 2007
`
`(quarter, eighth, etc.) the control/address signaling rate so
`that relatively lower cost memory devices may be used.
`Similarly, a data signal rate of one of signal paths 102a-d to
`one of signal paths 120a-d may be 2:1 (or other multiple
`such as 4:1, 8:1, etc.) so that a memory module connector
`interface is able to operate as fast as specified while memory
`devices 101a-d may operate at half (quarter, eighth, etc.) the
`data signaling rate so that relatively lower cost memory
`devices may be used.
`[0047] FIG. 5 illustrates a memory module topology
`including a plurality of integrated circuit memory devices
`and a plurality of integrated circuit buffer devices with an
`integrated circuit buffer device 501 for control, address
`and/or clock information. Memory module 500 is similar to
`memory module 100 except that buffer device 501 is
`coupled to signal paths 121 and 121a-b. Buffer device 501
`outputs control, address and/or clock information to buffer
`devices 100a-b on signal path 121a and to buffer devices
`100c-d on signal path 121b. In an embodiment buffer device
`501 copies control, address and/or clock information
`received on signal path 121 and repeats the control, address
`and/or clock information on signal paths 121a-b. In an
`embodiment, buffer device 501 is a clocked buffer device
`that provides a temporal relationship with control and
`address information provided on signal paths 121a-b. In an
`embodiment, signal paths 121a-b include at least one signal
`line to provide a clock signal and/or clock information. In an
`embodiment, buffer device 501 includes a clock circuit 1870
`as shown in FIG. 18. In an embodiment, buffer device 501
`receives control information, such as a packet request, that
`specifies an access to at least one of the integrated circuit
`memory devices 101a-d and outputs a corresponding control
`signal (on signal path 121a and/or 121b) to the specified
`integrated circuit memory device.
`[0048] FIG. 6 illustrates a memory module topology simi
`lar to that illustrated in FIG. 5 except that a termination 601
`is coupled to signal path 121 on memory module 600. In an
`embodiment, the impedance of termination 601 matches the
`impedance Z0 of signal path 121. In embodiments, termi
`nation 601 is disposed on memory module 600, buffer
`device 501 or a package used to house buffer device 501.
`[0049] FIG. 7 illustrates a memory module topology that
`provides data to and/or from each integrated circuit buffer
`device and terminations coupled to signal paths. In an
`embodiment, each signal path 120a-d is terminated by
`associated terminations 701a-d, respectively. In an embodi
`ment, terminations 701a-d have respective impedances that
`match the impedance Z0 of each of the signal paths 120a-d.
`In embodiments, terminations 701a-d, singly or in combi
`nation, are disposed on memory module 700, buffer devices
`100a-d or packages used to house buffer devices 100a-d.
`[0050] FIG. 8 illustrates a memory module topology hav
`ing a split multi-drop signal path between a buffer device for
`control, address and/or clock information and the plurality
`of buffer devices. In particular, memory module 800
`includes a split multi-drop control/address bus 121a-b
`coupled to buffers 100a-d and a buffer device 501. In an
`embodiment, a first portion of bus 121a is terminated by
`termination 801 and a second portion of bus 121b is termi
`nated by termination 802. In an embodiment, the impedance
`of termination 801 matches the impedance of the first leg
`(Z0) and the impedance of termination 802 matches the
`
`impedance of the second leg (Z1). In an embodiment,
`impedance Z0 equals impedance Z1. In embodiments, ter
`minations 801 and 802, singly or in combination, are dis
`posed on memory module 800, buffer devices 100a and
`100d or packages used to house buffer devices 100a and
`100d.
`[0051] Referring to FIG. 5, a control/address signal rate
`ratio of signal path 121 to signal path 121a (or 121b) to
`signal path 103 may be 2:1:1 (or other multiples such as
`4:1:1, 8:1:1, etc.) so that other multi-drop bus topology
`embodiments using signal paths 121a (or 121b) and signal
`path 103 do not have to necessarily operate as high a signal
`rate as an embodiment that uses signal path 121 as shown in
`FIG. 1. Also like FIG. 1, a control/address signal rate ratio
`of signal path 121 to signal path 103 may be 2:1 (or other
`multiples such as 4:1, 8:1, etc.) so that a memory module
`connector interface is able to operate as fast as specified
`while memory devices 101a-d may operate at half (or
`quarter, eighth, etc.) the control/address signaling rate so
`that relatively lower cost memory devices may be used.
`Similarly, a data signal rate of one of signal paths 102a-d to
`one of signal paths 120a-d may be 2:1 (or other multiple
`such as 4:1, 8:1, etc.) so that a memory module connector
`interface is able to operate as fast as the specified signaling
`rate while memory devices 101a-d may operate at half (or
`quarter, eighth, etc.) the data signaling rate so that relatively
`lower cost memory devices may be used.
`[0052] FIG. 9A illustrates a top view of a memory module
`topology including a plurality of integrated circuit memory
`devices and a plurality of integrated circuit buffer devices
`coupled to a connector interface. In an embodiment,
`memory module 900 includes a substrate 910 having a
`standard dual in-line memory module (“DIMM’’) form fac
`tor or other module form factor standards, such as small
`outline DIMM (“SO-DIMM’’) and very low profile DIMM
`(“VLP-DIMM’’)