(19) United States
`(2) Patent Application Publication (10) Pub. No.: US 2003/0028733 A1
`Tsunoda et al.
`(43) Pub. Date:
`Feb. 6, 2003
`
`US 20030028733A1
`
`(54) MEMORY APPARATUS
`
`(30)
`
`Foreign Application Priority Data
`
`Jun. 13, 2001 (JP)...................................... 2001-177924
`Jul. 13, 2001 (JP)...................................... 2001–213639
`Jul. 13, 2001 (JP)...................................... 2001–213640
`Publication Classification
`(51) Int. Cl." … G06F 12/00
`(52) U.S. Cl. .......................... 711/154; 711/156; 711/103;
`711/105
`
`(57)
`
`ABSTRACT
`
`(75) Inventors: Motoyasu Tsunoda, Sagamihara (JP),
`Shinya Iguchi, Fujisawa (JP); Junichi
`Maruyama, Yokohama (JP); Kazuo
`Nakamura, Fussa (JP)
`
`Correspondence Address:
`TOWNSEND AND TOWNSEND AND CREW,
`LLP
`TWO EMBARCADERO CENTER
`
`EIGHTH FLOOR
`
`SAN FRANCISCO, CA 94111-3834 (US)
`
`(73) Assignee: Hitachi, Ltd., Tokyo (JP)
`(21) Appl. No.:
`10/172,096
`
`(22) Filed:
`
`Jun. 13, 2002
`
`-
`
`-
`
`-
`
`A memory apparatus having a volatile memory for storing
`data from a host, a nonvolatile memory capable of storing
`the data stored in the volatile memory, and electrically
`deleting the data, and a control circuit for controlling data
`transfer between the volatile memory and the nonvolatile
`memory. A capacity of a data storage area of the volatile
`memory is larger than that of a data storage area of the
`nonvolatile memory.
`
`1 01
`
`MEMORY APP
`ARATUS
`
`
`
`FLASH MEMORY ||F CONTROL UNIT
`ECC
`ALTERNATIVE
`SECTOR
`CONTROL
`?áš?" | |39NTHQL
`CIRCUIT
`
`FLASH
`MEMORY
`
`
`
`
`
`
`
`
`
`
`
`DATA TRANSFER CONTROL UNIT
`
`CONTROL
`CRCUIT
`
`
`
`DATABUFFER
`
`
`
`
`
`MEMORY CONTROL UNIT
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 1
`
`

`
`Patent Application Publication
`
`Feb. 6, 2003 Sheet 1 of 26
`
`US 2003/0028733 A1
`
`
`
`
`
`LINT) TOHINOO WHO'NEW
`
`
`
`LINT? TOHINOO HE-ÏSNWHL WLWG
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 2
`
`

`
`Patent Application Publication
`
`Feb. 6, 2003 Sheet 2 of 26
`
`US 2003/0028733 A1
`
`GOZ
`
`. . . . . . . . . . . . . . . HOE)}{\/]:HË?SNW?i?. . . . . . . . . . . . . . .
`
`
`
`Å HOWEW HSWTHVNV/H CIS
`
`
`
`
`
`(WIWO HESn) WEHWETLIWTONNON
`
`9.OZ ~ || HOW~ 0 || Z.
`
`
`
`(WIWQ WWH9OHd)WEHWETLIWTON902
`
`
`
`
`
`
`
`WEHW XIHOM WE||SÅS| 02
`
`psgqw , -403
`
`~) 602
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 3
`
`

`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 4
`
`

`
`Patent Application Publication
`
`Feb. 6, 2003 Sheet 4 of 26
`
`US 2003/0028733 A1
`
`
`
`| NEALNOO
`
`
`
`|Off --~~~~ 9NISSHOOHd 9NIOS)-NO
`
`
`
`
`
`
`
`
`
`
`
`
`
`90ff; —~~ HIGISSÍOd SWM NOLLOEHH00 QNW 'EQWW SWM NOLLOEHHOO OOH
`
`
`
`
`
`
`
`
`
`
`
`ZO?7 ~~ CINE TWINHON
`
`907 ~ HHVAS
`
`
`
`
`
`
`
`#70; ~~~~ HT8ISSOdWI SWM NO|1OHHHOO 108 ‘EQWW SWM NOILOBHHOO OOB
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`G0V~~~ (HEAO BWIL) ET?ISSOdWI NOILITOEXE ONISSEOOHd
`
`
`
`
`
`
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 5
`
`

`
`Patent Application Publication
`
`Feb. 6, 2003 Sheet 5 of 26
`
`US 2003/0028733 A1
`
`
`
`
`
`LO!--~~~ SñIWHWddw AHOWEW
`
`
`
`G
`
`
`GNWWW.OO HOWE
`SONISSE OOHd
`
`
`
`9NISSE OOHd HO 9NILIHM
`ÁÁÁ SSEHOGY NI LINSEE
`
`
`C?NE Å LITW.WHON 8W
`HO ÅHLEH
`
`XXX SSH HOCIW
`
`5) NI LIHM
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 6
`
`

`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 7
`
`

`
`Patent Application Publication
`
`Feb. 6, 2003 Sheet 7 of 26
`
`US 2003/0028733 A1
`
`Z
`
`
`
`ECOW WWHOS
`
`90/ N
`
`
`
`
`
`
`
`
`
`BOJOW B}}{\SWHE WIWO HSWTH
`
`
`
`
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 8
`
`

`
`Patent Application Publication
`
`Feb. 6, 2003 Sheet 8 of 26
`
`US 2003/0028733 A1
`
`$ LOS
`
`HINDI +—
`
`0 LOS
`
`708
`
`Z08
`
`
`
` 4 Å HOWEW HSWTH
`
`| WWHOIS A
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 9
`
`

`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 10
`
`

`
`Patent Application Publication
`
`Feb. 6, 2003 Sheet 10 of 26
`
`US 2003/0028733 A1
`
`
`
`TOHI NOO
`
`-||| OW|W
`
`-||||WWHOS
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 11
`
`

`
`Patent Application Publication
`
`Feb. 6, 2003 Sheet 11 of 26
`
`US 2003/0028733 A1
`
`
`
`
`
`||N?A TOHINOO - || CIS
`
`|
`
`* * * - - - - - - - - - - - - - - * * * * - - - * * * * - - - - - - - - - - -
`
`90 || ||
`
`Z0 || ||
`
`80 || ||
`
`60 || ||
`
`0 || || ||
`
`Z || || ||
`
`$ | | |
`
`50NIGNOdSGHHOO
`
`
`
`(]}{\/O CIS
`
`| SOH
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 12
`
`

`
`Patent Application Publication
`
`Feb. 6, 2003 Sheet 12 of 26
`
`US 2003/0028733 A1
`
`LINTI TOHINOO
`
`HE-ÏSNWHL W LWCH
`
`
`
`
`
`... — — — — — — —
`
`* * * * = ** = *-* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
`
`602 ||
`
`0 | Z |
`
`Z || ||
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 13
`
`

`
`Patent Application Publication
`
`Feb. 6, 2003 Sheet 13 of 26
`
`US 2003/0028733 A1
`
`
`
`
`
`STILVHWc{dW W?OWE W
`
`
`
`
`
`LIN?) TOHINOO OWN
`
`
`
`LÍNÍ TOHINOO HE-ÏSNWHL WIWO
`
`
`
`
`
`
`
`
`
`1{N?A TOH1NOO - || Å HOWEW HSWTH
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 14
`
`

`
`Patent Application Publication
`
`Feb. 6, 2003 Sheet 14 of 26
`
`US 2003/0028733 A1
`
`
`
`
`
`LINQ TOHINOO Å HOWE||N
`
`
`
`|INTI TOH1NOO H/I ÅHOWEW HSWTH
`
`
`
`
`
`
`
`
`
`LINTI TOHINOO HE-ÏSNWHL W 1\/(]
`
`
`
`LINTI TOHINOO H/I OWW
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 15
`
`

`
`Patent Application Publication
`
`Feb. 6, 2003 Sheet 15 of 26
`
`US 2003/0028733 A1
`
`
`
`
`
`| E-H WEIHW
`
`WS WEIHW
`
`ES WEBW
`
`WWHOIS
`
`909 ||
`
`909 ||
`
`
`
`
`
`
`
`(WIWQ WWHOHOHd) WEHW ETIIWTON
`
`
`
`(WLWG HESn) WBHW ETIIVIOANON
`
`
`
`
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 16
`
`

`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 17
`
`

`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 18
`
`

`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 19
`
`

`
`Patent Application Publication
`
`Feb. 6, 2003 Sheet 19 of 26
`
`US 2003/0028733 A1
`
`
`
`ÅHOWEW HSWTH ~ ZO !
`
`90 || ~ VNV HOS
`
`
`
`
`
`170 || ~ ~ |INTI TOHINOO ÅHWEW
`
`
`
`| || ~ ~ ISOH
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 20
`
`

`
`Patent Application Publication
`
`Feb. 6, 2003 Sheet 20 of 26
`
`US 2003/0028733 A1
`
`
`
`
`
`
`
`ÅHOWEW HSWTH :20|| ~ Z0 || 9:0 || ~ VNV HOS#70 || ~ ~ LINQ TOHINOO KHOWEW | | |~~~~ ISOH
`
`
`
`
`
`
`
`ET TWA CJ
`
`
`
`
`
`
`
`
`
`
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 21
`
`

`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 22
`
`

`
`Patent Application Publication
`
`US 2003/0028733 A1
`
`
`
`MHOWEW HSVIH ? ZO || 90 || ~ WWHO'S VO || ~ LINTI TOHINOO AHOWEW || || || ~ ISOH
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`| OZZ
`
`
`
`?70ZZ9NISSE|00}}d d'OIS Å HOWEW
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 23
`
`

`
`Patent Application Publication
`
`Feb. 6, 2003 Sheet 23 of 26
`
`US 2003/0028733 A1
`
`909 Z
`
`8093
`
`
`
`
`
`ZO || ~ Å HOWEW HSWTHWVHCIS ~90 ||†70 || ~ ||N?A TOHINOO Å HOWEW
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`C||TWA 9NITHNET HVENA
`
`&
`
`
`
`
`
`Z09Z
`
`£)NISSE OORHd
`
`HOHHE
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 24
`
`

`
`Patent Application Publication
`
`Feb. 6, 2003 Sheet 24 of 26 US 2003/0028733 A1
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`4040
`
`i.gºlf
`#ace MEMORY APPARATUS
`4001
`4030 "460%
`4000
`| CONTROL UNIT
`HOST ?
`
`
`
`4040
`
`4003 FLASH MEMORY INTERFACE
`
`4061
`4020
`/
`4010
`FLASH MEMORY
`sp#AM STARINGoFPowehsupply
`4021
`
`
`
`REGISTER
`READING
`4052
`
`
`
`
`
`
`
`
`
`
`
`
`
`WOLATLE
`AREA
`
`
`
`4063 %
`STORE > 4064 %
`CONTROL
`STOP OF POWER #
`~4065_j STOHAGE
`SUPPLY
`4071
`AREA
`REGSISTER
`SAVING
`
`4022
`
`REGISTER WRITING
`
`REGISTER RETURN
`
`4031
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 25
`
`

`
`Patent Application Publication
`
`Feb. 6, 2003 Sheet 25 of 26 US 2003/0028733 A1
`
`STARTING OF POWER
`SUPPLY FROMHOST
`
`4101
`
`SETTING OF BUSYSIGNAL IN
`CONTROL REGISTER
`
`4102
`
`o – Špplied power supplywoºtºGB-s:4103
`
`BECOME PREDETERMINED WALUE 2
`Yes
`READINGO.g.QTHOHREGISTER FROM39NOL || 4104
`REGISTER STORAGE AREA OF FLASH MEMORY
`
`LOADING OF MIRROR AREA DATA OF FLASH MEMORY
`IN NONVOLATILE AREA OF SDRAM BASED ON READ
`CONTROL REGISTER INFORMATION
`
`41 05
`
`RELEASING OF BUSY SIGNAL
`FROM CONTROLREGISTER
`
`41 06
`
`RECEIVING OF SHUT-DOWN
`INSTRUCTION FROM HOST 7
`
`41 O7
`
`Yes
`
`NORMAL OPERATION OF
`MEMORY APPARATUS
`SSUANCEBUSYSIGNAL SETIN || 4109
`CONTROLREGISTER
`
`
`
`STROING OF NONVOLATILE AREA DATA OF
`SDRAM IN MIRROR AREA OF FLASH MEMORY
`BASED ON CONTROLREGISTER INFORMATION
`
`41 10
`
`WRITING OF CONTROLREGISTER IN CONTROL
`REGISTER STORAGE AREA
`
`41 11
`
`RELEASING OF BUSYSIGNAL
`FROM CONTROLREGISTER
`
`
`
`
`
`41 12
`
`STOP OF POWER SUPPLY FROM HOST
`
`41 13
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 26
`
`

`
`Patent Application Publication
`
`Feb. 6, 2003 Sheet 26 of 26 US 2003/0028733 A1
`
`FIG.26
`
`NORMALOPERATION OF
`MEMORY APPARATUS
`
`
`
`SDRAMACCESS
`RECEVING FROM HOST
`
`
`
`
`
`PASSING-THROUGH OF
`SDRAM INTERFACESIGNAL
`
`
`
`42O7
`
`OUTPUTTING OF
`WRITING IN
`COTROLREGISTER CONTROLREGISTER
`| TO HOST
`
`
`
`EXECUTION OF OPERATION
`INSTRUCTION FROM HOST
`
`4206
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 27
`
`

`
`US 2003/0028733 A1
`
`Feb. 6, 2003
`
`MEMORY APPARATUS
`
`BACKGROUND OF THE INVENTION
`[0001] The present invention relates to a memory appara
`tus, which uses a volatile memory and a nonvolatile
`memory, and to a construction of a high-speed and inex
`pensive memory system.
`[0002] In a memory system using a volatile memory and
`a nonvolatile memory, as described in JP-A-2001-5723, a
`method is available, in which a content of the nonvolatile
`memory is copied in the volatile memory when power is
`turned ON, and the volatile memory is accessed from a host
`and used. In this case, when power is turned OFF, a content
`of the volatile memory is copied in the nonvolatile memory,
`and a result of its processing is notified through an exclusive
`line to the host. Accordingly, power is safely turned OFF,
`and data is held even after the power is OFF.
`[0003] In the above-described conventional art, data trans
`fer between the volatile memory (DRAM) and the nonvola
`tile memory (flash memory) is carried out only when the
`power is turned ON or OFF Thus, no consideration has been
`given to execution of the data transfer during use of the
`memory system after the power is ON. As the data transfer
`targets all the nonvolatile memories, transfer to a large
`capacity memory takes time, and preparation until the
`memory system is ready to be used takes long. In the
`power-OFF state, since the exclusive line is used to notify
`the end of copying processing to the host, control is impos
`sible by using only an existing nonvolatile memory inter
`face. In addition, no consideration has been given to access
`ing of the nonvolatile memory from the host. Furthermore,
`no consideration has been given to a difference between a
`data transfer speed of the volatile memory and a data transfer
`speed of the nonvolatile memory.
`
`SUMMARY OF THE INVENTION
`[0004] An object of the present invention is to provide a
`memory apparatus, which enables a host to control data
`transfer between a volatile memory and a nonvolatile
`memory, and controllability from the host to be improved.
`[0005] Another object of the present invention is to pro
`vide a memory apparatus, which enables a host to access a
`nonvolatile memory, and controllability from the host to be
`improved.
`[0006] In accordance with the present invention, a control
`circuit receives a command from a host, interprets it, and
`starts data transfer between a volatile memory and a non
`volatile memory according to the interpreted command.
`[0007] In accordance with the present invention, the con
`trol circuit starts data transfer between the volatile memory
`and the nonvolatile memory according to an access com
`mand (including data reading and writing) to a predeter
`mined address on the volatile memory from the host.
`[0008] In accordance with the present invention, a first
`interface positioned between the host and the control circuit
`inputs/outputs data read/written in the volatile memory, and
`a second interface positioned between the host and the
`control circuit inputs/outputs data read/written in the non
`volatile memory.
`
`[0009] In accordance with the present invention, an inter
`face positioned between the host and the control circuit
`inputs/outputs data read/written in the volatile memory, and
`data read/written in the nonvolatile memory.
`[0010] In accordance with the present invention, a holding
`circuit holds data transferred between the volatile memory
`and the nonvolatile memory.
`[0011] Other objects, features and advantages of the
`invention will become apparent from the following descrip
`tion of the embodiments of the invention taken in conjunc
`tion with the accompanying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`[0012] FIG. 1 is a view showing an internal configuration
`of a memory apparatus according to the present invention.
`[0013] FIG. 2 is a view showing address spaces of an
`SDRAM and a flash memory according to the present
`invention.
`[0014] FIG. 3 is a view showing an example of a group of
`commands according to the present invention.
`[0015] FIG. 4 is a view showing an example of status/
`error information according to the present invention.
`[0016] FIG. 5 is a processing flowchart of a host and the
`memory apparatus according to the present invention.
`[0017] FIG. 6 is a view showing an internal configuration
`of a data transfer control unit according to the present
`invention.
`[0018] FIG. 7 is a view showing status transition of a
`sequencer according to the present invention.
`[0019] FIG. 8 is a timing chart of data transfer according
`to the present invention.
`[0020 FIG. 9 is a view showing an internal configuration
`of another memory apparatus according to the present
`invention.
`[0021] FIG. 10 is a view showing a terminal configuration
`of an MMC interface according to the present invention.
`[0022] FIG. 11 is a view showing a terminal configuration
`of an SD card interface according to the present invention.
`[0023] FIG. 12 is a view showing a terminal configuration
`of a memory stick interface according to the present inven
`tion.
`[0024] FIG. 13 is a view showing an internal configura
`tion of yet another memory apparatus according to the
`present invention.
`[0025] FIG. 14 is a view showing an internal configura
`tion of yet another memory apparatus according to the
`present invention.
`[0026] FIG. 15 is a view showing address spaces of an
`SDRAM and a flash memory according to the present
`invention.
`[0027] FIG. 16 is a view showing an address space
`management table of the SDRAM and the flash memory
`according to the present invention.
`[0028] FIG. 17 is a view showing a detail of the address
`space management table according to the present invention.
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 28
`
`

`
`US 2003/0028733 A1
`
`Feb. 6, 2003
`
`[0029] FIG. 18 is a flowchart of processing when a host
`and the memory apparatus are started according to the
`present invention.
`[0030] FIG. 19 is a flowchart of processing when the
`address space management table of the host and the memory
`apparatus is updated according to the present invention.
`[0031] FIG.20 is a flowchart of processing when host data
`is written at the host and the memory apparatus according to
`the present invention.
`[0032] FIG. 21 is a flowchart of processing when data is
`written in the flash memory of the memory apparatus
`according to the present invention.
`[0033] FIG. 22 is a flowchart of processing when opera
`tions of the host and the memory apparatus are finished
`according to the present invention.
`[0034] FIG. 23 is a flowchart of processing when data is
`read from the flash memory of the memory apparatus
`according to the present invention.
`[0035] FIG.24 is a view showing a configuration example
`of the memory apparatus according to the present invention.
`[0036] FIG. 25 is a flowchart showing an example of
`processing from a start of power supply to a stop of the
`power supply at the memory apparatus according to the
`present invention.
`[0037] FIG. 26 is a flowchart showing an example of
`processing of an SDRAM compatible memory operation at
`the memory apparatus according to the present invention.
`
`DESCRIPTION OF THE EMBODIMENTS
`[0038] A memory apparatus 4000 shown in FIG. 24 can
`be mounted on an information terminal such as a portable
`telephone set, personal digital assistants (PDA), a music
`player, a digital camera, a digital video camera, a set top box,
`a personal computer, or a car navigation system.
`[0039] The memory apparatus 4000 includes a function of
`writing data designated by a host 4040 in an address
`designated by the host 4040, a function of holding the
`written data for at least a fixed period or more when power
`is supplied, and a function of outputting the data held in the
`address designated by the host 4040 to the host 4040. This
`memory apparatus 4000 also has nonvolatility for holding a
`part or all of the written data even if power supply is
`stopped, and includes a function, which enables the host
`4040 of the memory apparatus 4000 to designate an address
`for the memory apparatus 4000, write data therein, and read
`data therefrom, by an interface 4001 at least having electric
`compatibility with a synchronous dynamic random access
`memory (SDRAM)
`[0040] In this case, the host 4040 is an information pro
`cessor such as a CPU or ASIC incorporated in the informa
`tion terminal. In the memory apparatus 4000, operation
`programs for, for example, enabling the host 4040 to execute
`various information processing, can be stored.
`[0041] The operation programs are various applications
`for, for example an operating system (OS), a driver, a JAVA
`virtual machine, a JAVA applet, and the like. The informa
`tion processing may be, for example, operation control of
`each hardware constituting the information terminal, a data
`
`operation, recording/reproducing of a moving image or a
`voice, or the like. The host 4040 can operate based on the
`operation programs stored in the memory apparatus 4000 by
`using the memory apparatus 4000 as a main memory. In the
`memory apparatus 4000, various data for processing by, for
`example, the operation programs, can also be stored. Here,
`the data are various data such as a text, an image, a voice,
`a moving image and the like, or operation parameters/setting
`files of the programs. Other data can also be stored.
`[0042] The memory apparatus 4000 is a volatile memory,
`but it includes an SDRAM 4010 to be accessed randomly, a
`flash memory 4020 as a nonvolatile memory, an SDRAM
`compatible interface 4001 for enabling the host 4040 to
`access the memory apparatus 4000. The memory apparatus
`4000 is connected through the SDRAM compatible interface
`4001 to the host 4040. Since the memory apparatus 4000
`operates as an SDRAM compatible memory, the host 4040
`can control the memory apparatus 4000 by using the
`SDRAM compatible interface. The memory apparatus 4000
`can store a part or all of the data of the SDRAM 4010 in the
`flash memory 4020. The memory apparatus 4000 can read a
`part or all of the data of the flash memory 4020. For
`example, if the data of the SDRAM 4010 is stored in the
`flash memory 4020 before the power supply to the memory
`apparatus 4000 is stopped, a data loss of the SDRAM 4010
`caused by a stop of the power supply can be prevented. In
`addition, for example, if the data of the flash memory 4020
`is read to the SDRAM 4010 before the host 4040 accesses
`the memory apparatus 4000 after the power supply to the
`memory apparatus 4000 is started, the host 4040 can use the
`memory apparatus 4000 as a nonvolatile SDRAM compat
`ible memory. The memory apparatus 4000 includes a func
`tion for enabling the host 4040 to optionally designate data
`transfer between the SDRAM 4010 and the flash memory
`4020. The memory apparatus 4000 also includes an instruc
`tion receiving function of receiving its operation instruction
`from the host 4040, and a status notifying function of
`notifying a status of the memory apparatus 4000 to the host
`4040.
`[0043] The instruction receiving function and the status
`notifying function are made operable when the host 4040
`reads/writes data of a predetermined format in a predeter
`mined address of the memory apparatus 4000. Thus, since it
`can use the instruction receiving function and the status
`notifying function without adding any new dedicated pins
`for giving an instruction to the memory apparatus 4000 to
`the SDRAM interface, the host 4040 can easily replace the
`existing SDRAM 4010 and the memory apparatus 4000. The
`host 4040 of the memory apparatus 4000 can instruct the
`memory apparatus 4000 to transfer the data of the SDRAM
`4010 to the flash memory 4020, and the data of the flash
`memory 4020 to the SDRAM 4010 by the instruction
`receiving function as occasion demands.
`[0044] The memory apparatus 4000 includes a data stor
`age area having nonvolatility, thus providing high conve
`nience. As a transfer speed equal to that of the normal
`SDRAM 4010 is provided, transfer time can be shorted
`compared with the case of direct access to the flash memory.
`Since the memory apparatus 4000 includes the SDRAM
`compatible interface 4001, the host 4040 having the
`SDRAM interface can use the memory apparatus 4000
`without any new designing or addition of hardware.
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 29
`
`

`
`US 2003/0028733 A1
`
`Feb. 6, 2003
`
`[0045] Next, an example of a function of the memory
`apparatus 4000 will be described.
`[0046] The memory apparatus 4000 includes a function of
`passing through a signal of the SDRAM compatible inter
`face 4001 to a signal of the SDRAM interface 4002 of the
`SDRAM 4010. By such pass-through function of the signal
`of the SDRAM compatible interface 4001, the host 4040 can
`use the memory apparatus 4000 as the SDRAM compatible
`memory apparatus 4000. For example, by a process similar
`to that of the SDRAM 4010, the host 4040 can issue a
`reading command, a writing command, a refreshing com
`mand or the like to the memory apparatus 4000. The
`memory apparatus 4000 includes a storage function of
`transferring data held in a predetermined area of the
`SDRAM 4010 to a predetermined area of the flash memory
`4020. By the storage function, the data transferred to the
`flash memory 4020 can be held on the flash memory 4020
`even if it is lost from the SDRAM 4010 because of a stop of
`the power supply to the memory apparatus 4000.
`[0047] The storage function is executed when an operation
`status of the memory apparatus 4000 satisfies predetermined
`storage execution conditions. One of the storage execution
`conditions is, for example a stop of the power supply. One
`of the storage conditions is, for example issuance of a
`storage execution instruction from the host 4040. One of the
`storage execution conditions is, for example taking of a
`value of a predetermined range by a predetermined register
`of the memory apparatus 4000. The predetermined register
`is, for example a counter register for counting the number of
`times of accessing the memory apparatus 4000 by the host
`4040.
`[0048] The memory apparatus 4000 has storage execution
`condition information for defining a storage execution con
`dition. The memory apparatus 4000 includes a function of
`changing the storage execution condition information. The
`memory apparatus 4000 includes a function for enabling the
`host 4040 to designate changing of the storage execution
`information. The memory apparatus 4000 includes a func
`tion of saving the storage execution information in the flash
`memory 4020. The memory apparatus 4000 includes a
`function of reading the storage execution condition infor
`mation from the flash memory 4020. The memory apparatus
`4000 includes a load function of transferring data held in a
`predetermined area of the flash memory 4020 to a prede
`termined area of the SDRAM 4010.
`[0049] The load function is executed when an operation
`status of the memory apparatus 4000 satisfies a predeter
`mined load execution condition. One of the load execution
`conditions is, for example a start of the power supply. One
`of the load execution conditions is, for example issuance of
`a load execution instruction from the host 4040. One of the
`load execution conditions is, for example taking of a value
`of a predetermined range by a predetermined register of the
`memory apparatus 4000.
`[0050] The memory apparatus 4000 has load execution
`condition information for defining a load execution condi
`tion. The memory apparatus 4000 includes a function of
`changing the load execution condition information. The
`memory apparatus 4000 includes a function for enabling the
`host 4040 to designate changing of the load execution
`condition information. The memory apparatus 4000 includes
`a function of saving the load execution condition informa
`
`tion in the flash memory 4020. The memory apparatus 4000
`includes a function of reading the load execution condition
`information from the load execution condition information.
`The memory apparatus 4000 includes a function of setting a
`correspondence between an address of the SDRAM 4010
`and an address of the flash memory 4020 according to a
`predetermined process.
`[0051] Data transfer in the storage function and the load
`function is carried out between addresses made correspond
`ing to each other by the address correspondence setting
`function. The address correspondence setting function is
`executed based on address correspondence setting informa
`tion. In the flash memory 4020, a failed area may be present,
`in which data cannot be normally read/written. Accordingly,
`for a memory area of the flash memory 4020, it is necessary
`to prevent use of a failed area present on the flash memory
`4020. Thus, based on the address correspondence setting
`information, correspondence is set between the address of
`the SDRAM 4010 and the address of the flash memory 4020
`in order to prevent data accessing to the failed area.
`[0052] The memory apparatus 4000 includes an address
`correspondence setting information storage register for stor
`ing the address correspondence setting information. The
`memory apparatus 4000 includes a function of changing the
`address correspondence setting information stored in the
`address correspondence setting information storage register.
`The memory apparatus 4000 includes a function for
`enabling the host 4040 to designate changing of the address
`correspondence setting information. The memory apparatus
`4000 includes a function of saving the address correspon
`dence setting information in the flash memory 4020. The
`memory apparatus 4000 includes a function of reading the
`address correspondence setting information from the flash
`memory 4020. The memory apparatus 4000 includes a
`function of monitoring a power supply status to the memory
`apparatus 4000.
`[0053] Next, the configuration of the memory apparatus
`4000 will be described more in detail.
`[0054] The memory apparatus 4000 includes at least the
`SDRAM compatible interface 4001, the SDRAM 4010, the
`flash memory 4020, and the control unit 4030. The SDRAM
`4010 and the control unit 4030 are connected to each other
`through an SDRAM interface 4002.
`[0055] The control unit 4030 and the flash memory 4020
`are connected to each other through a flash memory inter
`face 4003. An SDRAM compatible interface 4001 for inter
`connecting the memory apparatus 4000 and the host 4040 is
`connected to the control unit 4030.
`[0056] The memory apparatus 4000 constructs, for
`example the SDRAM 4010, the flash memory 4020, and the
`control unit 4030 on different silicon chips, and intercon
`nects terminals of the silicon chips by, for example wire
`bonding, thereby providing a multichip package, in which
`the components are sealed in one package. Here, the pack
`age indicates an LSI package form such as a thin small
`outline package (TSOP), or a ball grid array (BGA).
`[0057] The SDRAM compatible interface 4001 functions
`between, for example terminal groups for inputting/output
`ting electric signals to the chips, and has electric character
`istics compatible to the SDRAM terminal group. For
`example, the memory apparatus 4000 has compatibility
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1015, p. 30
`
`

`
`US 2003/0028733 A1
`
`Feb. 6, 2003
`
`between the SDRAM and a characteristic of setting-up or
`holding time of each signal, CAS latency or the like.
`[0058] Preferably, the SDRAM compatible interface 4001
`for interconnecting the host 4040 and the control unit 4030
`has compatibility not only between the SDRAM terminal
`group of, for example JEIDA standard and electric charac
`teristics, but also between the SDRAM terminal group and
`a package size of the memory apparatus 4000, a terminal
`group size of for example a pin or a solder ball disposed on
`the package of the memory apparatus 4000, terminal group
`disposition or the like.
`[0059] Thus, the host 4040 including the SDRAM com
`patible interface 4001 can easily use the SDRAM and the
`memory apparatus 4000 by replacement.
`[0060] The SDRAM compatible interface 4001 has a
`memory area for designating an address in, for example the
`SDRAM interface, expanded by an amount equivalent to a
`control register. The SDRAM 4010 is a memory apparatus
`4000, which includes a function of writing data designated
`by the host 4040 in an address designated by the host 4040,
`a function of holding the written data for at least a fixed
`period or more if power is supplied, and a function of
`reading the data stored in the address designated by the host
`4040 and outputting it to the host 4040. By executing
`inputting/outputting of a signal in synchronization with a
`clock, a data transfer speed is increased more compared with
`that of the DRAM of no signal synchronization. The
`SDRAM 4010 includes an SDRAM interface 4002. The
`SDRAM interface 4002 is a terminal group, in which an
`external unit such as a host unit (not shown) using the
`SDRAM 4010 designates an address or data to the SDRAM
`4010.
`[0061] The flash memory 4020 is a memory apparatus,
`which includes a function of writing data designated by the
`host 4040 in an address designated by the host 4040,
`nonvolatility for holding the written data for at least a fixed
`period or more even if the power supply is stopped, and a
`function of reading the data stored in the address designated
`by the host 4040, and outputting it to the host 4040. The flash
`memory 4020 includes a flash memory interface 4003. The
`flash memory interface 4003 is a terminal group, in which an
`external unit such as a host unit (not shown) using the flash
`memory 4020 designates an address or data to the flash
`memory 4020.
`[0062] The control unit 4030 includes a function of con
`trolling operations of the respective units of the memory
`apparatus 4000. The control unit 4030 includes a function of
`controlling the operations of the respective units of the
`memory apparatus 4000, and realizing functions of the
`memory apparatus 4000. The control unit 4030 includes a
`function of interconnecting the SDRAM compatible inter
`face 4001 and the SDRAM interface 4002, and relaying data
`transfer between the host 4030 and the SDRAM 4010. The
`control unit 4030 includes a storage function of tra