(19) United States
`(2) Patent Application Publication (10) Pub. No.: US 2006/0212651 A1
`(43) Pub. Date:
`Sep. 21, 2006
`Ashmore
`
`US 20060212651A1
`
`(54) MASS STORAGE CONTROLLER WITH
`APPARATUS AND METHOD FOR
`EXTENDING BATTERY BACKUP TIME BY
`SELECTIVELY PROVIDING BATTERY
`POWER TO VOLATILE MEMORY BANKS
`NOT STORING CRITICAL DATA
`
`(75) Inventor: Paul Andrew Ashmore, Longmont, CO
`(US)
`
`Correspondence Address:
`HUFFMAN LAW GROUP, P.C.
`1832 N. CASCADE AVE.
`COLORADO SPRINGS, CO 80907-7449 (US)
`
`(73) Assignee: Dot Hill Systems Corporation, Carls
`bad, CA
`(21) Appl. No.:
`11/079,981
`
`(22) Filed:
`
`Mar. 15, 2005
`
`Publication Classification
`
`(51) Int. Cl.
`(2006.01)
`G06F H2/00
`(2006.01)
`G06F II/00
`(52) U.S. Cl. .............................. 711/113: 711/114; 714/22
`
`(57)
`
`ABSTRACT
`
`A battery-backed write-caching mass storage controller is
`disclosed. The controller includes a plurality of volatile
`memory banks for caching write data prior to being written
`to disk drives. Critical data is stored into a first subset of the
`memory banks, leaving a second subset of memory banks
`storing only non-critical data. Critical data is data that must
`be retained during a main power loss to avoid loss of
`write-cached user data. Critical data includes the write
`cached user data itself, as well as metadata describing the
`write-cached user data. When the controller detects a loss of
`main power, the controller causes the critical memory banks
`to receive battery power, but disables battery power to the
`non-critical memory banks in order to extend the length of
`time the critical memory banks can continue to receive
`battery power to reduce the likelihood of user data loss.
`
`RAID Controller Operation
`
`identify critical data and assign location of critical data grouped together and within minimum number of
`memory bank address ranges as possible within the processor memory address space
`
`processor stores information in memory controller indicating which memory banks will store critical data and
`which will not
`
`
`
`controller performs nomal operations, including write-caching operations, by storing critical data only to
`memory banks indicated as storing critical data, non-critical data is written to any of the memory banks
`
`main power is lost and memory controller detects loss of main power
`
`202
`
`204
`
`206
`
`208
`
`memory controller controls switches to supply battery power to memory controller and all memory banks
`
`212
`
`memory controller places critical memory banks into self-refresh mode
`
`memory controller disables power from battery to non-critical memory banks
`
`214
`
`216
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1008, p. 1
`
`

`
`Patent Application Publication Sep. 21, 2006 Sheet 1 of 2
`
`US 2006/0212651 A1
`
`Fig. 1
`
`RAID Controller
`
`A-w
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`132 re-charge from main power
`
`to disk drives
`
`processor
`108
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`
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`
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`106 Self-refresh
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`processor
`communicates to
`memory controller
`information indicating
`which memory banks
`will store critical data
`
`
`
`
`
`host
`interface
`
`disk
`interface
`128
`
`114 main power present
`
`memory controller
`&
`bus bridge
`
`124
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`|A || || 1
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`-
`144
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`
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`memory
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`102
`
`-
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`142battery power
`148 main power
`Critical data, such as user write-cached data and metadata describing
`the write-cached data, is segregated into a subset of the volatile memory
`banks so that when main power is lost, battery power can be disabled to
`the memory banks not storing critical data to reduce the battery power
`consumption during the main power outage.
`
`
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`memory =HE 102
`
`
`
`
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`
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`bank 3
`102
`
`
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`144
`
`-
`Each memory bank hasits OW?)
`separatebatey powerinput and
`can be separately disabled.
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1008, p. 2
`
`

`
`Patent Application Publication Sep. 21, 2006 Sheet 2 of 2
`Fig. 2
`
`BAID Controller Operation
`
`US 2006/0212651 A1
`
`identify critical data and assign location of critical data grouped together and within minimum number of
`memory bank address ranges as possible within the processor memory address space
`
`processor stores information in memory controller indicating which memory banks will store critical data and
`which will not
`
`
`
`controller performs normal operations, including write-caching operations, by storing critical data only to
`memory banks indicated as storing critical data, non-critical data is written to any of the memory banks
`
`202
`
`204
`
`206
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1008, p. 3
`
`

`
`US 2006/0212651 A1
`
`Sep. 21, 2006
`
`MASS STORAGE CONTROLLER WITH
`APPARATUS AND METHOD FOR EXTENDING
`BATTERY BACKUP TIME BY SELECTIVELY
`PROVIDING BATTERY POWER TO VOLATILE
`MEMORY BANKS NOT STORING CRITICAL
`DATA
`
`FIELD OF THE INVENTION
`[0001] The present invention relates in general to the field
`of mass storage controllers, and particularly to write-caching
`controllers that use a battery to avoid loss of write-cached
`user data.
`
`BACKGROUND OF THE INVENTION
`[0002] Redundant Array of Inexpensive Disk (RAID) sys
`tems have become the predominant form of mass storage
`systems in most computer systems today that are used in
`applications that require high performance, large amounts of
`storage, and/or high data availability, such as transaction
`processing, banking, medical applications, database servers,
`internet servers, mail servers, scientific computing, and a
`host of other applications. A RAID controller controls a
`group of multiple physical disk drives in such a manner as
`to present a single logical disk drive (or multiple logical disk
`drives) to a computer operating system. RAID controllers
`employ the techniques of data striping and data redundancy
`to increase performance and data availability.
`[0003] An important characteristic of RAID controllers,
`particularly in certain applications such as transaction pro
`cessing or real-time data capture of large data streams, is to
`provide fast write performance. In particular, the overall
`performance of the computer system may be greatly
`improved if the write latency of the RAID controller is
`relatively small. The write latency is the time the RAID
`controller takes to complete a write request from the com
`puter system.
`[0004] Many RAID controllers include a relatively large
`cache memory for caching user data from the disk drives.
`Caching the data enables the RAID controller to quickly
`return data to the computer system if the requested data is in
`the cache memory since the RAID controller does not have
`to perform the lengthy operation of reading the data from the
`disk drives. The cache memory may also be employed to
`reduce write request latency by enabling what is commonly
`referred to as posted-write or write-caching operations. In a
`write-cache or posted-write operation, the RAID controller
`reads the user data specified by the computer system from
`the computer system into the RAID controller’s cache
`memory and then immediately notifies the computer system
`that the write request is complete, even though the RAID
`controller has not yet written the user data to the disk drives.
`Posted-writes are particularly useful in RAID controllers,
`since in some redundant RAID levels a read-modify-write
`operation to the disk drives must be performed in order to
`accomplish the system write request. That is, not only must
`the specified user data be written to the disk drives, but some
`of the disk drives may also have to be read before the user
`data and redundant data can be written to the disks, which
`may make the write latency of a RAID controller even
`longer than a non-RAID controller.
`[0005] However, posted-write operations make the system
`vulnerable to data loss in the event of a power failure. This
`
`is because the cache memory is a volatile memory that loses
`the user data when power is lost and the data has not yet been
`written to the disk drives.
`[0006] To solve this problem, some RAID controllers
`include a battery to continue to provide power to the cache
`memory in the event of a loss of main power. Typically, the
`system automatically notifies a system administrator who
`attempts to restore power to the system. Although the battery
`greatly reduces the likelihood that user data will be lost,
`because the charge on the battery is finite, the possibility still
`exists that the battery power will run out before main power
`can be restored, in which case the user data will be lost.
`Thus, it is crucial to consume as little battery power as
`possible during the main power outage to increase the
`likelihood that the battery will not run out before main
`power is restored. Therefore what is needed is an apparatus
`and method for reducing the battery consumption during the
`main power outage.
`
`BRIEF SUMMARY OF INVENTION
`[0007] The present invention provides a write-caching
`mass storage controller that segregates and stores critical
`data (write-cached data and metadata describing the write
`cached data) into one subset of volatile memory banks
`leaving another subset of volatile memory banks storing
`only non-critical data. In response to a loss of main power,
`the controller only provides battery power to the critical
`memory banks, but not to the non-critical memory banks, in
`order to reduce the amount of battery power consumed
`during the main power outage, thereby extending the time
`the critical memory banks can store the critical data to
`reduce the likelihood of user data loss.
`[0008] In one aspect, the present invention provides a
`write-caching mass storage controller. The controller
`includes a plurality of volatile memory banks, each having
`separate power inputs. The controller also includes a battery,
`coupled to provide power to the plurality of volatile memory
`banks via the separate power inputs, during a main power
`loss. The controller also includes a processor, coupled to the
`plurality of volatile memory banks, which controls storage
`of critical data to a first subset of the plurality of volatile
`memory banks and refrains from controlling storage of the
`critical data to a second subset of the plurality of volatile
`memory banks. The first and second subsets of virtual
`memory banks are mutually exclusive. The critical data
`comprises data which must be retained during the main
`power loss to avoid loss of write-cached user data. The
`controller also includes control logic, coupled to receive
`information from the processor indicating the first and
`second subsets of the plurality of volatile memory banks.
`The control logic detects the loss of main power and in
`response disables the second subset of the plurality of
`volatile memory banks from receiving power from the
`battery.
`[0009] In another aspect, the present invention provides a
`method for reducing battery power consumption during a
`main power loss to reduce the likelihood of loss of user
`write-cached data in a write-caching mass storage controller.
`The method includes storing information indicating first and
`second subsets of a plurality of volatile memory banks of the
`controller. Each of the first and second subsets are config
`ured to separately receive power from the battery. The first
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1008, p. 4
`
`

`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1008, p. 5
`
`

`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1008, p. 6
`
`

`
`US 2006/0212651 A1
`
`Sep. 21, 2006
`
`that the write request is complete until the data is actually
`written to disk. However, if configured to do so, the con
`troller 100 may cache the data in the volatile memory banks
`102 and indicate to the host that the write request is complete
`before the data is actually written to the disk, and subse
`quently write, or flush, the data to disk. This operation is
`referred to as write-caching, or may also be referred to as a
`posted-write operation. The data associated with a write
`cache or posted-write operation is referred to as write-cache
`data or posted-write data. That is, write-cache data is data
`stored in the volatile memory banks 102 that has not yet
`been written to disk but concerning which the controller 100
`has told the host that the write operation has completed. As
`stated above, write-cache data is critical data. Additionally,
`metadata that describes the write-cache data is also critical
`data. Additionally, the controller 100 may use the volatile
`memory banks 102 for buffering redundant RAID data
`generated for writing to the disks.
`[0026] Referring now to FIG. 2, a flowchart illustrating
`operation of the controller 100 of FIG. 1 is shown. Flow
`begins at block 202.
`[0027] At block 202, the critical data is identified. In one
`embodiment, the critical data is grouped together within the
`address space. In one embodiment, the critical data is
`grouped together such that the minimum number of volatile
`memory banks 102 must be designated as critical volatile
`memory banks. For example, assume the volatile memory
`banks 102 are four separate volatile memory banks 102 each
`capable of storing 512 MB of data, and assume the total
`amount of critical data is between 512 MB and 1 GB. Then
`the critical data would be grouped and located in the address
`space such that it is located within only two of the volatile
`memory banks 102, rather than three or four of the volatile
`memory banks 102. As mentioned above, in one embodi
`ment, the software developer identifies the critical data and
`assigns the locations of the critical data to segregate it. Flow
`proceeds to block 204.
`[0028] At block 204, the processor 108 stores information
`in the memory controller/bus bridge 124 indicating which of
`the volatile memory banks 102 are critical volatile memory
`banks 102 and which are non-critical volatile memory banks
`102. At a minimum, the processor 108 communicates to the
`memory controller/bus bridge 124 which of the volatile
`memory banks 102 are non-critical volatile memory banks
`102. Flow proceeds to block 206.
`[0029] At block 206, after the controller 100 boots up, the
`controller 100 performs normal input/output (I/O) opera
`tions with the hosts and disk drives. In particular, the
`controller 100 performs write-caching operations, storing
`critical data only to critical volatile memory banks 102. As
`mentioned above, non-critical data may be stored in either
`critical or non-critical volatile memory banks 102. It is noted
`that initially the various circuit elements of the controller
`100 are receiving main power 148. Flow proceeds to block
`208.
`[0030] At block 208, the controller 100 suffers the loss of
`main power 148 and the memory controller/bus bridge 124
`detects the loss of main power 148 via main power present
`indicator 114. Flow proceeds to block 212.
`[0031] At block 212, in response to the main power
`present indicator 114 indicating the loss of main power 148,
`
`the memory controller/bus bridge 124 generates the control
`signals 136 to cause the switches 144 to provide battery
`power 142 to their respective volatile memory banks 102.
`Additionally, the battery 112 provides power to the memory
`controller/bus bridge 124 and any other circuits of the
`controller 100 that must continue to receive power. Flow
`proceeds to block 214.
`[0032] At block 214, the memory controller/bus bridge
`124 places the critical volatile memory banks 102 into
`self-refresh mode via self-refresh signal 106 to reduce the
`amount of battery power 142 consumed by the critical
`volatile memory banks 102. Flow proceeds to block 216.
`[0033] At block 216, the microprocessor 100 examines the
`information stored into it by the processor 108 specifying
`which of the volatile memory banks 102 are non-critical and
`generates the control signal 136 to cause the corresponding
`switch 144 for each of the non-critical volatile memory
`banks 102 to disable battery power 142, in order to reduce
`the amount of battery power 142 consumed by the controller
`100, thereby extending the length of time the controller 100
`can continue to retain the critical data until main power 148
`is restored, and thereby reducing the likelihood that user data
`will be lost.
`[0034] Although the present invention and its objects,
`features, and advantages have been described in detail, other
`embodiments are encompassed by the invention. For
`example, although embodiments have been described in
`which the storage controller is a RAID controller, the
`selective disabling of battery power to non-critical volatile
`memory banks as described herein may also be employed in
`any storage controller (i.e., a non-RAID controller) that uses
`a cache memory to post write operations to disk drives or
`other storage devices. Furthermore, although embodiments
`have been described in which the memory controller/bus
`bridge 124 detects the main power loss, places the volatile
`memory banks 102 in self-refresh mode, and disables bat
`tery power 142 to the non-critical volatile memory banks
`102, in another embodiment the processor 108 performs
`these functions.
`[0035] Finally, those skilled in the art should appreciate
`that they can readily use the disclosed conception and
`specific embodiments as a basis for designing or modifying
`other structures for carrying out the same purposes of the
`present invention without departing from the spirit and
`scope of the invention as defined by the appended claims.
`
`I claim:
`1. A write-caching mass storage controller, comprising:
`a plurality of volatile memory banks, each having sepa
`rate power inputs;
`a battery, coupled to provide power to said plurality of
`volatile memory banks via said separate power inputs
`during a main power loss;
`a processor, coupled to said plurality of volatile memory
`banks, configured to control storage of critical data to
`a first subset of said plurality of volatile memory banks
`and to refrain from controlling storage of said critical
`data to a second subset of said plurality of volatile
`memory banks, wherein said first and second subset are
`mutually exclusive, wherein said critical data com
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1008, p. 7
`
`

`
`US 2006/0212651 A1
`
`Sep. 21, 2006
`
`prises data which must be retained during said main
`power loss to avoid loss of write-cached user data; and
`control logic, coupled to receive information from said
`processor indicating said first and second subsets of
`said plurality of volatile memory banks, configured to
`detect said loss of main power, and to disable said
`second subset of said plurality of volatile memory
`banks from receiving power from said battery in
`response to detecting said loss of main power.
`2. The mass storage controller as recited in claim 1,
`wherein said critical data comprises said write-cached user
`data.
`3. The mass storage controller as recited in claim 2,
`wherein said critical data further comprises metadata, said
`metadata describing said write-cached user data.
`4. The mass storage controller as recited in claim 3,
`wherein said metadata specifies locations of said write
`cached user data in said first subset of said plurality of
`volatile memory banks.
`5. The mass storage controller as recited in claim 3,
`wherein said metadata specifies locations on one or more
`storage devices controlled by the controller to which said
`write-cached user data is to be written.
`6. The mass storage controller as recited in claim 5,
`wherein said one or more storage devices comprise disk
`drives.
`7. The mass storage controller as recited in claim 3,
`wherein said metadata comprises parity logs, used by said
`processor to fix RAID level 5 write holes.
`8. The mass storage controller as recited in claim 3,
`wherein said metadata comprises debug logs.
`9. The mass storage controller as recited in claim 1,
`wherein said control logic is further configured to place said
`first subset of said plurality of volatile memory banks into a
`low power mode in response to detecting said main power
`loss.
`10. The mass storage controller as recited in claim 9,
`wherein said low power mode comprises a dynamic random
`access memory (DRAM) self-refresh mode.
`11. The mass storage controller as recited in claim 1,
`wherein said plurality of volatile memory banks comprise
`banks of dynamic random access memory (DRAM).
`12. The mass storage controller as recited in claim 1,
`wherein said plurality of volatile memory banks occupy
`separate address ranges within an address space of said
`processor.
`13. The mass storage controller as recited in claim 1,
`wherein said plurality of volatile memory banks comprise
`physically separate memory devices, said memory devices
`having said separate power inputs.
`14. The mass storage controller as recited in claim 13,
`wherein said physically separate memory devices comprise
`separate integrated circuits.
`15. The mass storage controller as recited in claim 1,
`wherein the mass storage controller is a redundant array of
`inexpensive disks (RAID) controller and said processor
`performs RAID functions.
`16. The mass storage controller as recited in claim 1,
`wherein said control logic comprises said processor.
`17. A method for reducing battery power consumption
`during a main power loss to reduce the likelihood of loss of
`user write-cached data in a write-caching mass storage
`controller, comprising:
`
`storing information indicating first and second subsets of
`a plurality of volatile memory banks of the controller,
`wherein each of the first and second subsets are con
`figured to separately receive power from the battery,
`wherein the first and second subset are mutually exclu
`S1Ve:
`storing critical data to the first subset of the plurality of
`volatile memory banks in exclusion of the second
`subset of the plurality of volatile memory banks, after
`said storing the information, wherein the critical data
`comprises data which must be retained during the main
`power loss to avoid loss of write-cached user data;
`detecting the main power loss, after said storing the
`critical data; and
`disabling the second subset of the plurality of volatile
`memory banks from receiving power from the battery
`in response to detecting the loss of main power.
`18. The method as recited in claim 17, wherein the critical
`data comprises the write-cached user data.
`19. The method as recited in claim 18, wherein the critical
`data further comprises metadata, the metadata describing the
`write-cached user data.
`20. The method as recited in claim 19, wherein the
`metadata specifies locations of the write-cached user data in
`the first subset of the plurality of volatile memory banks.
`21. The method as recited in claim 19, wherein the
`metadata specifies locations on one or more storage devices
`controlled by the controller to which the write-cached user
`data is to be written.
`22. The method as recited in claim 21, wherein the one or
`more storage devices comprise disk drives.
`23. The method as recited in claim 19, wherein the
`metadata comprises parity logs, used to fix RAID level 5
`write holes.
`24. The method as recited in claim 19, wherein the
`metadata comprises debug logs.
`25. The method as recited in claim 17, further comprising:
`placing the first subset of the plurality of volatile memory
`banks into a low power mode in response to said
`detecting the main power loss.
`26. The method as recited in claim 25, wherein the low
`power mode comprises a dynamic random access memory
`(DRAM) self-refresh mode.
`27. The method as recited in claim 17, wherein the
`plurality of volatile memory banks comprise banks of
`dynamic random access memory (DRAM).
`28. The method as recited in claim 17, wherein the
`plurality of volatile memory banks occupy separate address
`ranges within an address space of a processor of the con
`troller.
`29. The method as recited in claim 28, further comprising:
`assigning locations of the critical data within the address
`ranges of the first subset of the plurality of volatile
`memory banks, prior to said storing information indi
`cating the first and second subsets.
`30. The method as recited in claim 17, wherein the
`plurality of volatile memory banks comprise physically
`separate memory devices, the memory devices having the
`separate power inputs.
`31. The method as recited in claim 30, wherein the
`physically separate memory devices comprise separate inte
`grated circuits.
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1008, p. 8
`
`

`
`US 2006/0212651 A1
`
`Sep. 21, 2006
`
`32. The method as recited in claim 17, wherein the mass
`storage controller is a redundant array of inexpensive disks
`(RAID) controller.
`33. A write-caching mass storage controller, comprising:
`a plurality of volatile memory banks, each having sepa
`rate power inputs;
`a battery, coupled to provide power to said plurality of
`volatile memory banks via said separate power inputs,
`during a main power loss; and
`a processor, coupled to said plurality of volatile memory
`banks, configured to control storage of critical data to
`a first subset of said plurality of volatile memory banks
`and to refrain from controlling storage of said critical
`data to a second subset of said plurality of volatile
`memory banks, wherein said first and second subset are
`mutually exclusive, wherein said critical data com
`prises data which must be retained during said main
`power loss to avoid loss of write-cached user data, said
`processor further configured to detect said loss of main
`power, and to responsively disable said second subset
`of said plurality of volatile memory banks from receiv
`ing power from said battery.
`34. The mass storage controller as recited in claim 33,
`wherein said critical data comprises said write-cached user
`data.
`
`35. The mass storage controller as recited in claim 34,
`wherein said critical data further comprises metadata, said
`metadata describing said write-cached user data.
`36. The mass storage controller as recited in claim 35,
`wherein said metadata specifies locations of said write
`cached user data in said first subset of said plurality of
`volatile memory banks.
`37. The mass storage controller as recited in claim 35,
`wherein said metadata specifies locations on one or more
`storage devices controlled by the controller to which said
`write-cached user data is to be written.
`38. The mass storage controller as recited in claim 35,
`wherein said metadata comprises parity logs, used by said
`processor to fix RAID level 5 write holes.
`39. The mass storage controller as recited in claim 33,
`wherein said control logic is further configured to place said
`first subset of said plurality of volatile memory banks into a
`low power mode in response to detecting said main power
`loss.
`40. The mass storage controller as recited in claim 33,
`wherein said plurality of volatile memory banks occupy
`separate address ranges within an address space of said
`processor.
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1008, p. 9