Ulllted States Patent [19]
`Mills et al.
`
`[54] FLASH MEMORY INCLUDING A MODE
`REGISTER FOR INDICATING
`SYNCHRONOUS 0R ASYNCHRONOUS
`MODE 0F OPERATIO
`N
`
`_
`_
`[75] Inventors: Duane R. Mills, Folsom; Brian Lyn
`Dipert, Sacramento; Sachidanandan
`Sambandan, Folsom; Bruce
`McCormick; Richard D_ pashley, both
`of Roseville, an of Calif
`
`[73] Ass1gnee: Intel Corporation, Santa Clara, Cal1f.
`
`US006026465A
`[11] Patent Number:
`[45] Date of Patent:
`
`6,026,465
`Feb. 15, 2000
`
`FOREIGN PATENT DOCUMENTS
`
`5654532 5/1981 Japan'
`4-372030 12/1992 Japan.
`5334168 12/1993 Japan .
`2 251 324 7/1992 United Kingdom .
`
`OTHER PUBLICATIONS
`
`_
`“
`Arnold, Intel ?ash noW’boots a BIOS; block—or1ented part
`clzcgnélld holgl péher rcgutmes , EDN, vol. 36, No. 10A, May 16,
`
`, p.
`
`pgs. .
`(List Continued on next page‘)
`
`[21] Appl- NOJ 08/897,499
`[22]
`Filed:
`Jun‘ 18’ 1997
`
`Primary Examiner—Reginald G. Bragdon
`ggfotgzggnlfgent, 0r Fzrm—Blakely, Sokoloff, Taylor &
`
`Related US. Application Data
`
`[57]
`
`ABSTRACT
`
`[63] Continuation of application No. 08/253,499, Jun. 3, 1994,
`Pat- N0~ 5,696,917
`Int. c1.7 ........................... .. G06F 13/16; G06F 12/00
`[51]
`[52] US. Cl. .............................. .. 711/103; 711/5; 711/167
`58] Field of Search
`711/5 103 167_
`[
`’
`39’5 855’
`/
`
`"""""""""""""""" "
`
`[56]
`
`_
`References Clted
`U'S' PATENT DOCUMENTS
`
`364/136
`711/167
`364/130
`365/233
`711/169
`
`4,785,428 11/1988 BaJWa et a1. . . . . . .
`
`. . . . . .. 365/233
`
`7/1977 Simmons ..
`4,034,354
`5/1978 Grllnef ------------ -
`4,089,052
`4J3O7J447 12/1981 Provanzano et a1~ -
`4,596,004
`6/1986 Kaucflman """"" "
`4’63O’23O 12/1986 SUI} ct """" "
`4 813 018 3/1989 K
`-
`365/185.08
`,
`,
`obayashi et al.
`345/135
`478167814
`3/1989 Lumelsky ________ __
`711/133
`478477758
`7/1989 Olson et a1_ __
`4,918,587
`4/1990 Pechter et al. ........................ .. 711/218
`4,945,535
`7/1990 Hosotani et al. ......................... .. 714/8
`4,947,380
`8/1990 Van Zanten et al- -
`365/238
`5,036,460
`7/1991 Takatllra et a1~
`711/103
`2,043,872
`8/1991 Gagharci? et a1‘
`71g 15;
`,097,44
`3/1992 Yamauc 1 ............................. .. 36 /19
`5,101,490
`3/1992 Getson, Jr. et a1. .................... .. 710/15
`
`A?ash memory chip that can be switched into four different
`read modes is described. In the ?rst read mode, asynchro
`nous ?ash mode, the ?ash memory is read as a Standard ?ash
`memory Where the teadmg of the Contents of a ?rst address
`must be completed before a second address to be read can be
`speci?ed. In the second read mode, synchronous ?ash mode,
`a clock signal is provided to the ?ash chip and a series of
`addresses belonging to a data burst are speci?ed, one address
`per clock tick. Then, the contents stored at the addresses
`spec1?ed for the burst are output sequentlally dur1ng subse
`quent clock tlcks 1n the order 1n Wh1ch the addresses Were
`provided. Alternately, if a single address is provided to the
`?ash chip When it is in the synchronous mode, the subse
`quent addresses for the burst Will be generated Within the
`?ash chip and the data burst Will then be provided as output
`from the ?ash chip. In the third read mode, asynchronous
`DRAM mode, the roW and column addresses are strobed
`_
`_
`_
`1nto the ?ash memory us1ng strobe s1gnals. The ‘?ash
`memory then converts the roW and column addresses 1nter
`nally into a single address and provides as output the data
`stored at that single address. The ?ash memory does not
`need an extended precharge period or to be refreshed, but
`can be controlled by a standard DRAM controller. In the
`fourth read mode, synchronous DRAM mode, the ?ash
`memory emulates a Synchronous DRAM‘
`
`List continued on next a e.
`P g
`
`12 Claims, 14 Drawin Sheets
`g
`
`BUS SPECIFIC
`
`
`
`<1: Buifimc SIGNALS
`
`0E8 —>
`OE#_>
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`m
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`HAS“
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`
`
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`<—::E#
`
`B5
`
`M
`
`OUTPUT
`_ R
`*
`
`D53‘
`22$
`
`SYNOHRONOUS MAIN
`MEMORY INTERFACE FLASH
`
`m
`
`ME
`
`BANK[A]ADDRESS
`AMSA LATCH1430
`HlGH [A]
`3303] G 6mm] S/A OUT[A]
`14 L
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`ADDFHB] BAim] S/AOUT[B]
`
`i
`
`BANK [B] ADDRESS
`LATCH 1432
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1007, p. 1
`
`

`
`6,026,465
`Page 2
`
`US. PATENT DOCUMENTS
`
`9/1992 Neuhard et al. ..................... .. 358/1.16
`5,146,546
`3/1993 Bordsen et al. ..
`711/152
`5,193,162
`3/1993 Fandrich et al. ..
`365/227
`5,197,034
`9/1993 Bruckert et al. ..
`714/11
`5,249,187
`5,251,227 10/1993 Bruckert et al. ..
`714/23
`5,261,064 11/1993 Wyland ........... ..
`711/211
`5,263,003 11/1993 CoWles et al. ................... .. 365/230.03
`5,265,218 11/1993 Testa et al. ........................... .. 710/100
`5,276,812
`1/1994 Yamada et al.
`711/105
`5,287,457
`2/1994 Arimilli et al. ..... ..
`710/128
`5,291,580
`3/1994 BoWden, III et al.
`..... .. 711/5
`5,297,148
`3/1994 Harari et al. .......................... .. 714/710
`5,302,866
`4/1994 Chiang et al. .......................... .. 326/40
`5,306,963
`4/1994 Leak et al.
`327/14
`5,307,314
`4/1994 Lee .......... ..
`365/189.04
`5,327,390
`7/1994 Takasugi
`365/230.06
`5,331,601
`7/1994 Parris
`.. 365/230.08
`5,333,276
`7/1994 Solari .............. ..
`712/220
`5,339,134
`8/1994 Nakamura et al.
`399/367
`5,357,459 10/1994 Chapman ........ ..
`365/149
`5,359,569 10/1994 Fujita et al. .... ..
`365/229
`5,369,754 11/1994 Fandrich et al. ..
`711/103
`5,379,384
`1/1995 Solomon ..... ..
`710/128
`5,388,224
`2/1995 Maskas ....... ..
`710/104
`5,388,248
`2/1995 Robinson et al.
`365/52
`5,404,338
`4/1995 Murai .......... ..
`365/233
`5,404,485
`4/1995 Ban ................. ..
`711/202
`5,414,820
`5/1995 McFarland et al.
`710/128
`5,418,752
`5/1995 Harari et al. .... ..
`365/218
`5,422,855
`6/1995 Eslick et al. .... ..
`365/226
`5,426,603
`6/1995 Nakamura et al.
`..... .. 365/149
`5,428,579
`6/1995 Robinson et al.
`.. 365/230.03
`5,430,849
`7/1995 Banks .......... ..
`710/128
`5,438,549
`8/1995 Levy ....... ..
`365/229
`5,448,521
`9/1995 Curry et al. ..
`365/189.02
`5,450,551
`9/1995 Amini et al. .......................... .. 710/119
`5,453,957
`9/1995 Norris et al. ..................... .. 365/230.04
`5,465,367 11/1995 Reddy et al.
`..... .. 365/222
`5,471,632 11/1995 Gavin et al. ..
`710/104
`5,491,827
`2/1996 Holtey ......... ..
`711/163
`5,500,829
`3/1996 Toda et al. .
`.. 365/230.08
`5,526,311
`6/1996 Kreifels et al.
`..... .. 365/201
`5,530,673
`6/1996 Tobita et al. ..
`365/185.09
`5,729,709
`3/1998 Harness ....................................... .. 71/5
`
`OTHER PUBLICATIONS
`
`Case, Brian and Michael Slater, “DEC enters microproces
`sor business With Alpha; DEC to sell chips on open market”,
`Microprocessor Report, vol. 6, No. 3, Mar. 4, 1992, p. 1 (7
`pgS-)~
`“Chips: Headland Technology Zero Wait state single chip
`system logic”, Work—Group Computing Report, vol. 2, No.
`72, Oct. 7, 1991, p. 63 (1 pg.).
`Dalton, “Intel packs a computer on a chip: the 386 SL
`promises to make portables even more portable”, Lotus, vol.
`6, No. 12, Dec. 1990, p. 10 (2 pgs.).
`Dipert, Brian and Marcus Levy, “Chapter 5: Hardware
`Interfacing to Flash Memory Components: Designing With
`Flash Memory: The de?nitive guide to designing ?ash
`memory hardWare and software for components and PCM
`CIAcards”,Annabooks: San Diego, CA, Oct. 1993, pp. i—vii
`and 73—104.
`Dipert, Brian, “28F008SA HardWare Interfacing”, Intel Cor
`poration’s Mobile Computer Products: Chapter 4, Applica
`tion Note AP—359, Aug. 1992, pp. 4—299 to 4—309.
`
`Dipert, Brian, “Flash Memory: Meeting the Needs of Mobile
`Computing”, Intel Corporation’s Flash Memory vol. II:
`Chapter 10, Article Reprint AR—715, 1992, pp. 10—8 to
`10—15.
`“Flash Memory OvervieW”, Intel Corporation’s Flash
`Memory vol. 1: Chapter 2, Nov. 1992, pp. 2—1 to 2—6.
`Forella, John, “Solid state memeory: understanding the
`basics of non—volatile technology”, Defense Electronics,
`vol. 26, No. 1, Jan. 1994, p. 34 (3 pgs.).
`Grey, George, “The 88000 faces of Multibus II”, ESD: The
`Electronic System Design MagaZine, vol. 18 No. 9, Sep.
`1988, p. 45 (6 pgs.).
`Lavin, Paul, “Racing to the top: NEC’s PoWerMate 486/
`25E, With a look at the Apricot Qi 900”, PC User, No. 131,
`Apr. 25, 1990, p. 83 (4 pgs.).
`Martin, S. Louis, ’486 chip sets due for AT, MCA, EISA:
`sets differ on burst—mode and second—level cache support
`(80486 microprocessor), EDN, vol. 34, NO. 24A, Nov. 30,
`1989, p. 1 (2 pgs.).
`Patent Cooperation Treaty’s International Search Report for
`International application No. PCT/US95/07062, dated Dec.
`6, 1995, 6 pgs.
`Patent Cooperation Treaty’s Written Opinion for Interna
`tional application No. PCT/US95/07062, dated Jul. 23,
`1996, 1995, 9 pgs.
`Prince, Betty, “Memory in the Fast Lane”, IEEE Spectrum,
`Feb. 1994, pp. 38—41.
`Sama, Anil and Brian Dipert, “PoWer Supply Solutions for
`Flash Memory”, Intel Corporation’s Flash Memory vol. I:
`Chapter 2, Application Note AP—357, Sep. 1993, pp. 2—7 to
`2—41.
`“TWo—chip set based on 386SL core simpli?es palmtop
`system designs (VLSI Technology Inc.’s VL86C300 and
`VL86C100 chips based on Intel Corp’s 80386 microproces
`sor)”, Electronic Design, vol. 41, No. 21, Oct. 14, 1993, p.
`140 (2 pgs.).
`Verner, Don, “Implementing Mobile PC Designs Using
`High Density FlashFile Components”, Intel Corporation’s
`Flash Memory vol. I: Chapter 3, Application Note AP—362,
`Oct. 1993, pp. 3—139 to 3—193.
`Willett, Hugh G., “Moore: Flash’s Rise is EPROM’s
`Demise, Intel: Will not add EPROMs past 4—Mbit density”,
`Electronic Buyers’ NeWs, Apr. 22, 1991, p. 1 (2 pgs.).
`Wilson, “Vendors eye ?ash EPROM for role in one—chip
`microcomputers”, Computer Design, vol. 28, No. 11, Jun. 1,
`1989, p. 3, 26 & 27 (3 pgs.).
`Woods, Lynn A. and Aviel Livay, “Connect an FDDI periph
`eral to the Sbus”, Electronic Design, vol. 41, No. 22, Nov.
`1, 1993, p. 69 (8 pgs.).
`Ziegler, Jeff, Tim Hornback and Anthony Jordan, “The ten
`commandments of debugging: When troubleshooting com
`plex systems, don’t make the job any tougher than it is—get
`back to the basics”, Electronic Design, vol. 40, No. 18, Sep.
`3, 1992, p. 61 (8 pgs.).
`“27960CX: Pipelined BurstAccess 1M (128K><8) EPROM”,
`Intel Corporation, Order No. 290236—002, Oct. 1989, pp.
`4—358 to 4—378.
`27960KX: Burst Access 1M (128K><8) EPROM, Intel Cor
`poration, Order No. 290237—002, Oct. 1989, pp. 4—379 to
`4—396.
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1007, p. 2
`
`

`
`U.S. Patent
`
`Feb. 15,2000
`
`Sheet 1 0f 14
`
`6,026,465
`
`SYSTEM M
`
`MICROPROCESSOR
`11_Q
`
`BUS 120
`—
`
`FLASH
`MEMQRY
`1%
`
`FIG. 1
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1007, p. 3
`
`

`
`U.S. Patent
`
`Feb. 15,2000
`
`Sheet 2 0f 14
`
`6,026,465
`
`
`
`
`
`% mam Qmmmm >>O._
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`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1007, p. 4
`
`

`
`U.S. Patent
`
`Feb. 15,2000
`
`Sheet 3 0f 14
`
`6,026,465
`
`m .UE
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1007, p. 5
`
`

`
`U.S. Patent
`
`Feb. 15,2000
`
`Sheet 4 0f 14
`
`6,026,465
`
`| ADDRESS
`
`DATA
`
`I
`
`l
`OPEN—|——-—
`|
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1007, p. 6
`
`

`
`U.S. Patent
`
`Feb. 15,2000
`
`Sheet 5 0f 14
`
`6,026,465
`
`INITIAL STATE
`
`_> (WAITING FOR
`ARRAY ACCESS)
`m
`
`502
`
`LATCH NEW
`ADDRESS FOR
`PAGE COMPARE
`m
`
`THE ACCESS
`A READ?
`5S0
`
`WAIT STATE(S)
`GENERATIQN
`5&0
`
`READY
`
`FIG. 5
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1007, p. 7
`
`

`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1007, p. 8
`
`

`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1007, p. 9
`
`

`
`U.S. Patent
`
`Feb. 15,2000
`
`Sheet 8 0f 14
`
`6,026,465
`
`% I
`
`
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`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1007, p. 10
`
`

`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1007, p. 11
`
`

`
`U.S. Patent
`
`Feb. 15,2000
`
`Sheet 10 0f 14
`
`6,026,465
`
`l
`I
`(d) D(OUT) I '
`w.
`I
`
`OPEN
`
`FIG. 11
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1007, p. 12
`
`

`
`U.S. Patent
`
`Feb. 15,2000
`
`Sheet 11 0f 14
`
`6,026,465
`
`HEAD/WRITE
`RAS# ———> LOGIC
`JLQ
`
`RY/BY# >
`(FLOAT)
`
`ASYNCHRONOUS
`<E> MAIN MEMORY
`INTERFACE (AMMI)
`FLASH DEVICE
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`1‘
`
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`1220
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`
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`MONITOR
`12 0
`
`FIG. 12
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1007, p. 13
`
`

`
`U.S. Patent
`
`Feb. 15,2000
`
`Sheet 12 0f 14
`
`6,026,465
`
`
`
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`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1007, p. 14
`
`

`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1007, p. 15
`
`

`
`U.S. Patent
`
`Feb. 15,2000
`
`Sheet 14 0f 14
`
`6,026,465
`
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`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1007, p. 16
`
`

`
`1
`FLASH MEMORY INCLUDING A MODE
`REGISTER FOR INDICATING
`SYNCHRONOUS OR ASYNCHRONOUS
`MODE OF OPERATION
`
`This is a continuation of application Ser. No. 08/253,499,
`?led Jun. 3, 1994 now US. Pat. No. 5,696,917.
`
`FIELD OF THE INVENTION
`
`The present invention pertains to the ?eld of the archi
`tecture of computer systems. More particularly, the present
`invention relates to computer systems that use a large-block
`erasable non-volatile semiconductor memory as main
`memory.
`
`BACKGROUND OF THE INVENTION
`
`As modern computer programs have become increasingly
`more sophisticated, modern personal computer systems have
`also had to become more sophisticated in order to accom
`modate these computer programs. Computer programs are
`made up of a larger number of code instructions than they
`once Were and on average, require access to larger ?les of
`data that are read from, and Written to, When executing the
`programs.
`Typically, the heart of a personal computer system is a
`central processing unit (CPU) that resides on a micropro
`cessor chip. NeW microprocessor chips that operate at
`increasingly high operating speeds are constantly being
`developed in order to permit personal computers to execute
`the larger programs in a timely manner. Usually, these
`microprocessor chips are developed using CMOS
`(complementary metal-oxide semiconductor) technology.
`The greatest amount of poWer consumption for CMOS chips
`occurs on the leading and trailing edges of clock pulses (i.e.
`When a clock signal transitions from a loW voltage state to
`a higher voltage state and vice versa).
`When the operating speed of the microprocessor is
`increased, the number of clock pulses in a particular time
`period increases thereby increasing the poWer consumption
`of the microprocessor during this time period. Furthermore,
`more heat is generated by the microprocessor and must be
`dissipated in order to prevent the damage of components
`Within the computer system.
`Both poWer consumption and heat dissipation pose seri
`ous problems When designing a personal computer system.
`This is especially true in the case of mobile computers that
`are typically poWered by batteries. The more poWer that the
`computer consumes, the less time that the computer can
`operate off of a given siZed battery. Therefore, as the
`operating speed of the computer is increased, a designer is
`faced With several unattractive alternatives.
`If the same siZed batteries are used, then the effective
`operating time for the computer system must decrease When
`the operating speed is increased. On the other hand, if the
`effective operating time is to remain constant then it is
`necessary to either add additional batteries, thereby increas
`ing the bulk and Weight of the computer, or to use an exotic
`and therefore expensive battery technology (or both).
`The trend in mobile computers is toWards smaller, faster,
`less expensive and lighter units. Thus, the need to add
`additional batteries, or more expensive batteries is a signi?
`cant disadvantage. This disadvantage is exacerbated by the
`need to add cooling fans, or to implement other cooling
`techniques, in order to dissipate the additional heat that is
`generated by the high speed microprocessors.
`
`15
`
`25
`
`35
`
`45
`
`55
`
`65
`
`6,026,465
`
`2
`Additionally, because the microprocessors are operating
`at a higher speed, they can execute more instructions in a
`given amount of time, and therefore can also process a
`greater amount of data during that period. Abottle neck has
`developed in computer systems having fast microprocessors
`that can prevent the higher speed of the microprocessor to be
`utiliZed effectively. This bottle neck is the bus (or buses) that
`provide instructions for the microprocessor to execute and
`the data that the microprocessor Will use When executing the
`instructions.
`If the next instruction to be executed is not available When
`the microprocessor needs it, then the microprocessor must
`Wait idly (i.e. insert Wait cycles) While the required instruc
`tion is retrieved and provided to the microprocessor.
`Furthermore, if the next instruction to be executed requires
`data that is not immediately available to the microprocessor,
`the microprocessor must also idle until the data has been
`retrieved. During this idle time, the microprocessor clock
`continues to toggle thereby needlessly consuming poWer and
`generating heat that must be dissipated.
`In order to decrease the frequency With Which the micro
`processor encounters these Wait cycles, many modern high
`performance microprocessors have a small internal cache,
`called a primary cache. Instructions that are likely to be
`executed and data that is likely to be needed by the executing
`instructions are stored in the internal cache so that they may
`be accessed immediately by the CPU of the microprocessor.
`The sequential nature of computer programs is such that
`When a particular instruction Within the program is executed,
`it is highly probable that the next instruction to be executed
`Will be the instruction that folloWs the currently executing
`instruction. Therefore, When an instruction is to be executed,
`the cache is checked to determine Whether a copy of the
`required instruction is immediately available Within the
`cache. If a copy of the required instruction is stored Within
`the cache (called a cache hit), then the copy of the instruction
`can be supplied to the CPU immediately from the cache and
`there is not need for the CPU to Wait While the instruction
`is retrieved to the microprocessor chip from Wherever it is
`stored in the computer system.
`On the other hand, if a copy of the required instruction is
`not stored Within the cache (called a cache miss), then the
`CPU must Wait While the instruction is retrieved to the
`microprocessor chip from Wherever it is stored Within the
`computer system. Actually, rather than only retrieving the
`next instruction to be executed, a cache line is formed by
`retrieving the next instruction to be executed and a certain
`number of instructions folloWing the next instruction to be
`executed. That Way, if the subsequent instructions are in fact
`required to be executed, they Will be immediately available
`to the CPU from Within the cache line of the cache. Because
`of the sequential nature of programs, the bene?ts of caching
`also applies to data used by the programs.
`Because the internal cache is ?lled a cache line at a time,
`many microprocessors can accept data in a burst mode. In a
`typical burst read, the microprocessor speci?es the ?rst
`address of the data or instructions to be read into a cache
`line. Then, the data or instructions that are stored at the
`addresses of the cache line are sent sequentially from Where
`they are stored Within the computer system to the micro
`processor.
`Frequently the internal cache of the microprocessor is
`formed using static random access memory (SRAM).
`Because each SRAM cell is formed by six to eight
`transistors, there is only room on a microprocessor chip for
`a relatively small SRAM cache. Furthermore, SRAM is
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`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1007, p. 17
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`volatile meaning that SRAM retains the information stored
`as long as there is enough poWer to run the device. If poWer
`is removed, the contents of the SRAM cache are lost.
`Some microprocessors are dynamic, meaning that if
`poWer is removed from them, When poWer is restored they
`cannot return directly to the state they Were in When the
`poWer Was removed. When poWer is restored the micropro
`cessor must be reinitialiZed, and at least some of the pro
`cessing progress previously made Will probably be lost.
`Other microprocessors are static, meaning that they can be
`placed in an energy saving deep poWerdoWn mode, and then
`be returned relatively quickly to the state they Were in
`immediately before they entered the deep poWerdoWn mode.
`As mentioned earlier, data and instructions are stored
`Within the computer system and provided to the micropro
`cessor over one (or more) bus systems. Because most types
`of relatively fast random access memory are both volatile
`and relatively expensive, a typical computer system stores
`code and data on relatively inexpensive, nonvolatile
`memory store such as a ?oppy disk or hard disk.
`The typical computer system also has a main memory
`made of volatile memory because the nonvolatile memory
`has a relatively sloW access speed. When a program is to be
`executed, the computer system uses a technique knoWn as
`shadoWing to copy the code and data required to execute the
`program from the sloW nonvolatile memory to the faster
`volatile memory. The shadoW copy in the main memory is
`then used to execute the program. If any changes are made
`to the shadoW copy during the course of the program
`execution, the shadoW copy can be copied back to the sloWer
`nonvolatile memory, When the program ?nishes execution.
`Furthermore, because an unexpected poWer failure Will
`cause the contents of the volatile main memory to be lost, it
`is common to save intermediate results generated during the
`course of execution of the program.
`The most common form of main memory is dynamic
`random access memory (DRAM). DRAM is more com
`monly used than SRAM, even though it is sloWer than
`SRAM because DRAM can hold approximately four times
`as much data as a SRAM of the same complexity.
`DRAMs store information is integrated circuits that con
`tain capacitors. Because capacitors lose their charge over
`time, DRAMs must be controlled by logic that causes the
`DRAM chips to continuously “refresh” (recharge). When a
`DRAM is being refreshed, it cannot be read from, or Written
`to, by the microprocessor. Thus, if the microprocessor must
`access the DRAM While it is being refreshed, one or more
`Wait states occur.
`In some computer systems, SRAM is used as main
`memory in place of DRAM. One advantage of using SRAM
`as main memory is that SRAM is relatively faster to access
`than DRAM. Furthermore, because SRAM does not need to
`be refreshed, it is alWays available for access by the
`microprocessor, thereby eliminating the DRAM associated
`need for the microprocessor to include Wait states When
`accesses are attempted While the DRAM is being refreshed.
`Moreover, the lack of a refresh requirement simpli?es
`designing a computer system having SRAM based main
`memory because one does not have to Worry about control
`ling refresh cycles. In fact, a simple battery back-up can be
`supplied to preserve the contents of the SRAM in the event
`of a poWer failure. Of course, if the battery back-up fails, the
`contents of the SRAM main memory Will be lost.
`Rather than building a main memory completely from
`SRAM, it is more common to implement the main memory
`using DRAM, and then to supplement the DRAM based
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`main memory With a SRAM based external cache memory
`(i.e. a cache memory that is external to the microprocessor
`chip). Because the external cache is not contained on the
`microprocessor chip, it can typically be made to store more
`data and instructions than can be stored by the internal
`cache. Because the external cache is not located on the
`microprocessor chip, hoWever, it must supply the data and
`instructions to the microprocessor using one of the buses
`that often form bottlenecks for data and instructions entering
`and leaving the microprocessor chip.
`A high speed microprocessor chip typically interfaces
`With the rest of the computer system using one or tWo high
`speed buses. The ?rst of these buses is a relatively high
`speed asynchronous bus called a main memory bus. The
`second of these buses is a relatively high speed synchronous
`bus called a local bus. The typical operating speed of main
`memory and local buses is in the range of 16 to 33 MHZ and
`the trend is toWards increasingly faster buses.
`Although most microprocessors can interface directly
`With a main memory bus, some microprocessors do not
`provide an external interface to a local bus. These micro
`processor typically interface With a relatively sloW speed
`synchronous bus called an expansion bus. The typical oper
`ating speed of an expansion bus is in the range of 8 to 12
`MHZ.
`The main memory (or DRAM) bus is used by the micro
`processor chip to access main memory. Usually, rather than
`interfacing directly to the DRAM chips, the microprocessor
`is coupled to a DRAM controller chip that, in turn, is
`coupled to the DRAM chip or chips. The DRAM controller
`controls accesses to the DRAM chips initiated by the
`microprocessor. The DRAM controller also controls over
`head maintenance such as the refresh cycles for periodically
`refreshing the DRAM contents. Some microprocessors have
`the DRAM controller built directly into them. Frequently,
`the DRAM or SRAM chips are contained in surface-mount
`packages and several DRAMs or SRAMs are attached to a
`small circuit board to form What is called a Single In-line
`Memory Module (SIMM). One can then relatively easily
`modify the total amount (or the access speed) of main
`memory in a computer system by simply sWapping one type
`of SIMM for another. A SRAM based external cache may
`also be coupled to the microprocessor through the DRAM
`bus.
`If a computer system has a local bus, then the micropro
`cessor can access devices coupled to the local bus at a
`relatively fast speed. Thus, high bandWidth devices such as
`graphics adapter cards and fast input/output devices are
`typically coupled directly to the local bus. Sometimes the
`external cache is coupled to the local bus rather than to the
`DRAM bus. It is also possible to supplement (or replace) the
`main memory on the main memory bus by coupling DRAM
`to the local bus using a DRAM controller designed to
`interface With the local bus.
`Each device coupled to the local bus has an associated
`capacitive load. As the load on the local bus is increased, the
`maximum operating speed for the local bus decreases and
`the poWer required to drive the bus increases. Therefore, one
`device coupled to the local bus can be a peripheral bus
`bridge from the local bus to another bus called a high speed
`peripheral bus (eg a peripheral component interconnnect
`(PCI) bus). The bus bridge isolates the load of the devices
`coupled to the high speed peripheral bus from the high speed
`local bus.
`Another device coupled to the local bus is typically an
`expansion bus bridge that couples the high performance
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`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1007, p. 18
`
`

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`6,026,465
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`5
`local bus to a lower performance expansion bus. The loW
`bandwidth components of the computer system are then
`coupled to the loWer performance expansion bus. One type
`of device that is typically coupled to the expansion bus uses
`?ash memory. Flash memory typically is a high-density,
`nonvolatile, read-Write memory. Examples of ?ash memory
`based devices include BIOS ROM and hard disk substitutes.
`Flash memories differ from conventional EEPROMs
`(electrically erasable programmable read only memories)
`With respect to erasure. Conventional EEPROMs use a
`select transistor for individual byte erase control. Flash
`memories, on the other hand, achieve much higher density
`With single transistor cells. For a typical ?ash memory array,
`a logical “one” means that feW if any electrons are stored on
`a ?oating gate associated With a bit cell. A logical “Zero”
`means that many electrons are stored on the ?oating gate
`associated With the bit cell. Each bit of the ?ash memory
`array cannot be overWritten from a logical Zero state to a
`logical one state Without a prior erasure. During a ?ash erase
`operation, a high voltage is supplied to the sources of every
`memory cell in a block or in the entire chip simultaneously.
`This results in a full array or a full block erasure.
`After a ?ash memory array has been erased, a logical one
`is stored in each bit cell of the ?ash memory array. Each
`single bit cell of the ?ash memory array can then be
`programmed (overWritten) from a logical one to a logical
`Zero, given that this entails simply adding electrons to a
`?oating gate that contains the intrinsic number of electrons
`associated With the erased state. Program operations for
`?ash memories are also referred to as Write operations.
`The read operation associated With a typical ?ash memory
`array closely resembles the read operation associated With
`other read-only memory devices. A read operation for a
`typical high speed ?ash memory array takes on the order of
`80 nanoseconds (nS). Write and erase operations for a ?ash
`memory array are, hoWever, signi?cantly sloWer. Typically,
`an erase operation takes on the order of one second. AWrite
`operation for a single Word of a ?ash memory array takes on
`the order of 10 microseconds.
`British patent document no. GB 2 251 324 A, published
`Jul. 1, 1992, describes a computer system that uses ?ash
`memory. The patent document discloses various architec
`tures to incorporate a ?ash memory into a computer system.
`One architecture referred to therein is a variable ?le struc
`ture. For the viable ?le structure, computer code is stored
`contiguously in ?ash memory, alloWing a CPU to execute
`computer code directly from the ?ash memory array Without
`the need for RAM. Adirect mapped variable ?le structure is
`described that alloWs direct code execution from all of the
`?ash memory array. Apage mapped variable ?le structure is
`also described that alloWs direct code execution from a
`portion of the ?ash memory array. Thus, ?ash memory can
`serve as the main memory Within portable computers, pro
`viding user functions similar to those of disk-based systems.
`A ROM-executable DOS is available commercially and
`provides several bene?ts to both system manufacturers and
`ultimately end users. First, because most of the operating
`system is composed of ?xed code, the amount of system
`RAM required to execute DOS is reduced from 50K to 15K,
`thereby conserving system space and poWer. Secondly, DOS
`can noW be permanently stored in, and executed from, a
`single ROM-type of device such as ?ash memory. This
`enables systems to be provided that are ready to run right out
`of the box. Lastly, users enjoy “instant on” performance
`because the traditional disk-to-DRAM boot function and
`softWare doWnloading steps are eliminated.
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`For example, by storing application softWare and operat
`ing system code in a Resident Flash Array (RFA), users
`enjoy virtually instant-on performance and in-place code
`execution. An RFA also protects against softWare obsoles
`cence because, unlike ROM, it is in-system updatable.
`Resident softWare, stored in ?ash rather than disk, extends
`battery life and increases system reliability.
`Because erasing and Writing data to ?ash memory is a
`distinctly