111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US008301833Bl
`
`c12) United States Patent
`Chen et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,301,833 Bl
`Oct. 30, 2012
`
`(54) NON-VOLATILE MEMORY MODULE
`
`(75)
`
`Inventors: Chi-She Chen, Walnut, CA (US);
`Jeffrey C. Solomon, Irvine, CA (US);
`Scott Milton, Irvine, CA (US); Jayesh
`Bhakta, Cerritos, CA (US)
`
`(73) Assignee: Netlist, Inc., Irvine, CA (US)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 638 days.
`
`5,519,663 A
`6,158,015 A
`6,336,174 B1
`6,336,176 B1
`6,487,623 B1
`6,658,507 B1
`6,799,244 B2
`7,409,590 B2
`2002/0083368 A1
`2004/0190210 A1
`2007/0192627 A1 *
`2008/0195806 A1 *
`* cited by examiner
`
`5/1996
`12/2000
`1/2002
`1/2002
`1112002
`12/2003
`9/2004
`8/2008
`6/2002
`9/2004
`8/2007
`8/2008
`
`Harper, Jr. et a!.
`Klein
`Li eta!.
`Leyda eta!.
`Emerson et a!.
`Chan
`Tanaka eta!.
`Moshayedi et a!.
`Abe eta!.
`Leete
`Oshikiri ........................ 713/191
`Cope ............................. 7111111
`
`(21) Appl. No.: 12/240,916
`
`(22) Filed:
`
`Sep.29,2008
`
`Related U.S. Application Data
`
`(63) Continuation of application No. 12/131,873, filed on
`Jun. 2, 2008, now abandoned.
`
`(60) Provisional application No. 60/941,586, filed on Jun.
`1, 2007.
`
`(51)
`
`Int. Cl.
`G06F 12100
`(2006.01)
`(52) U.S. Cl. ........ 7111104; 711/160; 711/161; 711/162;
`710/10
`(58) Field of Classification Search .................. 711/160,
`711/161, 162, 104; 710/10
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`4,420,821 A
`12/1983 Hoffman
`4,449,205 A
`5/1984 Hoffman
`
`Primary Examiner- Midys Rojas
`(74) Attorney, Agent, or Firm- Nixon Peabody LLP;
`Khaled Shami
`
`(57)
`
`ABSTRACT
`
`Certain embodiments described herein include a memory
`system which can communicate with a host system such as a
`disk controller of a computer system. The memory system
`can include volatile and non-volatile memory and a controller
`which are configured such that the controller backs up the
`volatile memory using the non-volatile memory in the event
`of a trigger condition. In order to power the system in the
`event of a power failure or reduction, the memory system can
`include a secondary power source which is not a battery and
`may include, for example, a capacitor or capacitor array. The
`memory system can be configured such that the operation of
`the volatile memory is not adversely affected by the non(cid:173)
`volatile memory or the controller when the volatile memory is
`interacting with the host system.
`
`30 Claims, 12 Drawing Sheets
`
`500
`
`l
`
`5!0
`
`;
`
`Operate volatile memory at first frequency
`in first mode
`
`I
`
`5\
`
`550 ;
`
`Operate non-volatile memory at
`second frequency in second
`mode
`
`Operate volatile memory at
`third frequency in second
`mode
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1001, p. 1
`
`

`
`""""' Oo w w = """"'
`00 w =
`
`rJl
`d
`
`N
`....
`0 .....
`....
`.....
`rFJ =(cid:173)
`
`('D
`('D
`
`N
`~0
`(.H
`:-+-
`0
`
`(')
`
`0 ....
`
`N
`
`~ = ~
`
`~
`~
`~
`•
`00
`~
`
`Standard DIMM interface
`
`22
`
`FIG. 1
`
`I ADDR/CONT
`
`DATA
`
`SWITCH 1-----------1
`
`52
`
`SWITCH
`
`ADDRICONT
`
`DATA
`
`L ________ ----l
`/
`
`62
`
`:
`70:
`r-----------------1
`
`FPGA
`
`I
`I
`I
`
`J
`
`L~ ______ j ____ j
`
`I
`
`I
`
`IADDRICONT
`I
`
`MCU
`
`lDm
`
`.
`
`I
`I
`I
`
`L ___________________ i
`:
`
`I
`I
`I
`
`OUT,Brr.LL,
`PO'v'V_E~ t / 90
`
`------,
`
`_____________ _j
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`20
`
`I
`/-.JO
`
`----L -----'
`
`I
`/-40
`
`----
`
`42
`
`flO
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1001, p. 2
`
`

`
`U.S. Patent
`
`Oct. 30, 2012
`
`Sheet 2 of 12
`
`US 8,301,833 Bl
`
`1-:z
`0
`~
`D
`D
`<(
`
`<(
`!;(
`D
`
`1-:z
`0
`~
`~ ----,
`
`D
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`,----...1
`I
`I
`I
`I
`
`r----------,
`I
`I
`I
`I
`I
`I l(cid:173)
`Iz
`IO
`10
`l(i:
`ID
`ID
`I<(
`
`:::c
`0
`1-
`
`~
`
`r------
`
`1
`
`I
`I
`I
`
`I
`I
`I
`I
`
`~~ I
`,---_j
`: ~
`
`I
`
`~~
`
`I
`I
`I
`I
`I a:: 1-
`1----...J lw=>
`I $:a....__ __ ..J
`lo~
`:a...o
`I
`I
`I
`I
`L _____________ _j
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1001, p. 3
`
`

`
`""""' Oo w w = """"'
`00 w =
`
`rJl
`d
`
`N
`....
`0 .....
`
`(.H
`
`.....
`rFJ =(cid:173)
`
`('D
`('D
`
`N
`~0
`(.H
`:-+-
`0
`
`(')
`
`0 ....
`
`N
`
`~ = ~
`
`~
`~
`~
`•
`00
`~
`
`22
`
`82
`
`FIG. 3
`
`ADDR/CONT
`
`DATA
`
`90
`
`ADDR/CONT
`
`DATA
`
`\____
`62
`
`52
`
`SWITCH
`
`6[1,70
`
`I ADDRICONT
`
`DATA
`
`------,
`
`_____________ ....J
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`I L-------------------
`
`I
`I
`I
`I
`I
`1
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`_________ j
`
`--------
`
`------~
`
`I
`
`/-30
`
`20
`
`('0
`
`:
`,---------
`
`l
`
`I
`___ ..L
`/-40
`
`----
`42
`
`I L----------
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`1
`r--
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1001, p. 4
`
`

`
`""""' Oo w w = """"'
`00 w =
`
`rJl
`d
`
`N
`....
`0 .....
`
`.....
`rFJ =(cid:173)
`
`('D
`('D
`
`.j;o.
`
`N
`~0
`(.H
`:-+-
`0
`
`(')
`
`0 ....
`
`N
`
`~ = ~
`
`~
`~
`~
`•
`00
`~
`
`FIG. 4B
`
`DRAM
`
`!80
`
`FIG. 4A
`
`DRAM
`
`!80
`
`address/control
`
`clock ---1
`
`address/control
`
`!50
`
`system
`
`clock ---1
`
`address/control
`
`system
`
`Vdd_/
`
`!52
`
`70
`
`!50
`
`70
`
`!50
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1001, p. 5
`
`

`
`U.S. Patent
`
`Oct. 30, 2012
`
`Sheet 5 of 12
`
`US 8,301,833 Bl
`
`e ....... c::
`
`0
`(_)
`Us
`en
`.._
`Q)
`""0
`""0
`co
`
`c::
`0
`(_)
`
`e .......
`-en
`
`en
`.._
`Q)
`"'0
`""0 co
`
`"'0
`
`"'0 >
`
`~
`'
`
`~
`'
`
`~
`(_)
`0
`(_)
`
`lJ
`'i-
`.
`0
`u::
`
`:2
`w
`I-
`en
`>-
`en
`
`~
`'
`
`<:(
`c.9
`0....
`LL
`
`~ ..........
`
`~
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1001, p. 6
`
`

`
`""""' Oo w w = """"'
`00 w =
`
`rJl
`d
`
`N
`......
`0 ......
`0\
`......
`rFJ =(cid:173)
`
`('D
`('D
`
`N
`0 ......
`N
`~0
`(.H
`:-+-
`0
`
`(')
`
`~ = ~
`
`~
`~
`~
`•
`00
`~
`
`lsol Dev
`FPGA
`
`FPGA
`
`lsol Dev
`
`FPGA
`Flash
`Drams
`
`!02
`FPGA
`Flash
`Drams
`
`..; I CONVERTER f-t-L__.-
`!07
`
`BUCK-BOOST
`
`1
`
`L ____ _I _____ J
`
`I
`
`I
`I
`I
`1
`
`!05
`
`!04
`
`1 r ,
`1
`I
`I
`1
`1
`I
`I
`,-----------,
`from FPGA --.-oi >---'
`
`,------'-1
`
`~
`
`!20
`
`Converter
`
`Buck
`
`to NVDIMM
`
`!48
`
`FIG. 5
`
`Power Module
`
`gnd
`
`I l' !!2
`
`I
`I
`I
`I
`I
`I
`I
`
`L.-....... --~ l
`
`-----'
`
`[
`( i
`!40 r------------------,
`
`l capacitor
`
`Array
`
`!42
`
`!!0
`
`!'oo
`
`_j
`
`146
`
`-
`
`!JO
`
`Conv.
`Boost
`Buck/
`
`!44
`
`Contrlr
`PWM
`
`I
`
`gnd
`
`Vdd
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1001, p. 7
`
`

`
`U.S. Patent
`
`Oct. 30, 2012
`
`Sheet 7 of 12
`
`US 8,301,833 Bl
`
`200
`
`j
`
`Provide first voltage from input power supply
`and second voltage from first power subsystem
`
`210
`
`No
`
`Yes
`
`220
`
`Provide first voltage and second voltage from
`first power subsystem
`
`2.3'0
`
`Charge second power subsystem
`
`No
`
`Yes
`
`250
`
`Provide first voltage and second voltage from
`second power subsystem
`
`FIG. 6
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1001, p. 8
`
`

`
`U.S. Patent
`
`Oct. 30, 2012
`
`Sheet 8 of 12
`
`US 8,301,833 Bl
`
`JOO
`
`j
`
`Communicate data between volatile
`memory and host system in a first mode
`
`vJIO
`
`Store a first copy of data from the volatile
`memory to the non-volatile memory when
`in a second mode
`
`vJ2o
`
`Restore the first copy of data from the non(cid:173)
`volatile memory to the volatile memory
`
`-------- JJ 0
`
`J40
`
`\
`
`Erase the first copy of data from
`the non-volatile memory
`
`J50
`;
`Copy second copy of data from
`volatile memory to non-volatile
`memory in a second mode
`
`Restore the second copy of data from the
`non-volatile memory to the volatile memory
`
`~J60
`
`FIG. 7
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1001, p. 9
`
`

`
`""""' Oo w w = """"'
`00 w =
`
`rJl
`d
`
`N
`....
`0 .....
`\0
`.....
`rFJ =(cid:173)
`
`('D
`('D
`
`N
`~0
`(.H
`~
`(')
`0
`
`0 ....
`
`N
`
`~ = ~
`
`~
`~
`~
`•
`00
`~
`
`FCK_6P25 ·
`
`FPGA
`
`416'
`
`FIG. 8
`
`FCLK62P5:::3
`FCLK62PC2
`FCLK62P5 1
`
`(62.5 MHz to Flash Memory)
`
`-
`
`p clock to DRAM PLL)
`
`(backu
`
`BUCK_125+/-
`
`(
`408
`
`446'
`
`Clk125
`I
`406'
`
`PCLK4 +/-
`\
`4JO
`
`440
`
`4J2
`
`Clock Generator
`
`(125MHz)
`
`404
`
`I
`
`Oscillator
`25 MHz
`
`\
`402
`
`-
`
`DRAM
`
`424
`
`400
`
`/
`
`Dram_Cik
`
`(
`
`Differentlclock mux
`
`42J
`
`422
`
`BUCK_125 +1-
`
`408
`I
`
`200 MHz System Clock
`
`I
`420
`
`rs to
`
`Differential clock pa
`
`I
`
`PCLK4 +/-(to FPGA)-----4JO
`PCLK3 +/-(to Register)___.---42b
`PCLK2 +/-
`PCLK1 +/-
`PGU<O ,,_ }
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1001, p. 10
`
`

`
`U.S. Patent
`
`Oct. 30, 2012
`
`Sheet 10 of 12
`
`US 8,301,833 Bl
`
`500
`
`)
`
`510
`
`!
`
`Operate volatile memory at first frequency
`in first mode
`
`I
`
`520
`
`\
`
`Operate non-volatile memory at
`second frequency in second
`mode
`
`5JO
`l_
`Operate volatile memory at
`third frequency in second
`mode
`
`FIG. 9
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1001, p. 11
`
`

`
`U.S. Patent
`
`Oct. 30, 2012
`
`Sheet 11 of 12
`
`US 8,301,833 Bl
`
`<(
`<.9
`0..
`LL
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1001, p. 12
`
`

`
`U.S. Patent
`
`Oct. 30, 2012
`
`Sheet 12 of 12
`
`US 8,301,833 Bl
`
`600
`
`j
`
`v 6!0
`
`Communicate data words between volatile
`memory and host system in first mode
`
`- - - - - - - - - -~~620
`
`626 t Write entire data word from buffer
`
`I
`I
`I __________ I
`
`FIG. 11
`
`1
`
`1
`
`Transfer data words from volatile memory
`system to non-volatile memory system
`
`622
`
`I
`I
`~ Store first slice of data word in
`I
`I
`I
`
`buffer
`
`624 ~ Store second slice of data word in
`
`buffer
`
`I
`I
`I
`
`to non-volatile memory
`
`r
`I
`I
`I
`I
`I
`
`I
`I
`I
`I
`I
`I
`I
`I
`
`I
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1001, p. 13
`
`

`
`US 8,301,833 Bl
`
`1
`NON-VOLATILE MEMORY MODULE
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is a continuation of U.S. patent applica(cid:173)
`tion Ser. No. 12/131,873, filed Jun. 2, 2008, which claims the
`benefit ofU.S. Provisional Application No. 60/941,586, filed
`Jun. 1, 2007. Each of these applications is incorporated in its
`entirety by reference herein.
`
`BACKGROUND
`
`Certain types of memory modules comprise a plurality of
`dynamic random-access memory (DRAM) devices mounted
`on a printed circuit board (PCB). These memory modules are
`typically mounted in a memory slot or socket of a computer
`system (e.g., a server system or a personal computer) and are
`accessed by the computer system to provide volatile memory
`to the computer system.
`Volatile memory generally maintains stored information
`only when it is powered. Batteries have been used to provide
`power to volatile memory during power failures or interrup(cid:173)
`tions. However, batteries may require maintenance, may need
`to be replaced, are not environmentally friendly, and the sta(cid:173)
`tus of batteries can be difficult to monitor.
`Non-volatile memory can generally maintain stored infor(cid:173)
`mation while power is not applied to the non-volatile
`memory. In certain circumstances, it can therefore be useful
`to backup volatile memory using non-volatile memory.
`
`SUMMARY
`
`In certain embodiments, a memory system coupled to a
`computer system is provided which includes a volatile
`memory subsystem, a non-volatile memory subsystem, and a
`controller operatively coupled to the non-volatile memory
`subsystem. The memory system can also include at least one
`circuit configured to selectively operatively decouple the con(cid:173)
`troller from the volatile memory subsystem.
`In some embodiments, a power module for providing a
`plurality of voltages to a memory system is described. The
`power module includes non-volatile and volatile memory,
`and the plurality of voltages include at least a first voltage and
`a second voltage. The power module of certain embodiments
`includes an input providing a third voltage to the power mod(cid:173)
`ule and a voltage conversion element configured to provide
`the second voltage to the memory system. The power module
`also includes a first power element configured to selectively
`provide a fourth voltage to the conversion element. The power
`module further includes a second power element configured
`to selectively provide a fifth voltage to the conversion ele(cid:173)
`ment. The power module can be configured to selectively
`provide the first voltage to the memory system either from the 55
`conversion element or from the input.
`The power module can be configured to be operated in at
`least three states in certain embodiments. In a first state, the
`first voltage is provided to the memory system from the input
`and the fourth voltage is provided to the conversion element 60
`from the first power element. In a second, state the fourth
`voltage is provided to the conversion element from the first
`power element and the first voltage is provided to the memory
`system from the conversion element. In a third state, the fifth
`voltage is provided to the conversion element from the second 65
`power element and the first voltage is provided to the memory
`system from the conversion element.
`
`15
`
`2
`A method of providing a first voltage and a second voltage
`to a memory system including volatile and non-volatile
`memory subsystems is provided in certain embodiments. The
`method includes, during a first condition, providing the first
`voltage to the memory system from an input power supply
`and providing the second voltage to the memory system from
`a first power subsystem. The method further includes detect(cid:173)
`ing a second condition and, during the second condition,
`providing the first voltage and the second voltage to the
`10 memory system from the first power subsystem. The method
`also includes charging a second power subsystem and detect(cid:173)
`ing a third condition. During the third condition, the method
`includes providing the first voltage and the second voltage to
`the memory system from the second power subsystem.
`In certain embodiments, a method is provided for control-
`ling a memory system operatively coupled to a host system
`and which includes a volatile memory subsystem and a non(cid:173)
`volatile memory subsystem. The method can include operat(cid:173)
`ing the volatile memory subsystem at a first frequency when
`20 the memory system is in a first mode of operation in which
`data is communicated between the volatile memory sub(cid:173)
`system and the host system. In certain embodiments, the
`method further includes operating the non-volatile memory
`subsystem at a second frequency when the memory system is
`25 in a second mode of operation in which data is communicated
`between the volatile memory subsystem and the non-volatile
`memory subsystem. The method can also include operating
`the volatile memory subsystem at a third frequency when the
`memory system is in the second mode of operation, the third
`30 frequency less than the first frequency.
`In certain embodiments, a method is provided for control(cid:173)
`ling a memory system operatively coupled to a host system.
`The memory system includes a volatile memory subsystem
`and a non-volatile memory subsystem. In certain embodi-
`35 ments, the method includes communicating data words
`between the volatile memory subsystem and the host system
`when the memory system is in a first mode of operation. The
`method can further include transferring data words from the
`volatile memory subsystem to the non-volatile memory sub-
`40 system when the memory system is in a second mode of
`operation. Transferring each data word can include storing a
`first portion of the data word in a buffer, storing a second
`portion of the data word in the buffer, and writing the entire
`data word from the buffer to the non-volatile memory sub-
`45 system.
`A memory system operatively coupled to a host system is
`provided in certain embodiments. The memory system can
`include a volatile memory subsystem and a non-volatile
`memory subsystem comprising at least 100 percent more
`50 storage capacity than does the volatile memory subsystem.
`The memory system includes a controller operatively coupled
`to the volatile memory subsystem and operatively coupled to
`the non-volatile memory subsystem, the controller config(cid:173)
`ured to allow data to be communicated between the volatile
`memory subsystem and the host system when the memory
`system is operating in a first state and to allow data to be
`communicated between the volatile memory subsystem and
`the non-volatile memory subsystem when the memory sys(cid:173)
`tem is operating in a second state.
`A method of controlling a memory system operatively
`coupled to a host system is provided in certain embodiments.
`The memory system includes a volatile memory subsystem
`and a non-volatile memory subsystem. The method can
`include communicating data between the volatile memory
`subsystem and the host system when the memory system is in
`a first mode of operation. The method of certain embodiments
`further includes storing a first copy of data from the volatile
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1001, p. 14
`
`

`
`US 8,301,833 Bl
`
`3
`memory subsystem to the non-volatile memory subsystem at
`a first time when the memory system is in a second mode of
`operation. The method may further include restoring the first
`copy of data from the non-volatile memory subsystem to the
`volatile memory subsystem and erasing the first copy of data
`from the non-volatile memory subsystem. In certain embodi(cid:173)
`ments, the method also includes storing a second copy of data
`from the volatile memory subsystem to the non-volatile
`memory subsystem at a second time when the memory sys(cid:173)
`tem is in the second mode of operation, wherein storing the 10
`second copy begins before the first copy is completely erased
`from the non-volatile memory subsystem.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`4
`power the system in the event of a power failure or reduction,
`the memory system can include a secondary power source
`which does not comprise a battery and may include, for
`example, a capacitor or capacitor array.
`In certain embodiments, the memory system can be con(cid:173)
`figured such that the operation of the volatile memory is not
`adversely affected by the non-volatile memory or by the
`controller when the volatile memory is interacting with the
`host system. For example, one or more isolation devices may
`isolate the non-volatile memory and the controller from the
`volatile memory when the volatile memory is interacting with
`the host system and may allow communication between the
`volatile memory and the non-volatile memory when the data
`of the volatile memory is being restored or backed-up. This
`15 configuration generally protects the operation of the volatile
`memory when isolated while providing backup and restore
`capability in the event of a trigger condition, such as a power
`failure.
`In certain embodiments described herein, the memory sys(cid:173)
`tem includes a power module which provides power to the
`various components of the memory system from different
`sources based on a state of the memory system in relation to
`a trigger condition (e.g., a power failure). The power module
`may switch the source of the power to the various components
`in order to efficiently provide power in the event of the power
`failure. For example, when no power failure is detected, the
`power module may provide power to certain components,
`such as the volatile memory, from system power while charg(cid:173)
`ing a secondary power source (e.g., a capacitor array). In the
`event of a power failure or other trigger condition, the power
`module may power the volatile memory elements using the
`previously charged secondary power source.
`In certain embodiments, the power module transitions rela(cid:173)
`tively smoothly from powering the volatile memory with
`system power to powering it with the secondary power
`source. For example, the memory system may power volatile
`memory with a third power source from the time the memory
`system detects that power failure is likely to occur until the
`time the memory system detects that the power failure has
`actually occurred.
`In certain embodiments, the volatile memory system can
`be operated at a reduced frequency during backup and/or
`restore operations which can improve the efficiency of the
`system and save power. In some embodiments, during backup
`and/or restore operations, the volatile memory communicates
`with the non-volatile memory by writing and/or reading data
`words in bit-wise slices instead of by writing entire words at
`once. In certain embodiments, when each slice is being writ(cid:173)
`ten to or read from the volatile memory the unused slice( s) of
`volatile memory is not active, which can reduce the power
`consumption of the system.
`In yet other embodiments, the non-volatile memory can
`include at least 100 percent more storage capacity than the
`volatile memory. This configuration can allow the memory
`system to efficiently handle subsequent trigger conditions.
`FIG.1 is a block diagram of an example memory system 10
`compatible with certain embodiments described herein. The
`memory system 10 can be coupled to a host computer system
`and can include a volatile memory subsystem 30, a non-
`60 volatile memory subsystem 40, and a controller 62 opera(cid:173)
`tively coupled to the non-volatile memory subsystem 40. In
`certain embodiments, the memory system 10 includes at least
`one circuit 52 configured to selectively operatively decouple
`the controller 62 from the volatile memory subsystem 30.
`In certain embodiments, the memory system 10 comprises
`a memory module. The memory system 10 may comprise a
`printed-circuit board (PCB) 20. In certain embodiments, the
`
`FIG. 1 is a block diagram of an example memory system
`compatible with certain embodiments described herein.
`FIG. 2 is a block diagram of an example memory module
`with ECC (error-correcting code) having a volatile memory
`subsystem with nine volatile memory elements and a non- 20
`volatile memory subsystem with five non-volatile memory
`elements in accordance with certain embodiments described
`herein.
`FIG. 3 is a block diagram of an example memory module
`having a microcontroller unit and logic element integrated 25
`into a single device in accordance with certain embodiments
`described herein.
`FIGS. 4A-4C schematically illustrate example embodi(cid:173)
`ments of memory systems having volatile memory sub(cid:173)
`systems comprising registered dual in-line memory modules 30
`in accordance with certain embodiments described herein.
`FIG. 5 schematically illustrates an example power module
`of a memory system in accordance with certain embodiments
`described herein.
`FIG. 6 is a flowchart of an example method of providing a 35
`first voltage and a second voltage to a memory system includ(cid:173)
`ing volatile and non-volatile memory subsystems.
`FIG. 7 is a flowchart of an example method of controlling
`a memory system operatively coupled to a host system and
`which includes at least 100 percent more storage capacity in 40
`non-volatile memory than in volatile memory.
`FIG. 8 schematically illustrates an example clock distribu(cid:173)
`tion topology of a memory system in accordance with certain
`embodiments described herein.
`FIG. 9 is a flowchart of an example method of controlling 45
`a memory system operatively coupled to a host system, the
`method including operating a volatile memory subsystem at a
`reduced rate in a back-up mode.
`FIG. 10 schematically illustrates an example topology of a
`connection to transfer data slices from two DRAM segments 50
`of a volatile memory subsystem of a memory system to a
`controller of the memory system.
`FIG. 11 is a flowchart of an example method of controlling
`a memory system operatively coupled to a host system, the
`method including backing up and/or restoring a volatile 55
`memory subsystem in slices.
`
`DETAILED DESCRIPTION
`
`Certain embodiments described herein include a memory
`system which can communicate with a host system such as a
`disk controller of a computer system. The memory system
`can include volatile and non-volatile memory, and a control(cid:173)
`ler. The controller backs up the volatile memory using the
`non-volatile memory in the event of a trigger condition. Trig- 65
`ger conditions can include, for example, a power failure,
`power reduction, request by the host system, etc. In order to
`
`Petitioners SK hynix Inc., SK hynix America Inc. and SK hynix memory solutions Inc.
`Ex. 1001, p. 15
`
`

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`US 8,301,833 Bl
`
`5
`memory system 10 has a memory capacity of 512-MB, 1-GB,
`2-GB, 4-GB, or 8-GB. Other volatile memory capacities are
`also compatible with certain embodiments described herein.
`In certain embodiments, the memory system 10 has a non(cid:173)
`volatile memory capacity of 512-MB, 1-GB, 2-GB, 4-GB,
`8-GB, 16-GB, or 32-GB. Other non-volatile memory capaci(cid:173)
`ties are also compatible with certain embodiments described
`herein. In addition, memory systems 10 having widths of 4
`bytes, 8 bytes, 16 bytes, 32 bytes, or 32 bits, 64 bits, 128 bits,
`256 bits, as well as other widths (in bytes or in bits), are 10
`compatible with embodiments described herein. In certain
`embodiments, the PCB 20 has an industry-standard form
`factor. For example, the PCB 20 can have a low profile (LP)
`form factor with a height of 30 millimeters and a width of
`133.35 millimeters. In certain other embodiments, the PCB 15
`20 has a very high profile (VHP) form factor with a height of
`50 millimeters or more. In certain other embodiments, the
`PCB 20 has a very low profile (VLP) form factor with a height
`of 18.3 millimeters. Other form factors including, but not
`limited
`to,
`small-outline
`(SO-DIMM),
`unbuffered 20
`(UDIMM), registered (RDIMM), fully-buffered (FBDIMM),
`mini-DIMM, mini-RDIMM, VLP mini-DIMM, micro(cid:173)
`DIMM, and SRAM DIMM are also compatible with certain
`embodiments described herein. For example, in other
`embodiments, certain non-DIMM form factors are possible 25
`such as, for example, single in-line memory module (SIMM),
`multi-media card (MMC), and small computer system inter(cid:173)
`face (SCSI).
`In certain preferred embodiments, the memory system 10
`is in electrical communication with the host system. In other 30
`embodiments, the memory system 10 may communicate with
`a host system using some other type of communication, such
`as, for example, optical communication. Examples of host
`systems include, but are not limited to, blade servers, 1 U
`servers, personal computers (PCs), and other applications in 35
`which space is constrained or limited. The memory system 10
`can be in communication with a disk controller of a computer
`system, for example. The PCB 20 can comprise an interface
`22 that is configured to be in electrical communication with
`the host system (not shown). For example, the interface 22 40
`can comprise a plurality of edge connections which fit into a
`corresponding slot connector of the host system. The inter(cid:173)
`face 22 of certain embodiments provides a conduit for power
`voltage as well as data, address, and control signals between
`the memory system 10 and the host system. For example, the 45
`interface 22 can comprise a standard 240-pin DDR2 edge
`connector.
`The volatile memory subsystem 30 comprises a plurality of
`volatile memory elements 32 and the non-volatile memory
`subsystem 40 comprises a plurality of non-volatile memory
`elements 42. Certain embodiments described herein advan(cid:173)
`tageously provide non-volatile storage via the non-volatile
`memory subsystem 40 in addition to high-performance (e.g.,
`high speed) storage via the volatile memory subsystem 30. In
`certain embodiments, the first plurality of volatile memory
`elements 32 comprises two or more dynamic random-access
`memory (DRAM) elements. Types of DRAM elements 32
`compatible with certain embodiments described herein
`include, but are not limited to, DDR, DDR2, DDR3, and
`synchronous DRAM (SDRAM). For example, in the block
`diagram of FIG. 1, the first memory bank 30 comprises eight
`64Mx8 DDR2 SDRAM elements 32. The volatile memory
`elements 32 may comprise other types of memory elements
`such as static random-access memory (SRAM). In addition,
`volatile memory elements 32 having bit widths of 4, 8, 16, 32, 65
`as well as other bit widths, are compatible with certain
`embodiments described herein. Volatile memory elements 32
`
`6
`compatible with certain embodiments described herein have
`packaging which include, but are not limited to, thin small(cid:173)
`outline package (TSOP), ball-grid-array (BGA), fine-pitch
`BGA (FBGA), micro-BGA (f.LBGA), mini-BGA (mBGA),
`and chip-scale packaging (CSP).
`In certain embodiments, the second plurality of non-vola(cid:173)
`tile memory elements 42 comprises one or more flash
`memory elements. Types of flash memory elements 42 com(cid:173)
`patible with certain embodiments described herein include,
`but are not limited to, NOR flash, NAND flash, ONE-NAND
`flash, and multi-level cell (MLC). For example, in the block
`diagram of FIG. 1, the second memory bank 40 comprises
`512 MB of flash memory organized as four 128 Mbx8 NAND
`flash memory elements 42. In addition, non-volatile memory
`elements 42 having bit widths of 4, 8, 16, 32, as well as other
`bit widths, are compatible with certain embodiments
`described herein. Non-volatile memory elements 42 compat(cid:173)
`ible with certain embodiments described herein have pack(cid:173)
`aging which include, but are not limited to, thin small-outline
`package (TSOP), ball-grid-array (BGA), fine-pitch BGA
`(FBGA), micro-BGA (f.LBGA), mini-BGA (mBGA), and
`chip-scale packaging (CSP).
`FIG. 2 is a block diagram of an example memory module
`10 with ECC (error-correcting code) having a volatile
`memory subsystem 30 with nine volatile memory elements
`32 and a non-volatile memory subsystem 40 with five non-
`volatile memory elements 42 in accordance with certain
`embodiments described herein. The additional memory ele(cid:173)
`ment 32 of the first memory bank 30 and the additional
`memory element 42 of the second memory bank 40 provide
`the ECC capability. In certain other embodiments, the volatile
`memory subsystem 30 comprises other numbers of volatile
`memory elements 32 (e.g., 2, 3, 4, 5, 6, 7, more than 9). In
`certain embodiments, the non-volatile memory subsystem 40
`comprises other numbers of non-volatile memory elements
`42 (e.g., 2, 3, more than 5).
`Referring to FIG. 1, in certain embodiments, the logic
`element 70 comprises a field-programmable gate array
`(FPGA). In certain embodiments, the logic element 70 com(cid:173)
`prises an FPGA available from Lattice Semiconductor Cor(cid:173)
`poration which includes an internal flash. In certain other
`embodiments, the logic element 70 comprises an FPGA
`available from another vendor. The internal flash can improve
`the speed of the memory system 10 and save physical space.
`Other types of logic elements 70 compatible with certain
`embodiments described herein include, but are not limited to,
`a programmable-logic device (PLD), an application-specific
`integrated circuit (ASIC), a custom-designed semiconductor
`device, a complex programmable logic device (CPLD). In
`50 certain embodiments, the logic element 70 is a custom device.
`In certain embodiments, the logic element 70 comprises vari(cid:173)
`ous discrete electrical elements, while in certain other
`embodiments, the logic element 70 comprises one or more
`integrated circuits. FIG. 3 is a block diagram of an example
`55 memory module 10 having a microcontroller unit 60 and
`logic element 70 integrated into a single controller 62 in
`accordance with certain embodiments described herein. In
`certain embodiments, the controller 62 includes one or more
`other components. For example, in one embodiment, an
`60 FPGA without an internal flash is used and the controller 62
`includes a separate flash memory component which stores
`configuration information to program the FPGA.
`In certain embodiments, the at least one circuit 52 com(cid:173)
`prises one or more switches coupled to the volatile memory
`subsystem 30, to the controller 62, and to the host computer
`(e.g., via the interface 22, as schematically illustrated by
`FIGS. 1-3). The one or more switches are responsive to sig-
`
`Petitioners SK hynix Inc., SK hynix America In