United States Patent
`Mojoli et al.
`
`[19]
`
`[11]
`
`[451
`
`Patent Number:
`
`Date of Patent:
`
`4,615,040
`
`Sep. 30, 1986
`
`[54] HIGH SPEED DATA COMMUNICATIONS
`SYSTEM
`
`[75]
`
`[73]
`[211
`
`[22]
`
`[51]
`[52]
`
`[531
`
`[56]
`
`Inventors: Luigi F. Mojoli, Vimercate; Angelo
`F. Olivieri, Dovera, both of Italy
`Coenco Ltd., Great Britain
`Appl. No.: 620,580
`
`Assignee:
`
`Filed:
`
`Jun. 14, 1984
`
`Int. Cl.4 .................................. .. H04B 7/02
`U.S. Cl. ........................................ 375/40; 375/58;
`375/60; 375/100; 375/103; 375/111; 455/59;
`455/133
`Field of Search ....................... 375/38, 40, 58, 60,
`375/100, 103, 106, 111; 455/59, 61, 52, 133,
`134, 135, 65, 307, 312; 371/36, 68; 340/825.01;
`364/718, 726, 825; 328/14; 370/100
`References Cited
`U.S. PATENT DOCUMENTS
`3,794,921
`2/1974 Unkauf ...........
`4,015,205
`3/1977 Ikeda et al.
`4,063,174 12/1977 Das Gupta et al.
`4,246,655
`1/1981 Parker ............
`4,410,955 10/1983 Burke et al.
`4,499,585
`2/1985
`
`OTHER PUBLICATIONS
`
`Article entitled “An LS1 FSSK (MSK) Modem”, by R.
`Matyas, C. Jagger, S. Sunter and P. Jeans, published in
`1981, IEEE.
`
`Article entitled “A ROM Controlled LS1 Sequencer for
`Digital Data Subscriber Loop Transmission Equip-
`ment” by T. Ohyama, T. Cotoda and A. Takada, pub-
`lished in 1981, IEEE.
`
`Article entitled “An Integrated Circuit Digital Signal
`Processor” by J. Boddie, G. Daryanani, L. Eldumian,
`
`R. Gadenz, J. Thompson and S. Walters, published in
`1980, IEEE.
`
`Yoshida, Komalgi, Morita, “System Design and New
`Techniques For An Over—Water 100 KM Span Digital
`Radio”(l983).
`Carlton, “Digital Transmission Over Troposcatter
`Links Using Independent Sideband Diversity”.
`Campbell & R. P. Coutts, “Outage Prediction of Digital
`Radio Systems" (1982).
`Bello, “A Troposcatter Channel Model”, 17 IEEE
`Transactions on Communications Technology”, Apr.
`1969, at 130.
`
`Wilkens, “Four—Port 2-GHz Digital Radio Provides 96
`Message Circuits in 3.5 MHz without Multiplexer”
`(1975).
`Feher, “Digital Modulation Techniques in an Interfer-
`ence Environment”, 9 EMC Encyclopedia Series (Don
`White Consultants, Inc., 1984).
`Feher, “Digital Communications: Microwave Applica-
`tions” (Prentice—Hall Inc.), pp. 119-121.
`Primaty Examiner—Benedict V. Safourek
`Attorney, Agent, or Firm—Brumbaugh, Graves,
`Donohue & Raymond
`[57]
`ABSTRACT
`
`An improved data transmission system has a transmitter
`which includes a modulator responsive to a synthesized
`modulating signal, which provides for transmission of
`data substreams on parallel subchannels, for example,
`by using subcarrier frequencies. At the receiver the
`subcarriers are received and data is selected from the
`received subcarriers at two diverse receivers. In addi-
`tion, there are provided signals added to the transmitted
`data for retiming the data at the receiver.
`
`35 Claims, 21 Drawing Figures
`
`DATA (IA)
`SERVICE (IA)
`
`DATA (18)
`SERVICE (IBI
`
`DATA (I6)
`SERVICE NC 1
`
`DATA (ID)
`SERVICE (ID)
`
`ME
`'1CIRCUIT
`|14D
`
`Aruba Networks et al. Exhibit 1005 Page 00001
`
`

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`U.S. Patent
`
`Sep. 30, 1986
`
`Sheet 1 of9
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`4,615,040
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`
`Page 00002
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`

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`U.S. Patent
`
`Sep. 30, 1986
`
`Sheet2 of9
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`4,615,040
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`66
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`SCRAM BLER
`
`DIFFERENTIAL
`CODING AND
`SER TO PAR
`CONVERSION
`
`CONTROL
`
`DATA (IA)
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`Page 00003
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`

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`US. Patent
`
`Sep. 30, 1986
`
`Sheet3 of9
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`4,615,040
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`Page 00004
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`

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`U.S. Patent
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`Sep. 30, 1986
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`Sheet4 of9
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`4,615,040
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`D2 D3 D4 D5 D6 D7 D8
`IC9
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`Page 00005
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`U.S. Patent
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`Sep. 30, 1986
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`Sheet5 of9
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`4,615,040
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`208
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`Page 00006
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`U.S. Patent
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`Sep. 30, 1986
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`U.S. Patent
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`Sep. 30, 1986
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`Sheet7 of9
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`4,615,040
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`

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`U.S. Patent
`
`Sep. 30,
`
`1986
`
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`4,615,040
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`Page 00010
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`

`
`1
`
`HIGH SPEED DATA COMMUNICATIONS
`SYSTEM
`
`4,615,040
`
`10
`
`BACKGROUND OF THE INVENTION
`
`This invention relates to transmission of digital data,
`and particularly to transmission of data with high data
`rates over a dispersive medium.
`Digital data, comprising either computer information
`or digitized analog information, such as digital signals
`derived from telephone channels, is often transmitted
`over line-of-sight microwave links or via tropospheric
`scattering links between a transmitter and a receiver.
`Typical links of this type are shown in simplified form
`in FIGS. 1 and 2.
`FIG. 1 represents a line-of-sight communication link
`between a transmitting station 30 and a receiving station
`32. Transmissions between the transmitter 30 and the
`receiver 32 follow both a line-of-sight path 34 and one
`or more time variant additional paths, such as path 36
`which results from refractive effects of the atmosphere.
`There may also be transmission paths which result from
`ground or sea reflections. In the case of digital data
`transmission, difficulties arise in such a line-of-sight
`system where the mean delay of the second path 36 with
`respect to the first path 34 is greater than 0.02 times the
`symbol time of the data transmission.
`
`30
`
`35
`
`FIG. 2 is a simplified illustration of a tropospheric
`scattering transmission system wherein a transmitter 38
`transmits a signal which is scatterd by the troposphere
`and received by a remote receiver 40. In this type of
`system there are usually multiple paths between the
`transmitter 38 and the receiver 40. There are usually a
`sufficient number of transmission paths that transmis-
`sion time differences among the paths cannot be easily
`deflned,_bl1t is usually expressed in terms of an RMS
`delay related to the delay spectrum of the received
`power. For simplication, the drawing of FIG. 2 shows
`only two paths, labeled 42 and 44, but those skilled in
`the art will recognize that these are among a large num-
`ber of present paths. In a tropospheric transmission
`system for digital signals, problems arise when the RMS
`deviation value of the delay spectrum exceeds 0.l to 0.2
`times the symbol time. Accordingly, high data transmis-
`sion speeds also present difficulties in this type of sys-
`tem.
`
`It has been suggested in a published article that multi-
`path difficulties arising from the transmission of high
`speed digital data be alleviated by increasing the symbol
`time through the use of parallel transmission channels.
`In a paper entitled “System Design and New Tech-
`niques For an Overwater 100 Kilometer Span Digital
`Radio”, the authors Yoshiva et al. describe a system
`wherein a stream of digital data at a rate of 200 megabits
`per second is divided into four substreams, each of
`which is transmitted on a different carrier using 16
`QAM modulation. The effect of this design is not only
`to increase the symbol time by the use of the 16 QAM
`modulation technique, but also to increase the symbol
`time by providing a slower transmission rate of data on
`each of four subcarriers. The spectral characteristics of
`this system are illustrated in FIG. 3b.
`»
`If a signal is modulated onto a single carrier with a
`high data rate, a spectral characteristic of the transmit-
`ted signal will be a single broad spectrum about the
`carrier frequency, as illustrated by curve 46 in FIG. 3a.
`In the system ‘described by Yoshiva et al., the data is
`modulated into four subcarriers 48A, 48B, 48C and
`
`55
`
`60
`
`65
`
`2
`48D, each of which has a narrower spectral range be-
`cause of the lower data rate of the signal. The present
`invention relates to a transmission system of this type,
`wherein digital data in a digital data stream is separated
`into substreams of data at a lower data rate. The sub-
`streams are used to separately modulate subcarriers or
`other component signals which are transmitted in paral-
`lel to a receiver at which the substreams are derived
`from component carriers and reassembled into an out-
`put data stream.
`It is an object of the present invention to provide an
`improved transmissions system for the high speed trans-
`mission of digital data over a dispersive medium.
`It is a further object of the present invention to pro-
`vide such a system having improved diversity charac-
`teristics.
`_
`It is a further object of the present invention to pro-
`vide such a system having a modulator which reduces
`intersymbol interference caused by components of the
`system.
`
`It is a further object of the present invention to pro-
`vide such a system having improved data stream timing
`techniques to enable the efficient reconstruction of a
`data stream following parallel transmission of data sub-
`streams on different channels.
`
`SUMMARY OF THE INVENTION
`
`In accordance with the present invention there is
`provided a system for transmission and reception of a
`serial stream of digital data from a first location to a
`second location. The system includes means at the first
`location’ for converting the serial data stream into a
`number N of first parallel data substreams. There is also
`provided a number N of modulators at the first location
`for modulating a plurality of component signals each
`with one of the parallel data substreams. Means are
`provided for transmitting the modulated component
`signals to the second location. Each of the component
`signals is transmitted to the second location by at least
`two transmission channels. At the second location there
`are provided at least 2 N demodulators, each for de-
`modulating one of the component signals from one of
`the transmission channels. There is also provided at the
`second location a switching means for selecting the
`output of one of the demodulators for each of the modu-
`lated component signals thereby deriving a number N
`of second parallel data substreams each corresponding
`to one of the first data substreams. Finally, there is
`provided means for converting the N second parallel
`data substreams into an output serial data stream.
`In an exemplary embodiment of the system, the mod-
`ulators modulate a plurality of component signals each
`of which has a selected frequency within a frequency
`band. The component signals may be transmitted from
`the first location to the second location in the form of
`subcarriers of a composite signal. The two transmission
`channels between the first and second location may be
`channels which have different paths in space, different
`frequency bands or different polarities. The switching
`means may be responsive to signals which are represen-
`tative of the amplitude of the component signals as
`received at the second location or may be responsive to
`signals derived from the received signals representing
`the bit error rate of the transmission channels for each
`component signal.
`In accordance with another aspect of the present
`invention there is provided a system for the transmis-
`
`Page 00011
`
`

`
`4,615,040
`
`3
`sion of a serial stream of digital data from a first location
`to a second location. The system includes means at the
`first
`location which is responsive to the serial data
`stream for providing a plurality of N parallel data sub-
`streams, each of the substreams comprising a series of 5
`data frames, and each of the data frames including a
`data frame timing signal and a predetermined quantitiy
`of digital data. The first location is also provided with N
`modulators, each for modulating a component signal
`with one of the N data substreams. There is provided
`means for transmitting the modulated component sig-
`nals to a second location wherein there‘ is located N
`demodulators for demodulating the modulated compo-
`nent signals to derive therefrom the N parallel data
`substreams. Means are provided at the second location,
`responsive to the frame timing signals in the demodu-
`lated data substreams for retiming the digital data in the
`substreams, and there is provided means, responsive to
`the retimed substream digital data, for generating an
`output serial stream of digital data.
`In a typical embodiment a frame timing signal com-
`prises a selected sequence of digital bits, which is the
`same for each frame within a substream. The retiming
`means include a comparator for comparing the digital
`bits in each of the substreams to the selected sequence.
`The retiming means can also include means which are
`responsive to the timing signals in two or more sequen-
`tial data frames. The retiming means can also include a
`first-in-first-out memory for digital data having separate
`data-in and data-out clock inputs, and having a first
`memory channel for data signals and a second memory
`channel for signals derived from the frame timing sig-
`nals.
`In accordance with another aspect of the present
`invention, useful in a system for transmission of a stream
`of digital data between remote locations, the system
`having signal filtering characteristics, there is provided
`signal forming apparatus which includes a register for
`storing digital data bits in the data stream in an arrange-
`ment corresponding to the order of the bits in the
`stream. There is also provided a counter responsive to
`supplied clock signals and a programmed digital data
`memory having first address inputs coupled to the regis-
`ter and second address inputs coupled to the counter.
`The programmed data values in the memory corre-
`spond to sequential values of a synthesized modulating
`signal. The data values are selected to provide a synthe-
`sized modulating signal with spectral characteristics
`dependent on the data bits in the register which com-
`pensate for the signal filtering characterisics of the sys-_
`tem. Finally, there is provided a digital to analog con-
`verter responsive to data values from the memory.
`The signal forming apparatus can be used to form a
`modulating signal which is used to modulate a carrier.
`In an exemplary embodiment the digital data bits occur
`at a bit clock rate, and the register comprises a shift
`register which is clocked at the bit clock rate. The
`counter can be an N-bit digital counter which is sup-
`plied with clock signals which occur at a rate which
`usually is 2” times the bit clock rate. In a preferred
`embodiment
`the memory is programmed with data
`values which are selected to compensate for spectral
`amplitude and group delay characteristics of the sys-
`tem.
`
`For a better understanding of the present invention,
`together with other further objects, reference is made to
`the following description, taken in conjunction with the
`
`4
`accompanying‘ drawings, and its scope will be pointed
`out in the appended claims.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a simplified diagram of a data transmission
`system for line-of-sight communications showing multi-
`ple transmission paths.
`FIG. 2 is a simplified diagram of tropospheric data
`communication system showing multiple transmission
`paths.
`FIG. 3a is a graph showing spectral amplitude of a
`modulated signal for a data communication system sig-
`nal using a single carrier.
`FIG. 3b is a graph showing spectral amplitude of a
`modulated composite signal for a data communication
`system using multiple modulated component subcarri-
`ers.
`
`FIG. 4 is a block diagram of a transmitter for a data
`communication system, in accordance with the present
`invention.
`FIG. 5 is a block diagram of a modulator useful in a
`transmitter for a data communication system in accor-
`dance with the present invention.
`FIG. 6 is a block diagram of a receiver for a data
`communication system in accordance with the present
`invention.
`FIG. 7 is a block diagram of a frame timing signal
`detecting circuit useful in a receiver for a data commu-
`nication system in accordance with the present inven-
`tion.
`FIG. 8 is a block diagram of a demodulator useful in
`a receiver for a data communication system in accor-
`dance with the present invention.
`FIG. 9 is a block diagram of a data substream retim-
`ing arrangement useful in a receiver for a data commu-
`nication system in accordance with the present inven-
`tion.
`FIG. 10 is a simplified diagram indicating the ar-
`rangement of a frame of data in a data sub-substream of
`a data communication system in accordance with the
`present invention.
`FIG. 11 is a block diagram of a switching means
`useful in a receiver in a data communication system in
`accordance with the present invention.
`FIG. 12 is a schematic diagram of a series to parallel
`data conversion apparatus useful in a transmitter for a
`data communication system in accordance with the
`present invention.
`FIG. 13 is a circuit diagram of a scrambler useful in a
`transmitter for a data communication system in accor-
`dance with the present invention.
`'
`FIG. 14 is a schematic diagram of a series to parallel
`converter and differential coding circuit useful
`in a
`transmitter for a data communication system in accor-
`dance with the present invention.
`FIG. 15 is a circuit diagram showing a modulating
`circuit useful in a transmitter for a data communication
`system in accordance with the present invention.
`FIG. 16 is a circuit diagram of a modulator useful in
`a transmitter for a data communication system in accor-
`dance with the present invention.
`FIG. 17 is a circuitdiagram of a parallel to series
`converter and descrambling circuit useful in a receiver
`for a data communication system in accordance with
`the present invention.
`FIG. 18 is a circuit diagram of a timing signal decod-
`ing circuit useful in a receiver for a data communication
`system in accordance with the present invention.
`
`Page 00012
`
`

`
`’ 4,615,040
`
`5
`FIG. 19 is a circuit diagram of a timing arrangement
`useful in a receiver for a data communication system in
`accordance with the present invention.
`FIG. 20 is a circuit diagram of a retiming circuit
`useful in a receiver for a data communication system in
`accordance with the present invention.
`
`6
`provide 2 or more separate receivers one for each trans-
`mission channel, as will be further discussed.
`FIG. 5 is a further detailed description of one of the
`modulators 58 which is used in the transmitter of FIG.
`4. Each of the data substreams from the bit insertion
`circuit 54 is provided to a scrambler 66, and thereafter
`to a differential coding and serial to parallel conversion
`circuit 68. The scrambler 66 provides a randomization
`and scrambling of the bits in the serial data substream.
`The differential coding circuit provides differential
`bit—to-bit encoding and a conversion from the serial data
`substrearn to two serial data sub-substreams which are
`used for quadrature phase shift keying (QPSK) modula-
`tion' in the embodiment of the modulator 58 shown in
`FIG. 5. The sub-substreams are designated P and Q for
`the in-phase and quadrature phase modulating signals,
`for QPSK modulation. The sub-substreams are at a rate
`approximately one eighth the rate of the data stream,
`providing a QPSK signal with a symbol rate slightly
`greater than 256 ldlobits per second. The two sub-sub-
`streams are provided to shift registers 70 and 72, which
`are shifted to provide a parallel output of six time se-
`quential bits of the data sub-substreams for the modula-
`tor. The shifting of shift registers 70 and 72 is offset in
`phase so that the QPSK modulated signal is offset in
`modulation to avoid zero amplitude transitions. The
`parallel outputs of shift registers 70 and 72 are provided
`as 6 bit address signals to memories 74 and 76. The
`parallel signals include the current phase shift data bit,
`three previous data bits and two subsequent data bits.
`Memories 74 and 76 have 9 address bit inputs, which
`includes the 6 bits of data from shift registers 70 and 72,
`as well as 3 bits of address information provided from
`counter 82. Counter 82 is cycled by clock 80, which is
`run at a rate which is 8 times the rate at which the bits
`are shifted in shift registers 70 and 72. Accordingly
`counter 82 cycles through the 3 output bits provided as
`addresses to memories 74, 76 during each shift of shift
`registers 70 and 72. Generally the rate for clock 80 is
`21” times the shift clock rate, where M is the number of
`bits in counter 82.
`
`15
`
`25
`
`35
`
`DESCRIPTION OF THE INVENTION
`The present invention will be described with refer-
`ence to an exemplary embodiment, which is described
`in detail below and shown in FIGS. 4 through 20. Re-
`ferring to FIG. 4 there is shown a block diagram of a
`transmitter in accordance with the invention for trans- ,
`mitting a serial stream of digital data. The digital data
`stream, for example, data at a rate of 2048 kilobits per
`second is provided to input terminal 50. The serial data
`stream is provided to a serial to parallel converter 52,
`which divides the data, bit by bit, into 4 data substreams
`each at a rate of 512 kilobits per second. The 4 data
`substreams are provided to bit insertion logic 54, which
`is also provided with data on a service channel at termi-
`nal 56. The 4 data substreams, with the additional in-
`serted bits, as will be described, are thereafter provided
`to modulators 58A, 58B, 58C, and 58D. Each of these
`modulators is provided with a local oscillator interme-
`diate frequency signal tuned at a different frequency.
`‘ The different frequencies are designated fl, f2, f3 and f4.
`In the embodiment shown, these frequencies are:
`f1=69,479 Khz.
`i2=69,826 Khz.
`i3=70,l72 Khz.
`f4=70,5l9 Khz.
`Each of the modulators 58 in the FIG. 4 transmitter is of
`special design as will be described further in this appli-
`cation. The local oscillators provide component inter-
`mediate frequency carrier signals, which are modulated
`by modulators 58A through 58D to provide modulated
`component signals which’ comprise subcarriers which
`are combined in adder circuit 60. Following combina-
`tion the subcarrier signals are up-converted, amplified
`in amplifier 62 and provided to transmitting antenna 64.
`In accordance with one feature of the present inven-
`tion,
`the system includes two different
`transmission
`channels between the transmitter location and the re-
`ceiver location. Accordingly, it may be appropriate to
`provide one transmission channel which uses a signal
`with vertical polarization between a transmitting and a
`receiving antenna and a second transmission channel
`which uses horizontal polarization. In this case the same
`signal may be transmitted by the transmitter of FIG. 4
`on both polarizations at a first location and separately
`received at a second location using a polarization sensi-
`tive antenna and two receivers. In another arrangement
`there may be provided a single transmitter, of the type
`shown in FIG. 4 at the first location, and two receivers
`at the second location, each connected to its own an-
`tenna, the two antennas being arranged with separation
`in space or receiving angle to provide what is known as
`space diversity or angle diversity. In still another ar-
`rangement there may be one transmitting antenna and
`one receiving antenna, and a second transmission chan-
`nel may be provided by modulating a different carrier
`frequency with the subcarrier frequencies which are
`combined in adding circuit 60, so that the subcarrier
`frequencies are transmitted on two frequency separated
`RF channels. In some of these events only a single
`transmitter is necessary, while in other arrangements 2
`transmitters may be used. In any event it is desirable to
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`Memory 74 is programmed with data corresponding
`to the time sequential amplitude of a digitally synthe-
`sized modulating signal which is appropriate for the
`spectral transfer characteristics of the transmitter and
`receiver of the system of the present invention. The
`programming information in memories 74 and 76 each
`take into account the inter-symbol-interference which is
`caused by the preceding and following bits of data to be
`transmitted, which are included in the parallel data
`provided as address signals to memories 74 and 76, as
`well as the transfer characteristic of the filters used in
`the transmitter and the receiver of the invention. Ac-
`cordingly, the modulating signal which is generated by
`D-to-A converters 84 and 86 is preconditioned to com-
`pensate for the signal spectrum transfer characteristics
`of the entire system. The programming of memories 74
`and 76 is ideally arranged to satisfy the Nyquist criteria,
`that is, to have an equivalent transfer characteristic of
`the entire system, which has constant group delay and
`an amplitude of one-half at Nyquist frequency, and has
`a roll-off factor which follows a cosine roll-off pattern,
`with a roll-off factor of 0.4. Of special importance and
`benefit in the system of the present invention, this pre-
`conditioning is optimized for each modulated subcarrier
`signal and its associated filtering circuits. Prior art sys-
`tems use filters which approximate Nyquist condition
`for the amplitude but not for group delay. Group delay
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`4,615,040
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`7
`equalizers are consequently inserted to reduce the
`group delay impairments. By synthesizing the modulat-
`ing signal in the transmitter, by the use of programmed
`memories, it is possible to arrange the modulating signal
`to compensate not only for amplitude spectral charac-
`teristics of the system transfer function, but also for
`irregularities in the group delay characteristics of the
`system, and therefore to provide excellent correction by
`predistortion of the modulating signal for system ano-
`malyes. Particularly important among these anomalyes
`are the effect of intersymbol interference caused by the
`various filters used in the system. The output of memo-
`ries 74 and 76 are arranged with a one-half symbol time
`displacement for off-set QPSK to avoid a zero crossing
`of the two phase modulated signal. These output signals
`are in the form of 8 bits of digital information, which
`presents the amplitude of the synthesized modulating
`signal. The output of memory 74 is provided to D-to-A
`converter 84 and thereafter to smoothing filter 88. The
`output of smoothing filter 88 is provided to mixer 94 20
`which is supplied with a local oscillator signal from
`oscillator 92. Likewise the output from memory 76 is
`provided by D-to-A converter 86 to smoothing filter 90
`and mixer 98. The output of local oscillator 92 is pro-
`vided to mixer 98 by 90° phase shift circuit 96 to pro-
`vide for QPSK modulation of the intermediate fre-
`quency component carrier which is provided by oscilla-
`tor 92. The in-phase and quadrature phase modulated
`component signals are combined in adder 100 and there-
`after provided through low pass filter 102 to output
`terminal 104. The filter 102 is provided to eliminate
`higher harmonics of the IF signal frequency. Terminal
`104 of FIG. 5 is provided as one of the inputs to adder
`circuit 60 of FIG. 4 wherein the four QPSK modulated
`component signals from modulators 58A through 58D 35
`are combined to provide a composite signal which is
`up-converted, amplified and transmitted via antenna 64.
`Further details of circuits used in the transmitter of '
`FIG. 4 are shown in FIGS. 12, 13, 14 and 15. FIG. 12
`shows the series-to-parallel converter circuit 52, which 40
`includes a shift register 180 and a first-in-first-out mem-
`ory 182. The first-in-first-out memory 182 is provided to
`enable a change in clock rate from the reconstructed, or
`provided, clock of the input serial data stream, to a
`clock rate which is slightly higher than one-quarter the
`original data clock rate, in order to enable the insertion
`into the data substreams of additional signals to provide
`for frame timing signals and service channel signals. In
`the illustrative embodiment the incoming data stream,
`which provides 2048 kilobits per second is divided by
`shift register 180 into four substreams at a rate of 512
`kilobits per second. These substreams are provided to
`FIFO memory 182, which has a formatted output at the
`instantaneous rate of 544 kilobits per second. This out-
`put is divided into data bursts of 256 bits per burst, each
`burst having intervals for the provision of service chan-
`nel data bits and frame timing signal bits. These burst
`are output on leads A, B, C and D corresponding to the
`four data substreams.
`The devices connected to outputs A, B, C and D are
`three state devices, whereby the outputs can be pro-
`vided with data substream signals from FIFO memory
`182, timing and parity signals from shift registers 188A
`through 188D or service channel data signals from
`FIFO memory 192. The data substream signals which
`are output from FIFO memory 182 are provided to
`logic circuits 184 and 186 for the generation of parity bit
`signals. The parity bit signals are provided to shift regis-
`
`8
`ters 188A through 188D which are also provided with
`selected coding signals for the generation of frame tim-
`ing signals. These are provided through buffer amplifi-
`ers of a three state type to output leads A, B, C and D.
`Service channel signals are provided by shift register
`190 to FIFO memory 182, which is also a three state
`device connected to output leads A, B, C and D. The
`output on lines A, B, C and D are at a rate of 544 kilobits
`per second. These output signals are substreams which
`comprise frames of data substream signals, frame timing
`signals and service channel data signals. The substream
`rate is 544 kilobits per second and provides 512 kilobits
`per second of data, as well_as 16 kilobits per second of
`frame timing and parity information and 16 kilobits per
`second of service channel information. Each frame is
`provided with a burst of 128 bits of data, followed by 8
`bits of service channel, followed by a 128 bit data burst,
`followed by 7 bits of frame timing information and 1
`parity bit.
`The four substreams A, B, C and D are further di-
`vided into sub-substreams P and Q, as previously noted,
`in differential coding and series to parallel conversion
`circuit 68 so that each sub-substream modulates one
`phase of a component signal. Those skilled in the art
`know that proper differential coding allows the receiver
`to correctly recognize P and Q components. In the
`particular case of offset modulation, P and Q transitions
`are shifted in time and a simplified differential coding
`can be used.
`FIG. 13 shows a scrambling circuit 66 which is pro-
`vided for each of the data substreams A, B, C and D.
`The scrambling circuit 66 is provided with a substream
`of data on input terminal 194 which is connected by
`logic circuitry to shift register 196. The output at termi-
`nal 198 is a scrambled data substream at the same rate.
`The scrambling of the data substream assures a random-
`ization of transistions of digital data, which facilitates
`data transmission and synchronization at the receiver.
`Each of the data substreams A, B, C and D from
`scrambler output port 198 is provided to one of the
`labeled inputs A, B, C and D of the series to parallel
`converter and differential coding circuit 68 which is
`shown in FIG. 14. This circuit includes flip-flop inte-
`grated circuits 200 and 202, logic gates 204 and output
`flip-flip circuits 206 and 208. The outputs of this circuit,
`which are labeled AP, AQ, BP, BQ, etc. comprise the
`in-phase and quadrature phase modulating sub-sub-
`streams of digital data which include sequential frames
`as illustrated in FIG. 10. These sub-substreams are each
`provided to modulating circuits.
`A modulation signal synthesizing circuit for sub-
`stream A is shown in FIG. 15. Similar circuits are pro-
`vided for the other substreams. The circuit of FIG. 15
`includes shift registers 70 and 72 which receive the
`in-phase and quadrature phase data sub-substreams for
`the A channel (signals AP and AQ). These data sub-sub-
`streams are output from shift registers 70 and 72 as
`parallel 6 bit information to address inputs of memories
`74 and 76, which in the illustrated embodiment are
`programmable read-only memories. It should be under-
`stood that in some embodiments, adaptability of the
`circuits of the present invention may be provided by the
`use of random access memory in the circuit of FIG. 15,
`so that the memory contents may be changed for vary-
`ing transmission conditions or varying operation of
`either the transmitter or the receiver.
`An additional set of address inputs to memory 74 and
`76 is provided by common counting circuit 82 which
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`provides a 3 bit output counting signal. The